cyclic redundancy check generator

Cyclic Redundancy Check

ABSTRACT:

Cyclic redundancy check is a traditionally used error detection method in

networks. This project proposes an algorithm that generates another

algorithm. The produced algorithm calculates cyclic redundancy check

using a predefined polynomial. CRC modulo-2 division operation and uses

a polynomial as an input. The proposed algorithm works when the

polynomial is in the form) (4 0 ∑ − = + N i i i N XCX. The proposed

algorithm takes a polynomial as input and produces another algorithm.

The produced algorithm calculates CRC for a given input stream of bytes.

The algorithm is more useful under memory constrained conditions. This

project also describes existing cyclic redundancy check (CRC) methods.

Proposed algorithm is been compared with the existing algorithms. The

algorithm reduces number of data exchanges between register variables

and cache memory. The proposed algorithm reduces the amount of data

transfers from cache memory. Hence the algorithm is faster than the

existing algorithms. The algorithm is more useful in areas of applications

like micro-controller applications; Bluetooth enabled services, mobile

services, VLSI technologies in which available cache and EEPROM

memory is limited. The cyclic redundancy check is also used in file

integrity checking.

Department of Electronics and Telecommunication Engineering, Lakshmi Narain College of Technology, Bhopal

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PROJECT SPECIFICATION:

The concept of the CRC as an error-detecting code gets complicated

when an implementer or standards committee turns it into a practical

system. Here are some of the complications:

Sometimes an implementation prefixes a fixed bit pattern to the

bitstream to be checked. This is useful when clocking errors might

insert 0-bits in front of a message, an alteration that would

otherwise leave the check value unchanged.

Sometimes an implementation appends n 0-bits (n being the size

of the CRC) to the bitstream to be checked before the polynomial

division occurs. This has the convenience that the remainder of the

original bitstream with the check value appended is exactly zero, so

the CRC can be checked simply by performing the polynomial

division on the received bitstream and comparing the remainder

with zero.

Sometimes an implementation exclusive-ORs a fixed bit

pattern into the remainder of the polynomial division.

Bit order: Some schemes view the low-order bit of each byte as

"first", which then during polynomial division means "leftmost",

which is contrary to our customary understanding of "low-order".

This convention makes sense when serial-port transmissions are

CRC-checked in hardware, because some widespread serial-port

transmission conventions transmit bytes least-significant bit first.


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Byte order: With multi-byte CRCs, there can be confusion over

whether the byte transmitted first (or stored in the lowest-

addressed byte of memory) is the least-significant byte (LSB) or the

most-significant byte (MSB). For example, some 16-bit CRC

schemes swap the bytes of the check value.

Omission of the high-order bit of the divisor polynomial: Since

the high-order bit is always 1, and since an n-bit CRC must be

defined by an (n+1)-bit divisor which overflows an n-bit register,

some writers assume that it is unnecessary to mention the divisor's

high-order bit.

Omission of the low-order bit of the divisor polynomial: Since the

low-order bit is always 1, authors such as Philip Koopman represent

polynomials with their high-order bit intact, but without the low-

order bit (the or 1 term). This convention encodes the polynomial

complete with its degree in one integer.

These complications mean that there are three common ways to express a polynomial as an integer: the first two, which are mirror images in binary, are the constants found in code; the third is the number found in Koopman's papers. In each case, one term is omitted. So the

polynomial may be transcribed as:

0x3 = 0b0011, representing (MSB-first code)

0xC = 0b1100, representing (LSB-first code)

0x9 = 0b1001, representing (Koopman notation)


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CHAPTER 1


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INTRODUCTION

INTRODUCTION:

The cyclic redundancy check, or CRC, is a technique for

detecting errors in digital data, but not for making corrections

when errors are detected. It is used primarily in data

transmission. In the CRC method, a certain number of check

bits, often called a checksum, are appended to the message


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being transmitted. The receiver can determine whether or not

the check bits agree with the data, to ascertain with a certain

degree of probability whether or not an error occurred in

transmission. If an error occurred, the receiver sends a

“negative acknowledgement” (NAK) back to the sender,

requesting that the message be retransmitted.

The technique is also sometimes applied to data storage

devices, such as a disk drive. In this situation each block on the

disk would have check bits, and the hardware might

automatically initiate a reread of the block when an error is

detected, or it might report the error to software.

The material that follows speaks in terms of a “sender” and a

“receiver” of a “message,” but it should be understood that it

applies to storage writing and reading as well.


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CHAPTER 2

THEORY


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THEORY:

The CRC is based on polynomial arithmetic, in particular, on computing the remainder of dividing one polynomial in GF(2) (Galois field with two elements) by another. It is a little like treating the message as a very large binary number, and computing the remainder on dividing it by a fairly large prime such as 232 – 5. Intuitively, one would expect this to give a reliable checksum.

A polynomial in GF(2) is a polynomial in a single variable x whose coefficients are 0 or 1. Addition and subtraction are done modulo 2—that is, they are both the same as the exclusive or operator. For example, the sum of the polynomials

x3+x+1 and x4+ x3+ x2+ x

is x4+ x2 + 1, as is their difference. These polynomials are not usually written coefficient of 1.

Multiplication of such polynomials is straightforward. The product of one coefficient by another is the same as their combination by the logical and operator, and the partial products are summed using exclusive or. Multiplication is not needed to compute the CRC checksum. Division of polynomials over GF(2) can be done in much the same way as long division of polynomials over the integers. Below is an example.

The reader might like to verify that the quotient of x4+ x3 + 1 multiplied by the divisor of x3+x+1 plus the remainder of x2 + 1 equals the dividend.

The CRC method treats the message as a polynomial in GF(2). For example, the message 11001001, where the order of transmission is from left to right (110…) is treated as a representation of the polynomial x7+ x6+ x3 + 1. The sender and receiver agree on a certain fixed polynomial called the generator polynomial. For example, for a 16-bit CRC the CCITT (Comité Consultatif Internationale Télégraphique et Téléphonique) has chosen the polynomial x16 + x12 + x5 + 1,


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which is now widely used for a 16-bit CRC checksum. To compute an r-bit CRC checksum, the generator polynomial must be of degree r.

The sender appends r 0-bits to the m-bit message and divides the resulting polynomial of degree m+r–1 by the generator polynomial. This produces a remainder polynomial of degree r – 1 (or less). The remainder polynomial has r coefficients, which are the checksum. The quotient polynomial is discarded. The data transmitted (the code vector) is the original m-bit message followed by the r-bit checksum.

There are two ways for the receiver to assess the correctness of the transmission. It can compute the checksum from the first m bits of the received data, and verify that it agrees with the last r received bits. Alternatively, and following usual practice, the receiver can divide all the m+r received bits by the generator polynomial and check that the r-bit remainder is 0. To see that the remainder must be 0, let M be the polynomial representation of the message, and let R be the polynomial representation of the remainder that was computed by the sender. Then the transmitted data corresponds to the polynomial Mxr – R (or, equivalently, 1. Since renamed the ITU-TSS (International Telecommunications Union-Telecommunications Standards Sector). By the way R was computed, we know that Mxr +R= QG + R, where G is the generator polynomial and Q is the quotient (that was discarded). Therefore the transmitted data, Mxr – R, is equal to QG, which is clearly a multiple of G. If the receiver is built as nearly as possible just like the sender, the receiver will append r 0-bits to the received data as it computes the remainder R. But the received data with 0-bits appended is still a multiple of G, so the computed remainder is still 0.

That’s the basic idea, but in reality the process is altered slightly to correct for such deficiencies as the fact that the method as described is insensitive to the number of leading and trailing 0-bits in the data transmitted. In particular, if a failure occurred that caused the received data, including the checksum, to be all-0, it would be accepted.


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Choosing a “good” generator polynomial is something of an art, and beyond the scope of this text. Two simple observations: For an r-bit checksum, G should be of degree r, because otherwise the first bit of the checksum would always be 0, which wastes a bit of the checksum. Similarly, the last coefficient should be 1 (that is, G should not be divisible by x), because otherwise the last bit of the checksum would always be 0 (because Mxr = QG + R, if G is divisible by x, then R must be also). The following facts about generator polynomials are proved in [PeBr] and/or [Tanen]:

If G contains two or more terms, all single-bit errors are detected.

If G is not divisible by x (that is, if the last term is 1), and e is the least positive integer such that G evenly divides xe + 1, then all double errors that are within a frame of e bits are detected. A particularly good polynomial in this respect is x15+x14+ 1, for which e = 32767.

If x + 1 is a factor of G, all errors consisting of an odd number of bits are Detected.

An r-bit CRC checksum detects all burst errors of length = r. (A burst error of length r is a string of r bits in which the first and last are in error, and the intermediate r – 2 bits may or may not be in error.) The generator polynomial x + 1 creates a checksum of length 1, which applies even parity to the message. (Proof hint: For arbitrary k = 0, what is the remainder of dividing xk by x + 1?)

It is interesting to note that if a code of any type can detect all double-bit and single-bit errors, then it can in principle correct single-bit errors. To see this, suppose data containing a single-bit error is received. Imagine complementing all the bits, one at a time. In all cases but one, these results in a double-bit error, which are detected. But when the erroneous bit is complemented, the data is error-free, which is recognized. In spite of this, the CRC method does not seem to be used for


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single-bit error correction. Instead, the sender is requested to repeat the whole transmission if any error is detected.

CHAPTER 3


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SOURCE CODE

SOURCE CODE:

-- Specification -- File Name : CRC8_DATA16.vhd -- Description : CRC Engine ENTITY -- Clock : Positive Edge -- Reset : Active Low-- First Serial : MSB -- Data Bus Width : 16 bits -- Polynomial : (0 1 2 8) -- Date : 26-Apr-2012


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LIBRARY IEEE ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;USE ieee.std_logic_unsigned.all ;

ENTITY crc_gen IS PORT( clock : IN STD_LOGIC; reset : IN STD_LOGIC; soc : IN STD_LOGIC; data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); data_valid : IN STD_LOGIC; eoc : IN STD_LOGIC; crc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); crc_valid : OUT STD_LOGIC );END crc_gen;

ARCHITECTURE behave OF crc_gen IS

SIGNAL crc_r : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL crc_c : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL crc_i : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL crc_const : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";

BEGIN

crc_i <= crc_const when soc = '1' else crc_r;

crc_c(0) <= data(0) XOR data(6) XOR data(7) XOR data(8) XOR crc_i(0) XOR data(12) XOR data(14) XOR crc_i(6) XOR crc_i(4); crc_c(1) <= data(0) XOR data(1) XOR data(9) XOR crc_i(1) XOR data(13) XOR data(15) XOR crc_i(7) XOR crc_i(5) XOR data(6) XOR data(12) XOR data(14) XOR crc_i(6) XOR crc_i(4); crc_c(2) <= data(0) XOR data(1) XOR data(2) XOR data(10) XOR crc_i(2) XOR data(13) XOR data(15) XOR crc_i(7) XOR crc_i(5) XOR data(6) XOR data(8) XOR crc_i(0) XOR data(12) XOR crc_i(4); crc_c(3) <= data(1) XOR data(2) XOR data(3) XOR data(11) XOR crc_i(3) XOR data(14) XOR crc_i(6) XOR data(7) XOR data(9) XOR crc_i(1) XOR data(13) XOR crc_i(5); crc_c(4) <= data(2) XOR data(3) XOR data(4) XOR data(12) XOR crc_i(4) XOR data(15) XOR crc_i(7) XOR data(8) XOR data(10) XOR crc_i(2) XOR data(14) XOR crc_i(0) XOR crc_i(6); crc_c(5) <= data(3) XOR data(4) XOR data(5) XOR data(13) XOR crc_i(5) XOR data(9) XOR data(11) XOR crc_i(3) XOR data(15) XOR crc_i(1) XOR crc_i(7);


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crc_c(6) <= data(4) XOR data(5) XOR data(6) XOR data(14) XOR crc_i(6) XOR data(10) XOR data(12) XOR crc_i(4) XOR crc_i(2); crc_c(7) <= data(5) XOR data(6) XOR data(7) XOR data(15) XOR crc_i(7) XOR data(11) XOR data(13) XOR crc_i(5) XOR crc_i(3);

crc_gen_process : PROCESS(clock, reset) BEGIN IF(reset = '0') THEN crc_r <= "00000000" ; ELSIF( clock 'EVENT AND clock = '1') THEN IF(data_valid = '1') THEN crc_r <= crc_c; END IF; END IF; END PROCESS crc_gen_process;

crc_valid_gen : PROCESS(clock, reset) BEGIN IF(reset = '0') THEN crc_valid <= '0'; ELSIF( clock 'EVENT AND clock = '1') THEN IF(data_valid = '1' AND eoc = '1') THEN crc_valid <= '1'; ELSE crc_valid <= '0'; END IF; END IF; END PROCESS crc_valid_gen;

crc <= crc_r;

END behave;


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CHAPTER 4

ALGORITHM


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ALGORITHM:

The process employs a shift register, which we denote by CRC. This is of length r (the degree of G) bits, not r + 1 as you might expect. When the subtractions (exclusive or’s) are done, it is not necessary to represent the high-order bit, because the high-order bits of G and the quantity it is being subtracted from are both 1. The division process might be described informally as follows:

Initialize the CRC register to all 0-bits.

Get first/next message bit m.

If the high-order bit of CRC is 1,

Shift CRC and m together left 1 position, and XOR the result with the lower-order r bits of G.

Otherwise, Just shift CRC and m left 1 position. If there are more message bits, go back to get the next one.

It might seem that the subtraction should be done first, and then the shift. It would be done that way if the CRC register held the entire generator polynomial, which in bit form is r + 1 bits. Instead, the CRC register holds only the low-order r bits of G, so the shift is done first, to align things properly.

Below is shown the contents of the CRC register for the generator G =x3+x+1 and the message M =x7+ x6+ x5+ x2+ x. Expressed in binary, G =1011 and M=11100110.

000 Initial CRC contents. High-order bit is 0, so just shift in first message bit. 001 High-order bit is 0, so just shift in second message bit, giving: 011 High-order bit is 0 again, so just shift in third message bit, giving: 111 High-order bit is 1, so shift and then XOR with 011, giving: 101 High-order bit is 1, so shift and then XOR with 011, giving:


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001 High-order bit is 0, so just shift in fifth message bit, giving: 011 High-order bit is 0, so just shift in sixth message bit, giving: 111 High-order bit is 1, so shift and then XOR with 011, giving: 101 There are no more message bits, so this is the remainder.

These steps can be implemented with the (simplified) circuit shown in Figure 14–2, which is known as a feedback shift register.

The three boxes in the figure represent the three bits of the CRC register. When a message bit comes in, if the high-order bit (x2 box) is 0, simultaneously the message bit is shifted into the x0 box, the bit in x0 is shifted to x1, the bit in x1 is shifted to x2, and the bit in x2 is discarded. If the high-order bit of the CRC register is 1, then a 1 is present at the lower input of each of the two exclusive or gates. When a message bit comes in, the same shifting takes place but the three bits that wind up in the CRC register have been exclusive or’ed with binary 011. When all the message bits have been processed, the CRC holds M mod G.

If the circuit of Figure 14–2 were used for the CRC calculation, then after processing the message, r (in this case 3) 0-bits would have to be fed in. Then the CRC register would have the desired checksum, Mxr mod G. But, there is a way to avoid this step with a simple rearrangement of the circuit.

Instead of feeding the message in at the right end, feed it in at the left end, r steps away, as shown in Figure 14–3. This has


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X2

X1

X0

++


the effect of pre-multiplying the input message M by xr. But pre-multiplying and post-multiplying are the same for polynomials. Therefore, as each message bit comes in, the CRC register contents are the remainder for the portion of the message processed, as if that portion had r 0-bits appended.

CHAPTER 5


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X2

X1

X0

++


SIMULATION AND TESTING

SIMULATION AND TESTING:


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Fig 5.1

CHAPTER 6


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RESULT AND CONCLUSION

RESULT AND CONCLUSION:

1. for the first clock pulse: Data polynomial of 16 bit of decimal equivalent is 57930 and the crc generated is (00000000)2

2. for the second clock pulse: Data polynomial of 16 bit of decimal equivalent is 50799 and the crc generated is (10011001)2

3. for the third clock pulse: Data polynomial of 16 bit of decimal equivalent is 42359 and the crc generated is (00011011)2


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cyclic redundancy check generator

Documents

byte order

polynomial division

proposed algorithm

divisor polynomial

produced algorithm

predefined polynomial

check value appended

check value unchanged