Cyclic Combinational CircuitsCyclic Combinational Circuitsand Other Novel Constructsand Other Novel Constructs

Marc D. RiedelCalifornia Institute of Technology

Marrella splendens Cyclic circuit

...

...

...

...

(500 million year old Trilobite) (novel construct)

),,( 11 mxxf a

),,( 12 mxxf a

),,( 1 mn xxf a

inputs outputs

The current outputs depend only on the current inputs.

Combinational Circuits

1x

2x

mx

miix

,,1

{0,1}

nj

mjf

,,1

{0,1}{0,1}:

combinationallogic

1x

2x

3x

4x

5x

6x

NAND

OR

ANDAND

AND

NOR

1

0

0

1

1

1

1

0

1

0

0

1

Acyclic (i.e., feed-forward) circuits are always combinational.

Combinational Circuits

Acyclic (i.e., feed-forward) circuits are always combinational.Are combinational circuits always acyclic?

“Combinational networks can never have feedback loops.”“A combinational

circuit is a directed acyclic graph (DAG)...”

Combinational Circuits

1

0

0

1

1

1

NAND

OR

ANDAND

AND

NOR

1

0

1

0

0

1

Acyclic (i.e., feed-forward) circuits are always combinational.Are combinational circuits always acyclic?

“Combinational networks can never have feedback loops.”“A combinational

circuit is a directed acyclic graph (DAG)...”

Combinational Circuits

Designers and EDA tools follow this practice.

Circuits with Cycles

a

b

x

c

d

x

AND

AND

OR

OR

AND

OR

)))((( 1fxcdxab1f

x0

0

0

a

b

c

d

AND

AND

OR

OR

AND

OR

x

x

0

)))((( 1fcdxab1f 0

Circuits with Cycles

x

x

x

0

0

a

b

c

d

AND

AND

OR

OR

AND

OR

0

)))((( 1fxcdab1f

Circuits with Cycles

x1 x1

x

x

a

b

c

d

AND

AND

OR

OR

AND

OR

1

11

)))((( 1fcdab1f

Circuits with Cycles

1

1

x

x

x

a

b

c

d

AND

AND

OR

OR

AND

OR

1

))(( cdab1f

)(2 abxcdf

Circuit is cyclic yet combinational;computes functions f1 and f2 with 6 gates.

An acyclic circuit computing these functions requires 8 gates.

Circuits with Cycles

A cyclic topology permits greater overlap in the computation of the two functions:

x

x

a

b

c

d

AND

AND

OR

OR

AND

OR

There is no feedback in a functional sense.Circuit is cyclic yet combinational;computes functions f1 and f2 with 6 gates.

An acyclic circuit computing these functions requires 8 gates.

)(2 abxcdf

Circuits with Cycles

x ))(( cdab1f

Prior Work (early era)

• Kautz and Huffman discussed the concept of feedback in logic circuits (in 1970 and 1971, respectively).

• McCaw and Rivest presented simple examples (in 1963 and 1977, respectively).

Prior Work (later era)

• Stok observed that designers sometimes introduce cycles among functional units (in 1992).

• Malik, Shiple and Du et al. proposed techniques for analyzing such circuits (in 1994,1996, and 1998 respectively).

Cyclic Circuits: Key Contributions

Practice

Theory

• Devised efficient techniques for analysis and synthesis.

• Formulated a precise model for analysis.

• Implemented the ideas and demonstrated they are applicable for a wide range of circuits.

• Provided constructions and lower bounds proving thatcyclic designs can be more compact.

Outline of Talk

• Analysis: circuit model, symbolic techniques.• Synthesis: framework, implementation, and results.• Theory: circuit complexity (limited).

• Application of circuit design techniques to biological systems.

Current & Future Research Directions

Cyclic Circuits

• Fixed-point analysis over a ternary-valued (0, 1, ?) domain.

• Regardless of the prior values.• Independently of all timing assumptions.

Circuit Model

A circuit must produces definite output values for each input combination (in the “care” set):

• A sequence of controlling values always determines the output.

Formally:

Informally:

Controlling Values

a “controlling” input

full set of“non-controlling” inputs

unknown/undefinedoutput

0

?0

AND 11

11

??

AND

AND

Each gate has delay in [0, td]

The arrival time at a gate output is determined:

• either by the earliest controlling input;

AND

13

02

06

03

Timing Model

arrival times

(Assume td = 1)

The arrival time at a gate output is determined:

• either by the earliest controlling input;

AND

13

12

16

• or by the latest non-controlling input.

17

Timing Model

Each gate has delay in [0, td]

(Assume td = 1)

13

02

06

03

Analysis• Functional Analysis: determine what is computed.• Timing Analysis: determine how long it takes to compute it.

jgj

i lli )fanin(

max

+ 1level:

l1 = 1

l2 = 1

l3 = 2

l5 = 2

l4 = 3a

b

a

b

g1

g2

g3

g4

g5

c

c

10

10

10

10

10

12

02

12

11

01

10

Analysis

Explicit analysis:

ORAND AND

1x 2x 3x

1f 2f 3f

1x 2x 3x 1f 2f 3f

• Functional Analysis: determine what is computed.• Timing Analysis: determine how long it takes to compute it.

ORAND AND

1x 2x 3x

1f 2f 3f

00 00 00

01 02 01

Analysis

1x 2x 3x

00 00 00

1f 2f 3f

01 02 01

Explicit analysis:

• Functional Analysis: determine what is computed.• Timing Analysis: determine how long it takes to compute it.

02

0000 00

01 02 01

ORAND AND

00 1000

01 03

m inputs explict evaluation intractable combinations;m2

Analysis

1x 2x 3x

00 00 00

1f 2f 3f

01 02 01

00 00 10 01 02 03

Explicit analysis:

• Functional Analysis: determine what is computed.• Timing Analysis: determine how long it takes to compute it.

3f

1x 2x 3x

1f 2f

ORAND AND

Analysis

00

02

1000

01 03

Symbolic analysis:binary, multi-terminal decision diagrams.

(See “Timing Analysis of Cyclic Circuits,” IWLS, ’04)

0

1

1f

1x

01 02

2x

3x

?13

• Functional Analysis: determine what is computed.• Timing Analysis: determine how long it takes to compute it.

Synthesis

• General methodology: optimize by introducing feedback in the substitution/minimization phase.

• Developed a tool called CYCLIFY within Berkeley SIS Environment.

• Optimizations are significant and applicable to a wide range of circuits.

Design a circuit to meet a specification.

Example: 7 Segment Display

Inputs a

b

c

d

e

f

g

Output

1001

0001

1110

0110

1010

0010

1100

0100

1000

00000123 xxxx

9

8

7

6

5

4

3

2

1

0

Example: 7 Segment Display

g

f

e

d

c

b

a

)(

)(

))((

))((

))((

)(

))((

20321

10102321

2012103210

102213321

210203321

21310

302321320

xxxxx

xxxxxxxx

xxxxxxxxxx

xxxxxxxxx

xxxxxxxxx

xxxxx

xxxxxxxxx

a

b

c

d

e

f

g

Output

Substitution

Basic minimization/restructuring operation: express a function in terms of other functions.

Substitute b into a:

(cost 9)a ))(( 302321320 xxxxxxxxx

(cost 8)

Substitute c into a:(cost 5)

Substitute c, d into a:(cost 4)

a )( 323212 bxxxxxbx

a cxxcx 321

a dccx 1

Substitution/Minimization

Berkeley SISTool

a ))(( 302321320 xxxxxxxxx

},,,{ fdcb

target function

substitutional set

a dccx 1

low-cost expression

Acyclic Substitution

g

f

e

b

a

c

d

Select an acyclic topological ordering:

g

f

e

d

c

b

a

g

f

d

c

b

a

edcaxx 21

dccx 1

xxxxxxxxx 102213321 ))((

dxxxxxx 102320 )(

cdxx 10 )(

Select an acyclic topological ordering:

Area (literal count): 37

Acyclic Substitution

e 3cxb d

ba f

Acyclic Substitution

Select an acyclic topological ordering:

Nodes at the top benefit little from substitution.

g

f

d

c

b

a

edcaxx 21

dccx 1

xxxxxxxxx 102213321 ))((

dxxxxxx 102320 )(

cdxx 10 )(

e 3cxb d

ba f

Cyclic Substitution

How can we find a cyclic solution that is combinational?

g

f

d

c

b

a

e ?

22213

321322

312322

)(

)(

)(

xxxxxc

xxxxxxb

xxxxxxa

323 xxbxa

Target32 xxcba

Candidates

3221 )( xxxxca

Simpler Example:

Cyclic Substitution

22213

321322

312322

)(

)(

)(

xxxxxc

xxxxxxb

xxxxxxa

Target

Candidates

Simpler Example:

1322 cxxxxb

3 1xa xcb

313 xxxab

Cyclic Substitution

22213

321322

312322

)(

)(

)(

xxxxxc

xxxxxxb

xxxxxxa

Target

Candidates

Simpler Example:

321 xxaxc 32 xxbac

Cyclic Substitution

“Break-Down” approach

• Search performed outside space of combinational solutions.

• Terminates on optimal solution*

cost 12

cost 13 cost 12

cost 13combinational

cost 14

Branch and Bound

“Build-Up” approach

cost 17

cost 16cost 15not combinational

cost 14

Branch (without Bounding)

cost 13best solution

Search performed inside space of combinational solutions

g

f

e

d

c

b

a

Area (literal count): 34

Combinational solution:

x e0

bxa 3

gxxxax 1023 )(

axxex 321 )( exxxxxx 312320 )(

cxxcx 301

xxxfx 1023 )( f

Example: 7 Segment Display

• Limit the density of edges a priori• Limit breadth• Tunnel depth-wise (with backtracking)

Branch and Bound

Heuristics:

• for target functions, configurations)2(2nOn

Large search space:

(See “The Synthesis of Cyclic Circuits,” DAC, ’03)

Optimization for AreaNumber of NAND2/NOR2 gates for

Berkeley SIS vs. CYCLIFYsolutions

Benchmark Berkeley SIS CYCLIFY Improvement

5xp1 203 182 10.34%

ex6 194 152 21.65%

planet 943 889 5.73%

s386 231 222 3.90%

bw 302 255 15.56%

cse 344 329 4.36%

pma 409 393 3.91%

s510 514 483 6.03%

duke2 847 673 20.54%

styr 858 758 11.66%

s1488 1084 1003 7.47%

Based on “script.rugged” sequence and technology mapping.

Optimization for Area and Delay

Berkeley SIS CYCLIFY

benchmark Area Delay Area Improvement Delay Improvement

p82 175 19 167 4.57% 15 21.05%

t1 343 17 327 4.66% 14 17.65%

in3 599 40 593 1.00% 33 17.50%

in2 590 34 558 5.42% 29 14.71%

5xp1 210 23 180 14.29% 22 4.35%

bw 280 28 254 9.29% 20 28.57%

s510 452 28 444 1.77% 24 14.29%

s1 566 36 542 4.24% 31 13.89%

duke2 742 38 716 3.50% 34 10.53%

s1488 1016 43 995 2.07% 34 20.93%

s1494 1090 46 1079 1.01% 39 15.22%

Number of NAND2/NOR2 gates and the Delay ofBerkeley SIS vs. CYCLIFY solutions

Based on “script.delay” sequence and technology mapping.

Practice

• Improvements in area (and consequently power) and delay are significant.

• Similar improvements were obtained for larger scale circuits: e.g., the ALU of an 8051 microprocessor.

• E.D.A. companies (Altera and Synopsys) have expressed strong interest.

Theory

Prove that cyclic implementations can have fewer gates than equivalent acyclic ones.

cycliccircuit

acycliccircuit

(optimal)

functions, n variables,m fan-in gatesd

gates n more than gatesn

6/7 Construction

Cyclic Circuit: 6 functions, 3 variables, 6 fan-in 2 gates.

AND OR AND OR AND OR

1x 2x 3x 1x 2x 3x

1f 2f 3f 4f 5f 6f)( 321 xxx )( 312 xxx )( 213 xxx

321 xxx 312 xxx 213 xxx

Acyclic Circuit: at least 7 fan-in 2 gates.

1x2x

3x

Acyclic Circuit: at least 7 fan-in 2 gates.

f1

1x

2x

3x

2x

3x

f2

f3

f4

f5

f6

Theory

• Exhibit a cyclic circuit that is optimal in terms of the number of gates, say with C(n) gates, for n variables.

• Prove a lower bound on the size of an acyclic circuit implementing the same functions, say A(n) gates.

Strategy:

Main Result:

)(2

1)( nAnC

Current & Future Research Interests

• Logic Synthesis and Verification: functional decomposition, symbolic data structures, cyclic decision diagrams.

• Novel Platforms: asynchronous models, nanotechnology, noisy/probabilistic gates.

• Computational Biology analysis of intracellular biochemical networks.