CY2304

3.3 V Zero Delay Buffer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document Number: 38-07247 Rev. *O Revised March 17, 2017

3.3 V Zero Delay Buffer

Features

■ Zero input-output propagation delay, adjustable by capacitiveload on FBK input

■ Multiple configurations

■ Multiple low-skew outputs

■ 10 MHz to 133 MHz operating range

■ 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz

■ Space-saving 8-pin 150-mil small outline integrated circuit(SOIC) package

■ 3.3 V operation

■ Industrial temperature available

Functional Description

The CY2304 is a 3.3 V zero delay buffer designed to distributehigh-speed clocks in PC, workstation, datacom, telecom, andother high performance applications.

The part has an on-chip phase-locked loop (PLL) that locks to aninput clock presented on the REF pin. The PLL feedback is

required to be driven into the FBK pin, and can be obtained fromone of the outputs. The input-to-output skew is guaranteed to beless than 250 ps, and output-to-output skew is guaranteed to beless than 200 ps.

The CY2304 has two banks of two outputs each.

The CY2304 PLL enters a power down state when there are norising edges on the REF input. In this mode, all outputs arethree-stated and the PLL is turned off, resulting in less than25 A of current draw.

Multiple CY2304 devices can accept the same input clock anddistribute it in a system. In this case, the skew between theoutputs of two devices is guaranteed to be less than 500 ps.

The CY2304 is available in two different configurations, asshown in Available Configurations. The CY2304-1 is the basepart, where the output frequencies equal the reference if there isno counter in the feedback path.

The CY2304-2 allows the user to obtain Ref and 1/2x or 2xfrequencies on each output bank. The exact configuration andoutput frequencies depends on which output drives the feedbackpin.

For a complete list of related documentation, click here.

PLL

CLKA1

CLKA2

CLKB1

REF

CLKB2

/2 Extra Divider (-2)

FBK

Logic Block Diagram

Available Configurations

Device FBK from Bank A Frequency Bank B Frequency

CY2304-1 Bank A or B Reference Reference

CY2304-2 Bank A Reference Reference/2

CY2304-2 Bank B 2 × Reference Reference

CY2304

Document Number: 38-07247 Rev. *O Page 2 of 17

Contents

Pin Configurations ........................................................... 3Pin Definitions .................................................................. 3Zero Delay and Skew Control .......................................... 4Maximum Ratings ............................................................. 5Operating Conditions ....................................................... 5Electrical Characteristics ................................................. 5Switching Characteristics ................................................ 6Operating Conditions ....................................................... 7Electrical Characteristics ................................................. 7Thermal Resistance .......................................................... 8Test Circuit ........................................................................ 8Switching Characteristics ................................................ 9Switching Waveforms .................................................... 10Ordering Information ...................................................... 11

Ordering Code Definitions ......................................... 11Package Diagram ............................................................ 12

Acronyms ........................................................................ 13Document Conventions ................................................. 13

Units of Measure ....................................................... 13Appendix: Silicon Errata for the Zero Delay Clock Buffers, CY2304 ......................... 14

Part Numbers Affected .............................................. 14CY2304 Errata Summary .......................................... 14CY2303 Qualification Status of fixed silicon .............. 14

Document History Page ................................................. 16Sales, Solutions, and Legal Information ...................... 17

Worldwide Sales and Design Support ....................... 17Products .................................................................... 17PSoC® Solutions ...................................................... 17Cypress Developer Community ................................. 17Technical Support ..................................................... 17

CY2304

Document Number: 38-07247 Rev. *O Page 3 of 17

Pin ConfigurationsFigure 1. 8-pin SOIC pinout

1234 5

876

REFCLKA1CLKA2

GND

VDD

FBK

CLKB1CLKB2

Pin Definitions

8-pin SOIC

Pin Signal Description

1 REF [1] Input reference frequency, 5 V tolerant input

2 CLKA1 [2] Clock output, Bank A

3 CLKA2 [2] Clock output, Bank A

4 GND Ground

5 CLKB1 [2] Clock output, Bank B

6 CLKB2 [2] Clock output, Bank B

7 VDD 3.3 V supply

8 FBK PLL feedback input

Notes1. Weak pull-down. 2. Weak pull-down on all outputs.

CY2304

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Zero Delay and Skew Control

Figure 2. REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins

To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output drivingthe FBK pin is driving a total load of 7 pF, with any additional load that it drives. The relative loading of this output (with respect to theremaining outputs) can adjust the input-output delay. This is shown in Figure 2.

For applications requiring zero input-output delay, all outputs including the one providing feedback must be equally loaded. Ifinput-output delay adjustments are required, use the graph shown in Figure 2 to calculate loading differences between the feedbackoutput and remaining outputs.

For zero output-output skew, be sure to load outputs equally. For further information on using CY2304, refer to the application noteAN1234 - Understanding Cypress’s Zero Delay Buffers.

CY2304

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Maximum Ratings

Supply voltage to ground potential ............. –0.5 V to +7.0 V

DC input voltage (except Ref) ........... –0.5 V to VDD + 0.5 V

DC input voltage REF ...................................... –0.5 V to 7 V

Storage temperature ............................... –65 °C to +150 °C

Junction temperature ................................................ 150 °C

Static discharge voltage (per MIL-STD-883, Method 3015) ......................... > 2000 V

Operating Conditions

For CY2304SXC Commercial Temperature Devices

Parameter Description Min Max Unit

VDD Supply voltage 3.0 3.6 V

TA Operating temperature (ambient temperature) 0 70 °C

CL Load capacitance (below 100 MHz) – 30 pF

Load capacitance (from 100 MHz to 133 MHz) – 15 pF

CIN Input capacitance [3] – 7 pF

tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic)

0.05 50 ms

Electrical Characteristics

For CY2304SXC Commercial Temperature Devices

Parameter Description Test Conditions Min Max Unit

VIL Input LOW voltage – 0.8 V

VIH Input HIGH voltage 2.0 – V

IIL Input LOW current VIN = 0 V – 50.0 A

IIH Input HIGH current VIN = VDD – 100.0 A

VOL Output LOW voltage [4] IOL = 8 mA (-1, -2) – 0.4 V

VOH Output HIGH voltage [4] IOH = –8 mA (-1, -2) 2.4 – V

IDD (PD mode) Power-down supply current REF = 0 MHz – 12.0 A

IDD Supply current Unloaded outputs, 100 MHz REF, Select inputs at VDD or GND

– 45.0 mA

Unloaded outputs, 66 MHz REF (-1, -2) – 32.0 mA

Unloaded outputs, 33 MHz REF (-1, -2) – 18.0 mA

Notes3. Applies to both REF clock and FBK. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production.

CY2304

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Switching Characteristics

For CY2304SXC Commercial Temperature Devices

Parameter [5] Name Test Conditions Min Typ Max Unit

t1 Output frequency 30 pF load, all devices 10 – 100 MHz

t1 Output frequency 15 pF load, -1, -2 devices 10 – 133.3 MHz

tDC Duty cycle [6] = t2 t1 (-1, -2) Measured at 1.4 V, FOUT = 66.66 MHz, 30-pF load

40.0 50.0 60.0 %

tDC Duty cycle [6] = t2 t1 (-2) Measured at 1.4 V, FOUT = 83.0 MHz, 15-pF load

40.0 50.0 60.0 %

tDC Duty cycle [6] = t2 t1 (-1, -2) Measured at 1.4 V, FOUT < 50 MHz, 15-pF load

45.0 50.0 55.0 %

t3 Rise time[6] (-1, -2) Measured between 0.8 V and 2.0 V, 30-pF load

– – 2.20 ns

t3 Rise time [6] (-1, -2) Measured between 0.8 V and 2.0 V, 15-pF load

– – 1.50 ns

t4 Fall time [6] (-1, -2) Measured between 0.8 V and 2.0 V, 30-pF load

– – 2.20 ns

t4 Fall time [6] (-1, -2) Measured between 0.8 V and 2.0 V, 15 pF load

– – 1.50 ns

t5 Output-to-output skew on same Bank (-1, -2) [6]

All outputs equally loaded – – 200 ps

Output bank A to output bank B skew (-1)

All outputs equally loaded – – 200 ps

Output bank A to output bank B skew (-2)

All outputs equally loaded – – 400 ps

t6 Skew, REF rising edge to FBK rising edge [6]

Measured at VDD/2 – 0 250 ps

t7 Device-to-device skew [6] Measured at VDD/2 on the FBK pins of devices

– 0 500 ps

tJ Cycle-to-cycle jitter [6] (-1) Measured at 66.67 MHz, loaded outputs, 15-pF load

– 90 175 ps

Measured at 66.67 MHz, loaded outputs, 30-pF load

– – 200 ps

Measured at 133.3 MHz, loaded outputs, 15-pF load

– – 100 ps

tJ Cycle-to-cycle jitter [6] (-2) Measured at 66.67 MHz, loaded outputs 30-pF load

– – 400 ps

Measured at 66.67 MHz, loaded outputs 15-pF load

– – 375 ps

tLOCK PLL lock time [6] Stable power supply, valid clocks presented on REF and FBK pins

– – 1.0 ms

Notes5. All parameters are specified with loaded output.6. Parameter is guaranteed by design and characterization. Not 100% tested in production.

CY2304

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Operating Conditions

For CY2304SXI Industrial Temperature Devices

Parameter Description Min Max Unit

VDD Supply voltage 3.0 3.6 V

TA Operating temperature (ambient temperature) –40 85 °C

CL Load capacitance (below 100 MHz) – 30 pF

Load capacitance (from 100 MHz to 133 MHz) – 15 pF

CIN Input capacitance – 7 pF

Electrical Characteristics

For CY2304SXI Industrial Temperature Devices

Parameter Description Test Conditions Min Max Unit

VIL Input LOW voltage – 0.8 V

VIH Input HIGH voltage 2.0 – V

IIL Input LOW current VIN = 0 V – 50.0 A

IIH Input HIGH current VIN = VDD – 100.0 A

VOL Output LOW voltage [7] IOL = 8 mA (-1, -2) – 0.4 V

VOH Output HIGH voltage [7] IOH = –8 mA (-1, -2) 2.4 – V

IDD (PD mode) Power-down supply current REF = 0 MHz – 25.0 A

IDD Supply current Unloaded outputs, 100 MHz, Select inputs at VDD or GND

– 45.0 mA

Unloaded outputs, 66 MHz REF (-1, -2) – 35.0 mA

Unloaded outputs, 33 MHz REF (-1, -2) – 20.0 mA

Note7. Parameter is guaranteed by design and characterization. Not 100% tested in production.

CY2304

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Thermal Resistance

Parameter [8] Description Test Conditions 8-pin SOIC Unit

θJA Thermal resistance (junction to ambient)

Test conditions follow standard test methods andprocedures for measuring thermal impedance, inaccordance with EIA/JESD51.

140 °C/W

θJC Thermal resistance (junction to case)

54 °C/W

Test CircuitFigure 3. Test Circuit # 1

0.1 F

VDD

0.1 F

VDD

CLK OUT

CLOAD

OUTPUTS

GNDGND

Test circuit for all parameters

Note8. These parameters are guaranteed by design and are not tested.

CY2304

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Switching Characteristics

for CY2304SXI Industrial Temperature Devices

Parameter [9] Name Test Conditions Min Typ Max Unit

t1 Output frequency 30-pF load, All devices 10 – 100 MHz

t1 Output frequency 15-pF load, All devices 10 – 133.3 MHz

tDC Duty cycle [10] = t2 t1 (-1, -2) Measured at 1.4 V, FOUT = 66.66 MHz,30-pF load

40.0 50.0 60.0 %

tDC Duty cycle [10] = t2 t1 (-2) Measured at 1.4 V, FOUT = 83.0 MHz, 15-pF load

40.0 50.0 60.0 %

tDC Duty cycle [10] = t2 t1 (-1, -2) Measured at 1.4 V, FOUT < 50 MHz, 15-pF load

45.0 50.0 55.0 %

t3 Rise time [10] (-1, -2) Measured between 0.8 V and 2.0 V, 30-pF load

– – 2.50 ns

t3 Rise time [10] (-1, -2) Measured between 0.8 V and 2.0 V, 15-pF load

– – 1.50 ns

t4 Fall time [10] (-1, -2) Measured between 0.8 V and 2.0 V, 30-pF load

– – 2.50 ns

t4 Fall time [10] (-1, -2) Measured between 0.8 V and 2.0 V, 15-pF load

– – 1.50 ns

t5 Output-to-output skew on same bank (-1, -2) [10]

All outputs equally loaded – – 200 ps

Output bank A to output bank B skew (-1)

All outputs equally loaded – – 200 ps

Output bank A to output bank B skew (-2)

All outputs equally loaded – – 400 ps

t6 Skew, REF rising edge to FBK rising edge [10]

Measured at VDD/2 – 0 250 ps

t7 Device-to-device skew [10] Measured at VDD/2 on the FBK pins of devices

– 0 500 ps

tJ Cycle-to-cycle jitter [10] (-1) Measured at 66.67 MHz, loaded outputs, 15-pF load

– – 180 ps

Measured at 66.67 MHz, loaded outputs, 30-pF load

– – 200 ps

Measured at 133.3 MHz, loaded outputs, 15-pF load

– – 100 ps

tJ Cycle-to-cycle jitter [10] (-2) Measured at 66.67 MHz, loaded outputs, 30-pF load

– – 400 ps

Measured at 66.67 MHz, loaded outputs, 15-pF load

– – 380 ps

tLOCK PLL lock time [10] Stable power supply, valid clocks presented on REF and FBK pins

– – 1.0 ms

Notes9. All parameters are specified with loaded output.10. Parameter is guaranteed by design and characterization. Not 100% tested in production.

CY2304

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Switching WaveformsFigure 4. Duty Cycle Timing

Figure 5. All Outputs Rise/Fall Time

Figure 6. Output-Output Skew

Figure 7. Input-Output Skew

Figure 8. Device-Device Skew

t1

t2

1.4 V 1.4 V 1.4 V

OUTPUT

t3

3.3 V

0 V0.8 V

2.0 V 2.0 V0.8 V

t4

1.4 V

t5

OUTPUT

OUTPUT1.4 V

VDD/2

t6

INPUT

FBK

VDD/2

VDD/2

VDD/2

t7

FBK, Device 1

FBK, Device 2

CY2304

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Ordering Code Definitions

Ordering Information

Ordering Code Package Type Operating Range

Pb-free

CY2304SXC-1 8-pin SOIC (150 Mils) Commercial

CY2304SXC-1T 8-pin SOIC (150 Mils) – Tape and Reel Commercial

CY2304SXI-1 8-pin SOIC (150 Mils) Industrial

CY2304SXI-1T 8-pin SOIC (150 Mils) – Tape and Reel Industrial

CY2304SXC-2 8-pin SOIC (150 Mils) Commercial

CY2304SXC-2T 8-pin SOIC (150 Mils) – Tape and Reel Commercial

CY2304SXI-2 8-pin SOIC (150 Mils) Industrial

CY2304SXI-2T 8-pin SOIC (150 Mils) – Tape and Reel Industrial

X = blank or T blank = Tube; T = Tape and Reel

X = 1 or 2

Temperature Range: X = C or IC = Commercial; I = Industrial

X = Pb-free

Package Type: S = 8-pin SOIC

Base Device Part Number

Company ID: CY = Cypress

2304CY S X - X TX

CY2304

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Package DiagramFigure 9. 8-pin SOIC (150 Mils) Package Outline, 51-85066

51-85066 *H

CY2304

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Acronyms Document Conventions

Units of MeasureAcronym Description

PLL Phase Locked Loop

SOIC Small Outline Integrated Circuit

Symbol Units of Measure

C degree Celsius

MHz megahertz

µA microampere

mA milliampere

ms millisecond

ns nanosecond

pF picofarad

ps picosecond

V volt

CY2304

Document Number: 38-07247 Rev. *O Page 14 of 17

Appendix: Silicon Errata for the Zero Delay Clock Buffers, CY2304

This section describes the errors, workaround solution and silicon design fixes for Cypress zero delay clock buffers belonging to thefamilies CY2304. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

CY2304 Errata Summary

CY2303 Qualification Status of fixed silicon

Product Status: In production

Qualification report last updated on 11/27/2012

http://www.cypress.com/?rID=72595

1. Start up lock time issue

■ Problem Definition

Output of CY2304 fails to locks within 1 ms upon power up (as per datasheet spec)

■ Parameters Affected

PLL lock time

■ Trigger Condition(s)

Start up

■ Scope of Impact

It can impact the performance of system and its throughput

■ Workaround

Apply reference input (RefClk) before power up (VDD). If RefClk is applied after power up, noise gets coupled on the output andpropagates back to the PLL causing it to take higher time to acquire lock. If reference input is present during power up, noise willnot propagate to the PLL and device will start up normally without problems.

■ Fix Status

This issue is due to design marginality. Two minor design modifications have been made to address this problem.a. Addition of VCO bias detector block as shown in the following figure keeps comparator power down till VCO bias is present and

thereby eliminating the propagation of noise to feedback.b. Bias generator enhancement for successful initialization.

Table 1. Part Numbers Affected

Part Number Device Variants

CY2304SXC-1 All Variants

CY2304SXC-1T All Variants

CY2304SXC-2 All Variants

CY2304SXC-2T All Variants

CY2304SXI-1 All Variants

CY2304SXI-1T All Variants

CY2304SXI-2 All Variants

CY2304SXI-2T All Variants

Items Part Number Fix Status

Start up lock time issue [CY2304] All Silicon fixed. New silicon available from WW 10 of 2013

CY2304

Document Number: 38-07247 Rev. *O Page 15 of 17

CY2304

Document Number: 38-07247 Rev. *O Page 16 of 17

Document History Page

Document Title: CY2304, 3.3 V Zero Delay BufferDocument Number: 38-07247

Rev. ECN Orig. of Change

Submission Date Description of Change

** 110512 SZV 12/11/01 Change from Spec number: 38-01010 to 38-07247

*A 112294 CKN 03/04/02 On Pin Configuration Diagram (p.1), swapped CLKA2 and CLKA1

*B 113934 CKN 05/01/02 Added Operating Conditions for CY2304SI-X Industrial Temperature Devices, p. 4

*C 121851 RBI 12/14/02 Power up requirements added to Operating Conditions Information

*D 308436 RGL 01/26/05 Added Lead-free Devices

*E 2542331 AESA 09/18/08 Updated template. Added Note “Not recommended for new designs.”Removed part number CY2304SI-2 and CY2304SI-2T.Changed Lead-Free to Pb-Free.Changed IDD (PD mode) from 12.0 to 25.0 A.Deleted Duty Cycle parameters for FOUT < 50.0 MHz for commercial and industrial devices.

*F 2673353 KVM / PYRS

03/13/09 Reverted IDD (PD mode) and Duty Cycle parameters back to the values in revision *D:Changed IDD (PD mode) from 25 to 12 A for commercial devices.Added Duty Cycle parameters for FOUT < 50.0 MHz for commercial and industrial devices.

*G 2906571 KVM 04/07/10 Removed parts CY2304SC-1, CY2304SC-1T, CY2304SC-2, CY2304SC-2T, CY2304SI-1, CY2304SI-1T from the ordering information table.Updated Package Diagram.

*H 3072674 BASH 10/27/2010 Corrected part number in all table titles (pages 3 to 5) from CY2304SC-X and CY2304SI-X to CY2304SXC and CY2304SXI.Removed “except t8” from Figure 7

*I 3162681 BASH 02/04/2011 Updated to new template.

*J 3204827 CXQ 03/24/2011 Added duty cycle spec for 83.0 MHz output condition.

*K 4018186 CINM 06/10/2013 Updated Package Diagram:spec 51-85066 – Changed revision from *D to *F.Added Appendix: Silicon Errata for the Zero Delay Clock Buffers, CY2304.

*L 4291190 CINM 02/25/2014 Updated to new template.Completing Sunset Review.

*M 4578443 AJU 11/25/2014 Updated Functional Description:Added “For a complete list of related documentation, click here.” at the end.

*N 5270465 PSR 05/13/2016 Added Thermal Resistance.Updated Package Diagram:spec 51-85066 – Changed revision from *F to *H.Updated to new template.

*O 5663902 PAWK 03/17/2017 Updated to new template.Completing Sunset Review.

Document Number: 38-07247 Rev. *O Revised March 17, 2017 Page 17 of 17

CY2304

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