cvd co-based metallization - applied materials · 2014. 7. 9. · liner and selective metal cap...
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1© 2014 Applied Materials, Inc. All rights reserved. Volume 12, Issue 2, 2014Nanochip Technology Journal
KEYWORDS
Barrier
Co
Cu
CVD
Electromigration
Gap Fill
Interconnect
Liner
Reliability
Aggressive interconnect scaling makes it highly challenging
for incumbent PVD barrier and seed processes to achieve
the coverage and adhesion required for void-free line and
via fill at 22nm and below. Shrinking geometries also
create higher current densities and greater propensity for
electromigration (EM) failures. Ultra-thin CVD Co liners
improve fill reliability and yield in small lines and vias, in
combination with PVD barrier and seed technology.
Depositing a post-planarization selective CVD Co cap
enhances interface adhesion between the Cu lines and
dielectric, reducing EM. Complete Cu encapsulation with
CVD Co maximizes performance benefits for <22nm node
fill and reliability.
Cu metallization in today’s microelectronic fabrication
involves depositing the Cu barrier and seed layers
by PVD followed by Cu electroplating to fill the
topography (Figure 1a). Each of these process steps
requires careful optimization to ensure successful
gap fill. Since the introduction of Cu interconnects at
the 130nm node, barrier and seed thicknesses have
been continuously scaled to enable void-free Cu fill
in ever-shrinking geometries.
Coverage, film continuity, and interface adhesion
between the barrier and seed layers play an important
role in determining the quality of the Cu fill.[1] Below the
22nm node, higher packing density, aggressive pitch
scaling, and complicated wiring layouts prompt a need
for even thinner barrier and Cu seed layers to achieve
flawless Cu fill. However, further thickness scaling
can render the already thin barrier and seed layers
discontinuous along feature sidewalls, which leads to
voids in the fill. A thin, conformal Co liner deposited
before the Cu seed layer significantly improves gap fill
in narrow interconnects (Figure 1b).
Shrinking interconnect geometries also induce reliability
degradation as Cu diffusion can occur under the influence
CVD Co-Based Metallization for <22nm Cu Interconnects
Figure 1. Conventional
Cu metallization must be
augmented by CVD Co to
ensure the gap-fill integrity
and EM lifetime required at
22nm and below.
Figure 1
TaN/Ta BarrierDeposition
Clean
Electroplating
Polishing
Cu Seed Deposition
≥28nm
Conventional Cu Metallization Scheme CVD Co-Based Cu Metallization Scheme
TaN BarrierDeposition
Clean
Cu Seed Deposition
Electroplating
Polishing
Co LinerDeposition
Selective Co Cap Deposition
(a) (b)
≤22nm
2© 2014 Applied Materials, Inc. All rights reserved. CVD Co-Based Metallization
of high electrical current in closely packed lines. The
interface between the Cu and dielectric barrier layer
plays a critical role in determining EM lifetime. The
use of alloy Cu seed layers to mitigate EM failures is
well known.[2] This approach relies on segregating the
alloy material towards the metal/dielectric barrier
interface to improve adhesion. While EM lifetimes can
be improved by increasing the alloy concentration, a
saturation effect is reached. Furthermore, increasing the
alloy concentration to drive segregation in narrow lines
can increase line resistance.[2] Selective deposition of a
Co cap layer on top of the planarized Cu interconnects
has proven to be an elegant way of reducing EM while
minimizing the increase in line resistance (Figure 1b).[3]
While depositing a thin Co liner and a thin selective Co
cap individually have improved gap-fill margin and EM
lifetime, respectively, implementing both liner and cap
results in complete encapsulation of the Cu line in Co,
which dramatically extends EM lifetime.[4]
IMPROVING Cu FILL In leading-edge geometries, line-of-sight PVD barrier
and seed deposition can lead to overhang buildup at
feature openings, making it extremely challenging for
these processes to achieve continuous thin-film coverage
on feature sidewalls. Roughness or discontinuities in
the liner along the sidewalls in turn result in rough Cu
seed morphology, rendering the stack vulnerable to void
formation during electroplating (Figure 2a).
While tantalum (Ta) has been the most reliable choice
of PVD liner material since the introduction of Cu
interconnects, a conformal liner with good Cu-wetting
properties is needed to improve Cu seed coverage and
thereby improve Cu fill at the 22nm node and below. A
liner’s capacity for wetting Cu is a strong function of its
contact angle and interfacial energy.[5] The lattice of the
liner material should also closely match the Cu lattice
to promote strong adhesion between barrier and seed.
Co exhibits a good lattice match with Cu.[6] Conformal,
ultra-thin CVD Co improves the wetting and continuity
of the Cu seed. Figure 2b shows gap-fill performance with
a <20Å CVD Co liner in a representative 10nm node
feature. A CVD Co liner offers the added advantage that
it can be polished using slurries deployed for polishing
Ta, thereby reducing the integration costs typically
associated with the introduction of new materials
into the process flow.[4] Also, the improved adhesion
between barrier and seed produced from using a Co
liner results in fewer post-CMP defects (Figure 2c).
The stack thickness of the PVD TaN barrier and CVD Co
liner can be optimized for the low line resistivity desired
in fabricating advanced interconnects.[7]
Studies of other materials for wetting layers (e.g.,
ruthenium and molybdenum) have been reported.[8]
However, optimization of electroplating and CMP is
needed to successfully integrate these new materials
into the back-end process flow.
Figure 2. (a) CVD Co liner
improves Cu seed coverage.
(b) Cu gap fill with Co liner
in self-aligned via at the
10nm node.
(c) Void-free post-CMP
defect performance with
CVD Co liner.
Figure 2
(b)
(a)
(c)Applied Materials internal data
Applied Materials internal data
Source: Reference 1.
Post-CMP Defects
TaN/Ta/Cu TaN/Co/Cu
100nm
30Å TaN/70Å Ta/100Å Cu 30Å TaN/15Å Co/100Å Cu
50nm50nm
With Co Liner Without Co Liner
3© 2014 Applied Materials, Inc. All rights reserved. CVD Co-Based Metallization
ENHANCING RELIABILITYAfter planarization, a combination of weak Cu/dielectric
interfacial adhesion and normal incidence of a high
electrical current at this weak interface can exacerbate
EM failures. A selective CVD Co cap immobilizes the Cu
atoms at the interface, thereby improving EM lifetime.
Unlike alloys, the CVD Co cap remains confined to
the Cu/dielectric interface. This promotes stronger
interface adhesion without degrading line resistance.
In addition, the deposition of CVD Co at this interface
is carefully tuned to bind exclusively to the Cu surface
avoiding metal entrapment in low-κ that will lead to
time dependent dielectric breakdown (TDDB) failures.[3]
At 22nm and below, depositing CVD Co as both liner and
selective metal cap (Figure 3) creates an encapsulating
“glue” layer for Cu interconnects that promotes robust
interconnect reliability.[9]
HIGH-VOLUME MANUFACTURINGBoth CVD Co liner and selective CVD Co capping films
are deposited by means of a gas-phase reaction of an
organometallic precursor with a reducing agent. The
reaction parameters (e.g., thermal regime, partial pressure
of the reacting molecules, and exposure times) in each
case are carefully optimized to balance the individual
film performance requirements with the appropriate
deposition rate required for optimal productivity.
Figure 4 demonstrates the production worthiness and
stability of the CVD Co liner process. Figure 5 shows
stable, repeatable performance for selective CVD Co
capping. Current efforts are focused on extending
process and hardware performance to meet 10nm
node development targets.
CONCLUSIONCu interconnect processing complexity increases for
small geometries as integrated circuits become more
advanced. PVD Cu barrier/seed processes are becoming
increasingly challenged to achieve the required step
coverage in these tiny trenches and vias. Concurrently,
performance-degrading EM is also a growing issue at
smaller geometries. CVD Co technology is alleviating
these roadblocks to Cu interconnect scaling beyond
the 22nm node. The combined use of CVD Co as both
liner and selective metal cap offers the most robust
interconnect reliability.
Figure 3
Lifetime (h)
0.1 1 100 100010
2
90
95
20
30
4050
10
5
98
60
70
80
Cum
ulat
ive
Failu
re P
roba
bilit
y (%
)
Source: Reference 9.
Conventional Solution
With CVD Co Liner
With CVD Co Liner andSelective CVD Co Cap
10x
1000x
Figure 4
Wafer Count
<3% WiW; <2% WtW 1σ NU% measured thickness on PVD TaN
0 1000 2000 7000 90008000 100003000 4000 5000 6000
0
17.5
12.5
7.5
5
2.5
10
20
15
0.00%
2.50%
5.00%
10.00%
7.50%
Average Thickness (Å)1σ NU%
CV
D C
o Li
ner
Thi
ckne
ss (
Å)
1σ N
U%
Figure 5
Wafer Count
<3% WiW; <1% WtW 1σ NU% measured thickness on Cu
0 2500 7500 100005000
0.00
16.00
8.00
4.00
20.00
12.00 Co on Cu ThicknessCo on Cu 1σ NU%Co on BDIIx Thickness
Sele
ctiv
e C
o A
vera
ge T
hick
ness
(Å
)
Figure 3. Completely
encapsulating Cu interconnect
with CVD Co optimizes EM
lifetime.
Figure 4. CVD Co liner
process demonstrates
suitable stability for high-
volume manufacturing.
Figure 5. CVD Co capping
process meets production
requirements for stability
and repeatability.
4© 2014 Applied Materials, Inc. All rights reserved. CVD Co-Based Metallization
ACKNOWLEDGEMENTSThe authors appreciate contributions from the technology
and engineering teams of the Applied Materials Metal
Deposition Products and Advanced Process Technology
Development business units.
REFERENCES [1] M. He, et al., “Mechanism of Co Liner as Enhancement
Layer for Cu Interconnect Gap-Fill,” Jour. of the
Electrochem. Soc., 160 (12), D3040-D3044, 2013.
[2] O. Aubel, et al., “Comparison of Process Options
for Improving Backend-of-Line Reliability in 28nm
Node Technologies and Beyond,” Jap. Jour. of Appl.
Phys., 50, 2011.
[3] K. Shah, et al., “Selective Metal Capping with CVD Co
for Improved Interconnect Reliability,” Nanochip Tech.
Jour., Applied Materials, Inc., Vol. 11, Issue 1, 2013.
[4] A. Simon, et al., “Electromigration Comparison of
Selective CVD Cobalt Capping with PVD Ta(N) and
CVD Cobalt Liners on 22nm-Groundrule Dual-
Damascene Cu Interconnects,” IRPS, 2013.
[5] H. Kim, et al., “Cu Wettability and Diffusion Barrier
Property of Ru Thin Film for Cu Metallization,” Jour.
of the Electrochem. Soc., 152, 8, G594-G600, 2005.
[6] H. Bhandari, et al., “Chemical Vapor Deposition of
Cobalt Nitride and its Application as an Adhesion-
Enhancing Layer for Advanced Copper Interconnects,”
ECS Jour. of Solid State Sci. and Tech., 1 (5),
N79-N84, 2012.
[7] H.K. Jung, et al., “Formation of Highly Reliable
Cu/Low-κ Interconnects by Using CVD Co Barrier
in Dual Damascene Structures," IRPS, 2011.
[8] T. Matsuda, et al., “Superior Cu Fill with Highly
Reliable Cu/ULK Integration for 10nm Node and
Beyond," IEEE Intl. Electron Devices Meeting, 2013.
[9] A. Grill, et al., “Progress in the Development and
Understanding of Advanced Low κ and Ultralow κ
Dielectrics for Very Large-Scale Integrated
Interconnects—State of the Art,” Appl. Phys.
Reviews 1, 011306, 2014.
AUTHORS Kavita Shah is a global product manager in the Metal
Deposition Products business unit of the Silicon Systems
Group at Applied Materials. She holds her M. Eng. in
chemical engineering from Cornell University.
Sree Kesapragada is a global product manager in the
Metal Deposition Products business unit of the Silicon
Systems Group at Applied Materials. He earned his Ph.D.
in materials science and engineering from Rensselaer
Polytechnic Institute.
Tae Hong Ha is a technology manager in the Metal
Deposition Products business unit of the Silicon Systems
Group at Applied Materials. He received his M.S. in
materials science and engineering from the Pohang
Institute of Science and Technology, South Korea.
Jiang Lu is a member of technical staff in the Metal
Deposition Products business unit of the Silicon Systems
Group at Applied Materials. He holds his Ph.D. in
chemical engineering from Texas A&M University.
ARTICLE [email protected]
PROCESS SYSTEM USED IN STUDYApplied Endura® Volta™ CVD Cobalt
1© 2014 Applied Materials, Inc. All rights reserved. Volume 12, Issue 2, 2014Nanochip Technology Journal
Aspect ratios of through-silicon via (TSV) structures have
increased to ≥10:1 in recent years. This development poses
challenges for back-end-of-line (BEOL) PVD processes
that suffer line-of-sight limitations in achieving robust and
void-free CuBS deposition. Refinements in PVD chamber
design and parameter control are overcoming these issues,
enabling chipmakers to extend existing infrastructure and
knowhow to create high-reliability barriers and void-free
gap fill in structures tens of microns deep.
3D integration has emerged as a viable “more than Moore"
solution for cost-effectively producing vertically stacked
modules designed for high-performance, multi-functional,
compact, heterogeneous systems featuring broad
bandwidth, high speed, and low power consumption.
TSV technology is a critical enabler in this 3D integration
technology, enabling vertical electrical connections
between different devices. TSVs today are usually
fabricated using the so-called “via middle” process.
This involves creating them through the substrate after
the active devices are fabricated.[1]
Typical TSV processes include etching a deep via hole
in a substrate by reactive ion etch, lining the via with an
insulating layer that prevents leakage between the TSV
and the substrate, and depositing a barrier layer and
seed layer, followed by electroplating Cu to fill the TSV.
Finally the excess Cu is polished away. The integration
scheme and process flow is similar to that of the cur-
rent BEOL damascene process (Figure 1).
A key challenge in current 3D TSV integration is reducing
the impact on device performance of TSV-induced
stress surrounding 3D interconnections.[2,3] This issue
can potentially be mitigated by design restrictions, such
as keep-out zones, that limit the placement of active
devices within a certain distance from a TSV. From a cost
perspective, however, unused real estate on the wafer
is not desirable. Consequently, until viable methods of
mitigating such stress[4] are production-ready and can
ease the need for further scaling, via dimensions are
inevitably shrinking and TSV aspect ratios increasing.
Most TSVs today have aspect ratios of approximately
10:1 (50x5μm) compared to 5-8:1 about 5-6 years ago.
This trend has posed a significant challenge to existing
BEOL PVD technologies as they were not designed to
deposit materials into structures tens of microns deep.
KEYWORDS
Copper
Interconnects
PVD
Reliability
Tantalum
Titanium
TSV
Extending PVD CuBS to Through-Silicon Vias
Figure 1. Typical integration
flow for TSV via creation
and fill is very similar to the
BEOL sequence.
Figure 1
IncomingWafer TSV Etch CVD Liner
PVD Barrierand Seed
TSV CuPlating
Excess CuPolishing
2© 2014 Applied Materials, Inc. All rights reserved. Extending PVD CuBS to Through-Silicon Vias
The aspect ratio of a typical damascene structure
is 4:1 (with depths typically ≤55nm), compared to a
typical 10:1 TSV (with depths of 50-100µm). Figure 2a
shows an actual dimensional comparison between
BEOL structures and TSV. As shown in Figure 2b, step
coverage in a PVD deposition chamber is a strong
function of the neutral/metal ion ratio. Neutrals have
high angular distribution and follow line-of-sight
deposition. This results in the buildup of overhang at
the via opening and poor sidewall coverage, especially
in high aspect ratio (HAR) TSV structures. Ion energy is
also important, as only high-energy ions can reach the
bottom of deep vias. Technology refinements presented
in this article have greatly improved PVD capabilities
for TSV fabrication (Figure 2c).
TECHNOLOGY IMPROVEMENTSThe key requirements for PVD deposition within TSV
structures are: (1) a higher fraction of metal ions and
(2) improved deposition directionality to address line-
of-sight limitations. Magnetron design is important in
establishing the ionization level in a PVD chamber for
sputtering metal materials. To improve directionality by
narrowing the angular distribution of the ions, a potential
difference/bias must be established at the wafer level
to impart high energy levels to the ions and “pull” them
into the deep vias.
By addressing the above requirements effectively,
BEOL PVD coverage can be much improved (Figure 2c),
although actual coverage is heavily dependent on
the via’s profile, roughness, and aspect ratio.
Figure 2. (a) SEM image
shows vast scale difference
between BEOL structures
(circled) and a single TSV.
(b) Relative scale of BEOL vs.
TSV structures makes PVD
inappropriate for today's TSVs.
(c) Improved magnetron
design and optimized
directionality results in
TSV-optimized PVD
outperforming BEOL PVD.
Figure 2
Nor
mal
ized
Cov
erag
e
5x50μm TSVs
Via BottomBottom Corner6μm Above Bottom
0.0
12.0
10.0
8.0
6.0
4.0
2.0
BEOL Ta Coverage (15Å/s)Improved Ta Coverage (21Å/s)
Source: Reference 5.
(a)
(c)
(b)
BEOL
TSV
FEOL
Bottom
Bottom Corner
6μm Above Bottom
PVD Magnetron PVD Magnetron
BEOL Via(≤55nm, 4:1 AR)
TSV(5x50μm, 10:1 AR)
3© 2014 Applied Materials, Inc. All rights reserved. Extending PVD CuBS to Through-Silicon Vias
Magnetron design is the major contributor to the
performance improvement illustrated. By optimizing
the neutral/metal ion ratio[6] and the magnet motion,
coverage—and hence gap fill—is significantly improved.
Deposition rate also increases, which helps improve
productivity of the process.
Thickness of the barrier/seed layers correlates strongly
with the quality of gap fill. The range of barrier/seed
thicknesses that results in void-free gap fill can be
defined as a gap-fill window. With the enhanced design
described above and additional parameter tuning, much
thinner barrier/seed layers are possible. These minimize
metal buildup around via openings, thereby promoting
void-free gap fill (Figure 3) in addition to improving
productivity and reducing production costs.
Using the TSV-optimized PVD for Ta/Cu barrier/seed
results in gap fill up to four times better than that
obtained with BEOL PVD. The Ti/Cu combination
improves gap fill approximately two times over typical
BEOL Ta/Cu technology. Given that the lighter mass of
Ti would be expected to result in poorer coverage than
Ta, the Ti/Cu results are exceptional.
Ti vs. Ta BARRIERSChipmakers are beginning to consider transitioning
from Ta to Ti as the barrier material of choice. This
trend is based on manufacturing considerations as well
as on Ti’s material properties.
Device Fabrication
Ta has long been used as a barrier in BEOL processes
and was, therefore, a natural choice for TSV fabrication.
However, given its cost and the fact that a thicker barrier
is needed for TSV, much effort has been applied to
developing a viable Ti alternative. Multiple studies were
conducted,[7] and Ti was shown to have advantages as
a TSV barrier, despite the necessity of a 50% thicker
layer for gap fill (Figure 3). Thicker barrier material is
acceptable in TSVs as the bulk of the via (5-10μm CD)
will be filled with Cu; resistivity is not an issue, unlike a
damascene structure in which line resistance is critical.
From the costs of ownership (CoO) and consumables (CoC)
perspectives, Ti retains a significant advantage (Figure 4).
Figure 3
(a)
(b)
Nor
mal
ized
Cu
Seed
Thi
ckne
ss
Normalized Barrier Thickness
1 2 3 4
0
2
1
3
4
5
6
7
8
Gap-Fill Window of Barrier Seed Combination
Applied Materials internal data
Ta/CuTi/CuBEOL Ta/Cu
Figure 4
Cos
t of
Ope
rati
on
BEOL 4X Ta/8X CuImproved
PVD 2X Ta/3X CuImproved
PVD 3X Ti/3X Cu
0%
20%
40%
60%
80%
100% CoCCoO
CoC BarrierCoC Seed
CoC is >60% of CoO
Ta CoC is >50% of CoO
Better Ta coveragefor gap fill lowersCoO, but remains
~30% of CoOTi with proven reliability andgap fill lowers
CoO further
Figure 4. Normalized cost
analysis based on gap-fill
window shown in Figure 3.
Figure 3. (a) TSV-optimized
Ti/Cu and Ta/Cu PVD
barrier/seed results are
significantly superior to
those of BEOL PVD.
(b) Cross-sectional SEM
shows successful gap fill
in 5x50μm TSVs.
4© 2014 Applied Materials, Inc. All rights reserved. Extending PVD CuBS to Through-Silicon Vias
Material Properties
In the TSV integration flow, CVD oxide is often the liner
of choice. However, it is porous; consequently, outgassing
may occur during barrier deposition, which leads to
barrier oxidation. Oxidized Ti remains a good Cu wetting
layer (Figure 5) and retains its barrier properties.[8]
In contrast, Ta loses its wetting property, which often
leads to void formation during gap fill. In addition, Ti
is known to form an intermetallic compound with Cu.
This intermixing is believed to strengthen the adhesion
between Ti and Cu, minimizing delamination concerns.
Recent studies have shown that the barrier directly
affects dielectric liner reliability.[9] More interestingly,
they have shown that a PVD Ti barrier is more reliable
than PVD Ta in HAR TSVs. A separate study previously
demonstrated that Ti, like manganese, exhibits a self-
forming barrier capability,[10] with outward diffusion of
Ti atoms creating a robust Cu(Ti)/Cu interface with
good barrier properties. This phenomenon suggests
that a thin Ti film has sufficient barrier characteristics
to prevent Cu diffusion into surrounding dielectrics
following gap fill.
CONCLUSIONWith TSV scaling and the industry’s desire to extend
PVD for CuBS within these HAR features, several PVD
chamber technology improvements are advancing the
reliability and cost-effectiveness of Cu metallization.
Furthermore, implementation of Ti as a low-cost
alternative barrier with superior properties sustains
PVD’s role in the TSV space. In anticipation of further
scaling, ongoing work focuses on extending PVD
technology as future TSV aspect ratios increase.
ACKNOWLEDGEMENTSThe authors extend their appreciation to the technology
and engineering teams from the Applied Materials
Metal Deposition Products business unit, Advanced
Product and Technical Development group, and Asia
Product Development Center for their contributions.
REFERENCES[1] N. Kumar, et al., “Robust TSV Via-Middle and
Via-Reveal Process Integration Accomplished Through Characterization and Management of Sources of Variation,” Proc. of the Elect. Comp. and Tech. Conf. (ECTC), 2012 IEEE 62nd, pp. 787-793, 2012.
[2] C.L. Yu, et al., “TSV Process Optimization for Reduced Device Impact on 28nm CMOS,” 2011 Symp. on VLSI Tech. (VLSI), pp. 138-139, June 14-16, 2011.
[3] W. Guo, et al., “Impact of TSV Induced Mechanical Stress on FinFET Devices,” IEEE Electron Devices Meeting (IEDM), Dec. 10-12, 2012.
[4] Y. Civale, et al., “Via-Middle Through-Silicon Via with Integrated Airgap to Zero TSV-Induced Stress Impact on Device Performance,” Elect. Comp. and Tech. Conf. (ECTC), 2013 IEEE 63rd, pp. 1420-1424, 2013.
[5] GLOBALFOUNDRIES, “GLOBALFOUNDRIES Demonstrates 3D TSV Capabilities on 20nm Technology,” http://www.globalfoundries.com/newsroom/press-releases/2013/12/28/global-foundries-demonstrates-3d-tsv-capabilities-on-20nm-technology, April 2013.
[6] P.J. Kelly, et al., “Magnetron Sputtering: A Review of Recent Developments and Applications,” Vacuum 56, pp. 159-172, 2000.
Figure 5
Applied Materials internal data
PVD Ti + PVD Cu PVD Ta + PVD Cu Figure 5. 100Å PVD Barrier
+ 20Å Cu after 175C˚ 30min
anneal shows good Cu
wetting on oxidized Ti (left)
vs. the Cu agglomeration that
occurs on oxidized Ta (right).
5© 2014 Applied Materials, Inc. All rights reserved. Extending PVD CuBS to Through-Silicon Vias
[7] Y. Civale, et al., “Thermal Stability of Copper Through-
Silicon Via Barriers during IC Processing,” Intl. Inter.
Tech. Conf. and Matls. for Adv. Metal. (IITC/MAM),
pp. 4577-0502, IEEE, 2011.
[8] M. Hamada, et al., “Highly Reliable 45-nm-Half-
Pitch Cu Interconnects Incorporating a Ti/TaN
Multilayer Barrier,” Inter. Tech. Conf. (IITC), 2010 Intl.,
pp. 1-3, 2010.
[9] Y. Li, et al., “Impact of Barrier Integrity on Liner
Reliability in 3D Through Silicon Vias,” Reliability Phys.
Symp. (IRPS), 2013 IEEE Intl., pp. 5C.5.1-5C.5.5, 2013.
[10] K. Ohmori, et al., “A Key of Self-Formed Barrier
Technique for Reliability Improvement of Cu Dual
Damascene Interconnects,” IITC, 2010.
AUTHORSIsaac Ow is a global product manager in the Metal
Deposition Products business unit of the Silicon
Systems Group at Applied Materials. He holds his Ph.D.
in physics from the National University of Singapore.
Anthony Chan is a technology manager in the Metal
Deposition Products business unit of the Silicon
Systems Group at Applied Materials. He earned his Ph.D.
in physics from the Rensselaer Polytechnic Institute.
ARTICLE [email protected]
PROCESS SYSTEM USED IN STUDYApplied Endura® Ventura™ PVD
1© 2014 Applied Materials, Inc. All rights reserved. Volume 12, Issue 2, 2014Nanochip Technology Journal
Deliberately non-uniform dose implants can improve
device performance across the wafer by compensating for
non-uniformities introduced by process steps other than
implantation. In conjunction with improved controls on dose
delivery and beam profile, new algorithms are enhancing
the ability to customize dosing in up to seven zones for
any scan line without rotating the wafer. These expanded
capabilities offer chipmakers a versatile means of improving
device performance and yield.
The continuing quest for improved semiconductor
device performance and yield translates into ongoing
optimization of the operational parameters of
semiconductor equipment to produce better performing
devices in a more repeatable and more uniform manner
across the wafer and wafer to wafer. Fabrication processes,
such as CMP, CVD, and (plasma) etching, have inherent
non-uniformities, which typically translate into variability
of device threshold voltage (Vth
) or saturation current
across the wafer. Ion implantation allows very precise
control over implanted dose and device parameters,
making it an effective means of correcting or offsetting
such variabilities.[1-4]
Ion implantation uniformity corrections can be broadly
grouped as: (1) device doping-level adjustment to
counteract the non-uniform signature of the other process
on Vth
and (2) modification of material properties, e.g.,
etch rate modulation to produce uniform process results.
The first category typically requires low-dose, ≤5E13 cm-2
implants, which are performed by medium-current
ion implanters. The second category typically involves
implants over a broader dose range up to 1E16 cm-2 with
CMP material removal rate modulation.
PRINCIPLE OF OPERATIONUniform dosing of a wafer is accomplished with a
spot beam and hybrid scanning. The wafer is scanned
mechanically in the vertical direction at a speed between
15 and 45 cm/s (fixed during the wafer pass) and
the beam is scanned electrostatically in the horizontal
direction at a nominal frequency of 1kHz. The beam
scanning rate is variable, both from one scan to the
next and during a scan. Position-specific piecewise
adjustments to the scan waveform are made to produce
uniform left-to-right dosing of the wafer by increasing
or decreasing the time the beam spends at positions
where the beam current is low or high, respectively.[5]
The horizontal scan is then repeated after the mechanical
wafer scan travels a predetermined distance, resulting
in several hundred scan lines across the wafer during a
single mechanical scan. Vertical uniformity is achieved
by making corrections to the macroscopic slope of the
scan waveform to compensate for measured variations
in spot beam current.
The same approach of modulating the scan waveform
to achieve uniform dosing on the wafer is used to
produce deliberately non-uniform dose patterns. The
beam is scanned at nominal speed across wafer zones
intended to receive the nominal recipe doses and is
sped up locally across wafer zones intended to receive
lower dosing.
Enhancing Customized Dose Patterningfor Higher Yields
KEYWORDS
Doping
Ion Implantation
Process Control
2Enhancing Customized Dose Patterning© 2014 Applied Materials, Inc. All rights reserved.
The custom wafer dosing pattern is defined using up to
1,245 individual wafer locations, located on a grid with
7.5mm spacing. Either of two methods can be used:
(1) downloading of the desired dose correction map in
electronic format or (2) a fast, user-friendly graphical
user interface (GUI) that allows the user to define the
location, shape, size, orientation, and a zone dose ratio
as high as 7:1 for up to seven stylized zones.
High-fidelity dose pattern reproduction requires
sophisticated modeling involving convolution of the
input dose pattern, and the beam shape and current
density distribution. This modeling is incorporated in
a new Solver/Predictor algorithm, which allows the user
to preview the final wafer dose pattern without needing
in-line post-implant metrology. A new multi-pixel
profiling Faraday, located in the wafer plane, enables
measurement of the complete 2D beam profile with
resolution down to 3mm.
The download mechanism in principle enables
individual wafer adjustment of the dose pattern based
on critical process parameters provided by an in-line
metrology tool. On the other hand, the GUI allows
rapid input of approximate dose patterns that may be
appropriate for large numbers of wafers or wafer lots.
Information about the GUI-defined dose patterns is
stored in the implant recipe and is available for use
in subsequent jobs.
Zone shapes can be edited graphically by simply grabbing
and dragging shape “handles” with the mouse or by
modifying their numerical attributes in an on-screen
table. Zone shapes can be centered on the wafer or
offset from center; they may be circular or elliptical
with the axes of the ellipse rotated at any angle. Zone
information is transformed into a high-resolution map,
which is in turn translated into as many different scan
lines and unique scan waveforms as needed to correctly
reproduce the pattern on wafer.
The Predictor algorithm convolutes the calculated
waveforms with the actual 2D multi-pixel beam profile,
presenting the user with a predictive map showing
the expected dosing on the wafer. Figure 1 shows the
excellent agreement between the predicted pattern
produced by the Solver/Predictor and a Therma-Probe
(TW) contour map of the actual wafer.
Figure 1
Applied Materials internal data
RESULTSCustomizable dosing is illustrated here using two
examples that have real relevance to the types of non-
uniformities typically requiring correction: a “top hat”
pattern and a “ring” pattern. In these examples, both
patterns were implanted with a nominal BF2+ 25keV
5E13 cm-2 recipe; the first pattern is a two-zone top hat
with a central zone diameter of 80mm and a 2.5:1 dose
ratio. The second pattern is a 30mm-wide ring centered
at a radius of 105mm and dosed 30% lower than the
nominal dose in the central and outer zones.
The resulting wafer dose patterns were evaluated in
TW units using 225-point Therma-Probe contour maps,
and 225-point vertical and horizontal Therma-Probe
diameter scans. The contour maps (Figure 2) show that
the patterns are uniform, well-centered, with a sharp
transition region.
Figure 2
Applied Materials internal data
Figures 3 and 4 depict the accuracy and uniformity of
the delivered dose patterns for the top hat and ring
pattern, respectively. To allow calibration of the TW
response to dose for this specific beam setup, a number
of additional uniform wafers were also implanted with
the same beam setup to doses from 2.5E13 to 5.5E13 cm-2.
The figures also show these reference implants for
Figure 1. Pattern predicted
by new Predictor algorithm
corresponds closely with the
TW wafer map.
Figure 2. “Top hat” pattern
and a “ring” pattern
implanted with a nominal
BF2+ 25keV 5E13 cm-2 recipe
show excellent uniformity
and centering with sharp
transition regions.
3Enhancing Customized Dose Patterning© 2014 Applied Materials, Inc. All rights reserved.
comparison. The customized results demonstrate excellent dose accuracy in the nominally dosed zones, precise targeting of the dose in the secondary zones, and outstanding dose uniformity within each zone.
Demonstrating the direct relationship between the abruptness of the transition region and beam size, Figure 4a shows that the transition region broadens as the beam size increases. This behavior offers an additional degree of freedom in controlling the desired
dose pattern. As most non-uniform processes suitable for
correction (e.g., gate or spacer CD or film thicknesses)
exhibit gradual spatial dependence, they could be
corrected equally well using a “silk hat” pattern for a
smaller beam or a top hat pattern for a larger beam.
Figure 4b shows the insensitivity of transition width to
wafer position, comparing the diameter scans for top
hat patterns with different central zone radii implanted
with the same-size beam.
Figure 4. (a) Therma-Probe
wafer diameter scans for
the same top hat pattern
implanted with the same
nominal recipe using beams
of different sizes.
(b) Therma-Probe wafer
diameter scans for top
hat patterns with different
central zone radius implanted
with the same beam setup.
Figure 3
(a)
TW
Uni
ts
Wafer Position (mm)
-150 -100 -50 0 50 150100
5.5E13
4.5E13
3.5E13
2.5E13
750
950
900
850
800
(c)
TW
Uni
ts
Wafer Position (mm)
-150 -100 -50 0 50 150100
5.5E13
4.5E13
3.5E13
800
950
900
850
(b)T
W U
nits
Dose (E13/cm2)
1 3 5 7
780
830
880
930
980
Uniform Reference WafersCentral ZoneOuter Zone
(d)
TW
Uni
ts
Dose (E13/cm2)
1 3 5 7
800
850
900
950
Uniform Reference WafersCentral ZoneOuter ZoneRing Zone Min
Figure 4
(a)
TW
Uni
ts
Wafer Position (mm)
-150 -100 -50 0 50 150100
775
975
925
875
825
Beam Size 90mm 75mm 50mm 30mm
(b)
TW
Uni
ts
Wafer Position (mm)
-150 -100 -50 0 50 150100
750
950
900
850
800
Center Zone Radius 80mm 100mm 120mm
Figure 3. (a) Therma-Probe
horizontal and vertical wafer
diameter scans of top hat
pattern with 2.5:1 dose ratio.
Grey lines are dose-calibration
diameter scans of uniformly
implanted wafers.
(b) Dosing analysis for top
hat pattern.
(c) Therma-Probe scans of
ring pattern with 30% dose
difference.
(d) Dosing analysis for ring
pattern.
4Enhancing Customized Dose Patterning© 2014 Applied Materials, Inc. All rights reserved.
Figure 5
Applied Materials internal data
(b)
(a)
33 x 28mm 42 x 56mm 72 x 90mm
Figure 5. (a) Therma-Probe
contour wafer maps for
patterns with the same central
zone radius implanted with
beams of different sizes.
(b) Associated two-dimensional
multi-pixel beam profiles.
Figure 6. Therma-Probe
contour maps:
(a) previous technology
required wafer rotation;
(b) no rotation necessary
for single-step implant using
new algorithm and beam
control; and
(c) four-step implant using
new algorithm and beam
control with no rotation.
Figure 6
Applied Materials internal data
(a) (b) (c)
Figure 5 presents the TW contour maps corresponding
to the wafer diameter scans shown in Figure 4a as well
as the sizes of the beams used to generate them. Beam
size plays an important role in the fidelity of the final
dose pattern and was a key factor in developing the
Predictor algorithm.
Figure 6 shows a contour map of a wafer implanted
using previous technology compared with two implanted
using the new algorithm in conjunction with beam size
control. The wafers were implanted with the same
beam setup and the same target pattern. Previous
generations of custom implant technology required
rotation of the wafer, which is no longer necessary with
the improvements highlighted in this article. Figure 6b
also shows the sharper transition region and excellent
uniformity obtained with the new technology. Figure 6c
demonstrates the capability of the algorithm to deliver
off-center dose in the same location for different wafer
orientations, thus enabling high-tilt off-center implants.
CONCLUSIONNew capabilities in customizing ion implantation
patterns are improving device performance and yield by
correcting non-uniformities introduced by process steps
other than ion implantation. A two-dimensional beam
profiler and enhanced dose controller make possible
custom dose delivery delivered through enhanced
predictive algorithms for virtually any desired pattern
without rotating the wafer. The system accommodates
up to seven different zones with a zone dose ratio as
high as 7:1 while maintaining excellent dose accuracy
and uniformity within each zone.
ACKNOWLEDGEMENTSG. Gammel, D. Olden, M. Welsch, and N. Parisi of
Applied Materials’ Varian Semiconductor Equipment
business unit made significant contributions to this
work. The authors also extend their appreciation to
S. Falk, Y-K Kim, and D. Rodier for many productive
discussions.
5Enhancing Customized Dose Patterning© 2014 Applied Materials, Inc. All rights reserved.
REFERENCES [1] A. Renau, “Method and System for Compensating for
Anneal Non-Uniformities,” U.S. Patent 6,828,204 B2,
2004.
[2] M-Y Lee, et al., “The Concept of LDSI (Locally-
Differentiated-Scanning Ion Implantation) for the
Fine Threshold Voltage Control in Nano-Scale FETs,”
16th Intl. Conf. on Ion Implant. Tech., IIT 2006,
K.J. Kirkby, R. Gwilliam, A. Smith, and D. Chivers,
Eds. Melville, NY, AIP Conf. Proc., pp. 62-64, 2006.
[3] C. Krueger, et al., “Achieving Uniform Device
Performance by Using Advanced Process Control
and SuperScan,” 18th Intl. Conf. on Ion Implant. Tech.,
IIT 2010, J. Matsuo, M. Kase, T. Aoki, and T. Seki,
Eds. Melville, NY, AIP Conf. Proc., pp. 123-126, 2011.
[4] F. Sinclair, et al., “V900 3D: Advanced Medium
Current Implanter,” 22nd Intl. Conf. on Ion Implant.
Tech., IIT 2014.
[5] J.C. Olson, et al., “Scanned Beam Uniformity Control
in the VIISta 810 Ion Implanter,” 1998 Intl. Conf.
on Ion Implant. Tech. Proceedings, J. Matsuo,
G. Takaoka, and I. Yamada, Eds. Piscataway, NJ: IEEE,
pp. 169-172, 1999.
AUTHORSStan Todorov is a staff scientist in the Varian
Semiconductor Equipment business unit of the Silicon
Systems Group at Applied Materials. He holds his Ph.D.
in physics from Columbia University.
Greg Gibilaro is a senior software engineer in the Varian
Semiconductor Equipment business unit of the Silicon
Systems Group at Applied Materials. He earned his
B.S. in engineering and computer science from the
University of Connecticut.
Norm Hussey is a principal software engineer in
the Varian Semiconductor Equipment business unit
of the Silicon Systems Group at Applied Materials.
He received his B.S. in electrical engineering from
Northeastern University.
John Sawyer is a principal software engineer in the
Varian Semiconductor Equipment business unit of the
Silicon Systems Group at Applied Materials. He holds
his B.S. in computer science from Merrimack College.
ARTICLE [email protected]
PROCESS SYSTEM USED IN STUDYVarian VIISta® 900 3D Medium Current Ion Implant
1© 2014 Applied Materials, Inc. All rights reserved. Volume 12, Issue 2, 2014Nanochip Technology Journal
At the 1xnm node, 3D FinFETS pose a number of new
metrology challenges. Gate and fin height are two of the most
important process control parameters for which no inline
in-die measurement has yet been implemented. In-column
beam tilt CD-SEM for height measurement has been
developed in response and is showing good results in the gate
height application. Fin height measurement needs further
refinement, yet initial results show promise that this method
may become a viable metrology method for 3D devices.
As demand for high-performance ICs proliferates, key
fabrication challenges are the shrinking device dimensions
and growing complexity of device geometry in all three
dimensions. At the 1xnm node, 3D FinFET structures
are posing process control challenges for traditional
metrology with respect to such measurements as gate
height, fin height, sidewall angle, profile, spacer widths,
spacer pull-down, and footing/undercut.
At present, inline process control of 3D structures has been
achieved mainly through scatterometry/optical critical
dimension (OCD) and the atomic force microscope (AFM).
OCD is labor-intensive to implement and cannot monitor
in-die process variation. AFM is also time consuming
and cannot readily measure key processes in FinFET
fabrication due to the relatively large dimension of the
scanning tip.
To remedy this gap in metrology capabilities, in-column
beam tilt on a top-down CD-SEM has been implemented
to enable measurement of gate and fin heights. Tilt-beam
CD-SEM was first introduced by Su, et al.,[1] in 2000, who
demonstrated sidewall imaging capability by bending
the electron beam in the column on an Applied Materials
VeraSEM-3D CD-SEM. The tilted perspectives at two
angles (2˚ and 5˚) provided accurate sidewall angle
information (including re-entrant profile) in addition
to CD for monitoring a photolithography process.
Marschner, et al., applied the tilt-beam technique to
gain sidewall angle and resist height information that
complemented bottom CD to determine the best
process window in a focus exposure matrix.[2]
Bunday, et al., in 2002 further qualified the precision
and accuracy of this method, and explored its application
to etch bias control.[3] A year later, Bunday reported
further improvement in tilt-beam measurement on a
NanoSEM-3D (upgraded from VeraSEM-3D) with a
systematic study of measurement capability on various
front- and back-end-of-line structures in the CMOS
process.[4] He also reported measuring capability
involving one tilt on sidewall angle with a known feature
height and explored its application to FinFET fins in 2007.[5]
To date, studies on tilt beam have focused on sidewall
metrology and less on height measurement. Now,
with FinFET designs ramping up for production, an
immediate metrology solution is needed specifically for
in-die gate and fin height control. This work evaluated
the tilt-beam technique for gate and fin height metrology,
assessing its accuracy, sensitivity, and precision. To our
knowledge, it is the first time that sub-nm precision has
been demonstrated in tilt-beam metrology.
MECHANISM OF TILT-BEAM METROLOGY The mechanism of tilt-beam CD-SEM has been discussed
in detail in earlier publications.[1,3,4] It is similar to
binocular vision, in which both eyes must be used to
receive images from two different angles to attain depth
perception. To measure the height of a sidewall using
tilt-beam CD-SEM, the feature of interest is scanned
twice by the electron beam tilted at two different angles
KEYWORDS
1xnm Node
3D Metrology
CD-SEM
FinFET
Fin Height
Gate Height
Tilt-Beam
Tilt-Beam CD-SEM for FinFET Metrology at the 1xnm Node
2© 2014 Applied Materials, Inc. All rights reserved. Tilt-Beam CD-SEM for FinFET Metrology
from the column, thus creating two images with different
edge widths (E1 and E2) as shown in Figure 1.
In the two images, the sidewall will appear to have
different edge widths. The height (h), sidewall angle (θ),
and two edge widths (E1 and E2) measured at two
different tilt angles (α1 and α2) have the geometrical
relationships illustrated in Figure 1. Height and sidewall
angle can be calculated based on the mathematical
relation of α1, α2, E1, and E2 shown in the figure.
The accuracy of the calculated height is inversely
proportional to the angle difference of the two tilt-beams.
The larger the angle difference, the more accurate the
height calculation.
While a larger tilt angle difference reduces measurement
uncertainty and error, the maximum applicable tilt
angle is determined by the aspect ratio and density of
the structures to be measured. The more the incident
beam is tilted, the larger its beam size and the poorer
the resolution of the image. Poorer resolution means less
sensitivity to CD change; however the greater apparent
edge width when imaged in tilt compensates for the
loss of sensitivity caused by the larger beam size.
In these studies, two working points were calibrated
corresponding to beam tilt angles of 5˚ and 14˚. The
azimuths of both tilted beams were 180˚, illuminating
the sample from the left. The tilt angles were calibrated
to within 0.05˚ of the nominal tilt and azimuth value.
APPLICATIONS ON FINFET DEVICES Bunday, et al.,[7] listed 13 parameters of the FinFET structure critical to process control, among which gate height over the fin (overburden) and fin height require immediate attention. Loading effects can produce substantial variation in gate height within die and from die to die. In the development stage, variation can be large enough to cause gate open and fin exposure, resulting in defective devices.
Fin height control is even more critical as the slightest variation directly affects the effective gate width and, thus, the drive current and threshold voltage of the device. Accurate measurements of these parameters in different in-die locations will be essential for implementing high-volume manufacturing of FinFET devices.
Gate Height Control The tilt-beam measurement was performed at the step in a gate-last process at which the dummy gate had been removed and the high-κ/work function material deposited. In the structure, lines of SiGe/oxide/nitride spacer were covered by high-κ/work function material lying perpendicular to and over the fins that were also covered by high-κ/work function material (Figure 2). Trenches between the lines were to be filled with gate metal, the height of which would be defined by the spacer height in the CMP step after metal gate filling. Therefore, minimizing the variation in spacer height at this step was vital for controlling the final gate height.
Figure 1. Tilt-beam CD-SEM
involves imaging a feature
twice with an electron beam
at two different incident
angles (α1 and α2) from
which its height can be
calculated.
Figure 2. FinFET structure on
which tilt-beam measurements
were taken for gate height
measurement.
Figure 1
Source: Reference 6.
Top View
Low Tilt
High Tilt
hEE 12
12 tantan −=− αα
11 tantan
αθ
⋅−=
hEh
θ
θ
E2E1
h
2α1α
Figure 2
Oxide
Fin
SiGe
Spacer
HK/WF
Source: Reference 6.
3© 2014 Applied Materials, Inc. All rights reserved. Tilt-Beam CD-SEM for FinFET Metrology
The nitride spacer on the left side of the oxide was
measured on semi-dense (250nm pitch) and isolated
(640nm pitch) features on three wafers with built-in
spacer height variation. One center die and one edge
die from these wafers were selected for transmission
electron microscope (TEM) reference measurement on
different in-die features. Figures 3a-c show tilt-beam
measurement correlation to TEM on these features.
For both semi-dense features, the R2 (coefficient of
determination of how well a set of values would predict
another) was more than 0.99; it was 1 for the isolated
feature owing to limited TEM data points, but still
showed good sensitivity to the process split. The overall
R2 showed good correlation at 0.8941.
Precision was evaluated by measuring the P-type
semi-dense structure on 10 dies across the wafer on 10
consecutive runs. A linear trend correction was applied
to the results to remove the anticipated CD growth
from SEM carbonization caused by repeated bursts
at the same location. Overall precision of 0.81nm was
calculated by averaging the 3σ from all 10 sites.
The gate height tilt-beam measurement is being
implemented for production process control. Figure 4
is a run chart of the inline raw data of the N-type
semi-dense feature, N-type isolated feature, and P-type
semi-dense feature. The data show different process
capabilities on each type of feature. Since inline tilt-beam
measurement has been implemented, such process
defects as missing pull-down have been detected at this
measurement step, as shown by the excursions in the
statistical process control charts (circled in the figure).
Daily monitoring is now being implemented in line. Pitch
and edge are monitored for both tilt angles in the X and Y
directions to control beam stability, tilt angle, and azimuth.
Figure 3
(a)
TEM
Ref
eren
ce
Tilt-Beam Measurement
P-Type Semi-Dense
TEM
Ref
eren
ce
Tilt-Beam Measurement
N-Type Semi-Dense
TEM
Ref
eren
ce
Tilt-Beam Measurement
N-Type Iso
R2 = 0.9981 R2 = 0.9989 R2 = 1
(b) (c)Source: Reference 6.
High Tilt
Low Tilt
High Tilt
Low Tilt
High Tilt
Low Tilt
Figure 3. Correlation of
tilt-beam measurement
with TEM on (a) and
(b) semi-dense features,
and on (c) isolated features.
(d) Overall correlation of all
features measured 0.8941.
(d)
TEM
Tilt-Beam Measurement
Overall TEM Correlation
R2 = 0.8941
4© 2014 Applied Materials, Inc. All rights reserved. Tilt-Beam CD-SEM for FinFET Metrology
Fin Height Control Tilt-beam measurement was evaluated on wafers after the fin-reveal step at which the oxide between the fins has been etched back to expose the top of the fins (Figure 5a). Three wafers underwent a process split at the oxide etch step with ±5nm built-in variation in the revealed fin height from the process of record.
The fin structure is more challenging to measure compared to the gate structure as both height and width are much smaller; the pitch is also much smaller, which results in
more secondary electron signals being reabsorbed on
the sidewall. In addition, the rounded profile makes edge
detection difficult (Figure 5b). E-beam tilt angles of 5˚ and
14˚ were also used for fin height measurement, but to
achieve reasonable collection efficiency the fin on the edge
of an array was measured for every feature of interest.
To reduce measurement uncertainty caused by the finite
edge width, the whole line (edge width of one sidewall
plus the top CD) was measured instead of the edge
width of one sidewall (Figure 5c).
Figure 5
Source: Reference 6.
θ
θ
E2E1
h
2α
1α
θ
θ
E2E1
h
2α
1α
Line MethodEdge Width Method
(b) (c)(a)
FinHeight OxideSi Fins
FinHeight
Figure 4
Nit
ride
Hei
ght
P-Type Semi-Dense Captured Inline Defect: Missing Pull-Down
PIEF
Q07
8MXF
3
PIEF
Q04
4MXE
3
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7
PIEF
Q09
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6
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7MXB
1
PIEE
R050
MXE
0
PIEE
R042
MXA
5
PIQ
YF20
41M
XG4
K6Q
YA13
8WFG
4
K6Q
YA13
3WFA
0
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4
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Q04
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2
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R049
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7
PID
QW
097M
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PID
QW
096M
XC3
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0
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4
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3
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3
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ride
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ght
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PIEF
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R049
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7
PID
QW
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XG5
PID
QW
096M
XC3
PIQ
YF02
61M
XD5
K6Q
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3WFE
7
K6Q
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5
K6Q
YA07
3WFE
1
K6Q
YA06
9WFD
0
K6Q
YA06
0WFB
5
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4
K6Q
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4
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2
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3
K6PY
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0WFG
3
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5
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3
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3
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3
Nit
ride
Hei
ght
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PIEF
Q07
8MXF
3
PIEF
Q04
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3
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MXE
7
PIEF
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6
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1
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0
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MXA
5
PIQ
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41M
XG4
K6Q
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8WFG
4
K6Q
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3WFA
0
PIEF
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4
PIEF
Q04
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2
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R049
MXA
7
PID
QW
097M
XG5
PID
QW
096M
XC3
PIQ
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61M
XD5
K6Q
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3WFE
7
K6Q
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5
K6Q
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3WFE
1
K6Q
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9WFD
0
K6Q
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0WFB
5
K6Q
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4
K6Q
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4
K6Q
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2
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3
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3
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5
K6N
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3
K6N
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4WFA
3
K6N
ZE08
4WFE
3
Source: Reference 6.
Figure 4. Run chart of one
month’s inline raw data of the
N-type semi-dense feature,
N-type isolated feature, and
P-type semi-dense feature,
highlighting process excursions
caused by missing pull-down.
Figure 5. (a) TEM image
and 3D illustration of fin
height measurement.
(b) TEM image of a typical in-
die fin structure with rounded
profile highlighted in red.
(c) Measurement scheme
for edge width method vs.
line method.
5© 2014 Applied Materials, Inc. All rights reserved. Tilt-Beam CD-SEM for FinFET Metrology
A center die and edge die of each wafer were measured with TEM as the reference. Figure 6 shows correlations
of tilt-beam CD-SEM and TEM for each feature of interest.
The overall R2 with all features included is 0.77—as
expected, less than that for the gate height. The OCD
target shows the strongest correlation (R2 0.95). This
is attributable to the stronger signal from the sidewall
of the fin with the slightly wider edge and a sharper
top edge that enhanced the accuracy of edge detection.
The in-die electrical 2 feature correlates the least due to
less clearly defined edges of the fin profile (Figure 5b).
Precision was evaluated by measuring the in-die
electrical 1 feature on 12 dies across the wafer on 12
consecutive runs. The 3σ of the height measurement
was calculated based on the results of these runs. A
linear trend correction was applied to the results to
remove the SEM carbonization caused by repeated
bursts at the same location. Overall precision of 1.47nm
was calculated by averaging the 3σ from all 12 sites.
Not surprisingly, differences in geometry reduced the
precision of the fin height measurement compared to that
of the gate height measurement. Although acceptable
as the first attempt, the precision needs further
improvement before being implemented in production.
CONCLUSIONTilt-beam CD-SEM was used for gate and fin height
metrology on FinFET devices. Feasibility was demonstrated
for gate height measurement, with excellent correlation to
TEM and 0.8nm 3σ precision. This is the first successful
demonstration of inline in-die gate height measurement
for 1xnm node FinFET process control. The tilt-beam
technique is being implemented in production with daily
beam monitoring that is successfully identifying process
excursions. Work on improving fin height measurement is
continuing. Future studies will investigate using the tilt-
beam approach in conjunction with OCD for measuring
trench and via depths to develop more comprehensive
measurements for 3D fabrication.
Figure 6
Tilt
-Bea
m C
D-S
EM
TEM
OCD Target
Tilt
-Bea
m C
D-S
EM
TEM
In-Die Electrical 1
Tilt
-Bea
m C
D-S
EM
TEM
In-Die Electrical 2
Source: Reference 6.
y = 1.0345x + 1.9818
R2 = 0.9563
y = 1.0563x + 0.3543
R2 = 0.8428
y = 0.8504x + 11.5
R2 = 0.7116
Tilt
-Bea
m C
D-S
EM
TEM
All Features
y = 0.9565x + 5.4909
R2 = 0.7721
Figure 6. Tilt-beam
measurement correlations
to TEM for fin height
measurement. Fin profile
differences account for the
variation in correlation factor.
6© 2014 Applied Materials, Inc. All rights reserved. Tilt-Beam CD-SEM for FinFET Metrology
ACKNOWLEDGEMENTSThe authors extend their appreciation to D. Konduparthi
and C. Osorio of GLOBALFOUNDRIES, Malta, New York,
and R. Naftali, O. Shoval, M. Bar Zvi, and S. Levi in the
Process Diagnostics and Control business unit of the
Silicon Systems Group at Applied Materials, whose
collaboration made this work possible.
REFERENCES [1] B. Su, et al., “Shape Control Using Sidewall Imaging,"
Proc. SPIE, Metr., Insp., and Process Cont. for
Microlithogr., pp. 232-238, 2000.
[2] T. Marschner, et al., “Determination of Best Focus and
Exposure Dose Using CD-SEM Sidewall Imaging,” SPIE
26th Annu. Int. Symp. Microlithogr., pp. 355-365, 2001.
[3] B.D. Bunday, et al., “Quantitative Profile-Shape
Measurement Study on a CD-SEM With Application
to Etch-Bias Control," SPIE 27th Annu. Int. Symp.
Microlithogr., pp. 138-150, 2002.
[4] B.D. Bunday, et al., “Quantitative Profile-Shape
Measurement Study on a CD-SEM With Application
to Etch-Bias Control and Several Different CMOS
Features," Proc. SPIE, Metr., Insp., and Process Cont.
for Microlithogr., pp. 383-395, 2003.
[5] B. Bunday, et al., “The Coming of Age of Tilt CD-SEM,”
SPIE Adv. Lithogr., pp. 65181S-65181S, 2007.
[6] X. Zhang, et al., “Addressing FinFET Metrology
Challenges in 1X Node Using Tilt-Beam CD-SEM,”
Proceedings of SPIE Vol. 9050, 90500C, SPIE Digital
Library, 2014.
[7] B. Bunday, et al., “Gaps Analysis for CD Metrology
Beyond the 22nm Node,” SPIE Adv. Lithogr.,
pp. 86813B-86813B, 2013.
AUTHORSXiaoxiao Zhang is a senior engineer in the Fab 8 Metrology
team of the Advanced Module Engineering group at
GLOBALFOUNDRIES. She holds her Ph.D. in electrical
engineering from the University of Hawaii at Manoa.
Alok Vaid is a senior member of technical staff in
the Fab 8 Metrology team of the Advanced Module
Engineering group at GLOBALFOUNDRIES. He earned
his M.S. in mechanical engineering from the University
of Texas at Austin.
Jessica Hua Zhou is an application engineer in the
Process Diagnostics and Control business unit of
the Silicon Systems Group at Applied Materials. She
received her M.S. in electronic engineering from
Northwest University.
Adam Zhenhua Ge is an application engineer in the
Process Diagnostics and Control business unit of the
Silicon Systems Group at Applied Materials. He holds
his M.S. in materials engineering from the Harbin
Institute of Technology, China.
Ofer Adan is a CD-SEM global product and technology
manager in the Process Diagnostics and Control business
unit of the Silicon Systems Group at Applied Materials.
He earned his M.S. in electronic materials engineering
from the Ben Gurion University, Israel.
ARTICLE [email protected]
PROCESS SYSTEM USED IN STUDYApplied VeritySEM®4i+ Metrology