csp315 virtual fpga - indian institute of …varma/csp315/virtual_fpga_ppt1.pdfmotivation iit-delhi...
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LOGO
“ Add your company slogan ”
Virtual FPGACSP315
Sandeep Kr Bindal
Yogesh Kumar
Ankit Kr Jain
Tarundeep Singh
Anuj Chauhan
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Motivation
IIT-Delhi is planning a virtual lab that can benefit thousands of students across India learn experiments in engineering and technology.
“The virtual laboratory will bridge physical distanceand availability of resources in far off places.Today it is possible to design good experimentsamong students for better learning”
- Surendra Prasad
Director, IIT Delhi
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Motivation
As part of the FPGA and Digital Design
Lab we aim to build :
experiments that will help students
understand computer architecture related
concepts such as caching, pipelining etc.
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MAJOR COMPONENTS / BLOCKS/
KITS ETC.
• FPGA Board
• Software
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Board – Alpha Data ADM-XRC-II
Based on the Xilinx® Virtex-2 FPGAs
Up to 24MBytes of SSRAM
Has interface to allow specialised IO modules
Complete processing system, memory, I/O and Host interface resources.
Contains a PCI to local bus bridge
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Status
Already installed on two machines in the
FPGA Lab.
Machines can be accessed using SSH
from our laptops too.
User accounts on the above machines
have already been created for our use.
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Software
Xilinx EDK 9.1
Xilinx ISE 9.1
Status – Licensed copies of these
softwares are available from the DHD Lab
and have already been procured by us.
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Work Done Previously
We were able to access various memory
modules like BRAM(on chip),ZBT-RAM(off chip)
Ran Microblaze using BRAM as memory(dual
ported) and tested it (executed instructions in
machine code)
Used 2 separate BRAMs for Instruction and
Data memory.
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Work Done Previously
Tested Interrupt (microblaze to PC) and
polling.
Automated execution of simple C
programs with help of mb-gcc (cross
compiler for Microblaze).
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Block
DiagramBlock Diagram
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MAJOR TASKS AND
ASSIGNMENTS
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Running Cache (Sandeep, Yogesh)
Read cache implementation policies (write
back/through)
Adding cache to Microblaze and testing
Adding functionalities such as set
associativity, block size
Tracing the hit/miss data for the cache
Study the impact of varying cache
parameters on performance
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Running UART (Yogesh , Sandeep)
Mapping UART pins to GPIO using level
shifter to connect it to the CPU
Testing UART for simple printf statements
Integrating the UART with the OS
(uCLinux)
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Monitor/OS (Ankit , Tarundeep)
Finding the code for uCLinux (linux without MMU)
Studying kernel dependencies and the code
Compiling and running uCLinux code for microblaze
Combining it with UART to create a terminal like interface for remote viewing
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Pipelining (Anuj , Ankit)
Study Microblaze’s pipeline implementation
Tracing the stall cycles for pipelined Microblaze
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Virtualization (Anuj , Tarundeep)
Consolidating all the status signals from
cache, pipelining etc.
Creating an interface for the end user
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PERT CHART
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GANTT CHART
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POSSSIBLE EXTENSIONS
Multiple Microblazes
FPGA Scheduling so that multiple users
can access the FPGA chip at once.
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Project Weblink
http://sites.google.com/site/iitdvirtualfpga/
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