csit 301 (blum)1 memory. csit 301 (blum)2 types of dram asynchronous –the processor timing and the...

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CSIT 301 (Blum) 1 Memory

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Page 1: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

CSIT 301 (Blum) 1

Memory

Page 2: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

CSIT 301 (Blum) 2

Types of DRAM

• Asynchronous– The processor timing and the memory timing

(refreshing schedule) were independent. Thus the processor might have to wait until the memory “window” was open for access.

• Synchronous (SDRAM) – The processor and memory timing are linked. This

allows for more efficient processor-memory interaction.

– Note SDRAM is NOT static dynamic RAM – that doesn’t make sense

Page 3: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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The Role of Cache• It’s important to remember the role of cache (SRAM) when

trying to understand the distinction between various types of DRAM.

• Over 90% of the time the processor finds what it needs in cache.

• But when one needs to access memory, one caches not only that particular value held in that particular location but also many of the values in the nearby locations (because they are likely to be needed as well – locality of reference).

• So the differences in memory types are often not in an individual access but in the accessing of a larger amount of data for the purposes of caching it.

Page 4: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Asynchronous DRAM

• Asynchronous DRAM was common until the mid to late 1990’s but now is out-dated. – Fast Page Mode

• What made FPM fast was that the same row but different columns of data could be accessed without forcing one to reselect the row strobe.

– Extended Data Out (EDO)• What was “extended” about EDO was that it could go longer

between refreshes.

– Burst Extended Data Out (BEDO) • Consecutive data was fetched in “bursts” saving on the

addressing part of access time.

Page 5: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Synchronous DRAM

• Since the mid to late 1990’s SDRAM has taken over as the standard for use in main memory. – JEDEC (Joint Electron Device Engineering

Council) or PC66 or Ordinary SDRAM operates with bus speeds up to 66MHz, now is outdated.

– PC100 SDRAM that works at higher bus speed of 100 MHz

Page 6: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Synchronous DRAM (Cont.)

– PC133 SDRAM operates at bus speed of 133 MHz and slower. This is a standard memory these days.

– There are versions of PC133 SDRAM that differ in “latency.”

– Latency is the time you spend waiting until conditions are right to proceed with some action.

– This is the CAS Latency mentioned previously.

Page 7: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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DDR-SDRAM• Double Data Rate Synchronous DRAM• One allows data to be accessed on both the

positive and negative edge of the clock (double pumping). This effectively doubles the throughput. – The associated chips go by PC200 (double PC100) or

PC266 (double PC 133)– But the memory modules are designated by

throughput. With a 64-bit bus (8 bytes) operating at PC200 (double pumped 100MHz bus), the DDR module goes by PC1600

• 1600 = 200 8

Page 8: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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DDR2 from Wikipediahttp://en.wikipedia.org/wiki/DDR2_SDRAM

• “The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, allowing transfers from two different cells to occur in the same memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.”

Page 9: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Rambus DRAM

• Rambus DRAM or RDRAM • A proprietary memory technology produced

by Rambus. • It is a competitor of the DDR-SDRAM but

it seems to be losing out. – Which is better depends to the situation. – For very high memory usage in P4 systems,

RDRAM might be better.

Page 10: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Serial Presence Detect• With all of the different types of memory, the

computer needed a way to determine the specs of the memory installed so that it could be used efficiently.

• This is the job of the Serial Presence Detect (SPD).

• A set of data usually stored on the memory stick itself that informs the BIOS of the module's size, data width, speed, and voltage.

• Previously done by the parallel presence detect (PPD).

Page 11: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Memory Packaging

• How memory is packaged– DIP: Dual inline pin Package (OLD)

• Rectangular, has pins on both sides

• 386

– SIPP: single inline chip packages (OLD)• Little circuit board with memory chip

• Has pins, hard to install

Page 12: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Memory modules (Cont.)

• SIMM single inline memory module – Like SIPP but no pins, easier to install– a 32-bit path to the memory

72-pin SIMM

30-pin SIMM

Page 13: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Memory modules (Cont.)

• DIMM dual in-line memory module, – a 64-bit path

• RIMM the Rambus version of DIMM (is not really an acronym)

• SO-DIMMs (small outline) are memory modules for laptops– Initially laptop memory was proprietary and not easily

changed or updated. Furthermore there was no easy access to its location.

Page 14: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Row versus Bank

• Row: Physical unit of memory

• Bank: logical unit

• The bank is based on bus width. Pentiums use a 64-bit width. – Two SIMMs to make a bank– One DIMM to make a bank– One RIMM to make a bank

Page 15: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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Installing Memory

Page 16: CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent

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References

• http://www.pcguide.com/ref/ram/types.htm

• http://www.webopedia.com

• http://www.whatis.com

• PC Hardware in a Nutshell, Thompson and Thompson

• All-in-One A+ Certification, Meyers and Jernigan