cset 4650 field programmable logic devices dan solarek introduction to fpgas field programmable gate...

CSET 4650 CSET 4650 Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan SolarekDan SolarekDan Solarek

Introduction to FPGAsIntroduction to FPGAsField Programmable Gate ArraysField Programmable Gate Arrays

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Hierarchy of Logic ImplementationsHierarchy of Logic ImplementationsThe diagram below is a modified version of the one we first The diagram below is a modified version of the one we first used to discuss the role of FPLDs in logic implementationused to discuss the role of FPLDs in logic implementationThis version more closely reflects the details as we have This version more closely reflects the details as we have come to know themcome to know them

Logic

StandardLogic

ASIC

ProgrammableLogic Devices

(FPLDs)

GateArrays

Cell-BasedICs

Full CustomICs

CPLDsSPLDs(e.g., PALs) FPGAs

TTL CMOS SemiCustomICs

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FPGA DevelopmentFPGA Development

FPGAs evolved from Gate ArraysFPGAs evolved from Gate Arrays

Parallel with development of CPLDsParallel with development of CPLDs

ASIC

ProgrammableLogic Devices

(FPLDs)

GateArrays

Cell-BasedICs

Full CustomICs

CPLDsSPLDs(e.g., PALs) FPGAs

SemiCustomICs

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Gate Array Technology (1970s)Gate Array Technology (1970s)

Mask-Programmable Logic DevicesMask-Programmable Logic DevicesMPLDs as compared to FPLDsMPLDs as compared to FPLDsProgrammed as part of fabrication processProgrammed as part of fabrication process

Mask-Programmable Gate ArraysMask-Programmable Gate ArraysA specific type of MPLDA specific type of MPLDBuild standard layout of transistors on chipBuild standard layout of transistors on chipCustomer specifies wiring to connect transistors into gates Customer specifies wiring to connect transistors into gates and gates into systemsand gates into systemsOnly has to go through last few mask steps of fabrication Only has to go through last few mask steps of fabrication processprocessFaster than full-custom chip fabricationFaster than full-custom chip fabrication

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Gate Array Technology (1970s)Gate Array Technology (1970s)Simple logic gatesSimple logic gates

Use transistors toUse transistors toimplement combinationalimplement combinationaland sequential logicand sequential logic

InterconnectInterconnectWires to connect inputs andWires to connect inputs andoutputs to logic blocksoutputs to logic blocks

I/O blocksI/O blocksSpecial blocks at peripherySpecial blocks at peripheryfor external connectionsfor external connections

Add wires for connectionsAdd wires for connectionsDone when chip is fabricatedDone when chip is fabricated

““mask-programmable logic device”mask-programmable logic device”

Construct any circuitConstruct any circuit

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Evolution of the FPGAEvolution of the FPGA

Early FPGAs Early FPGAs Used mainly for “glue logic” between other components Used mainly for “glue logic” between other components (interfacing)(interfacing)Simple Combinational Logic Blocks (CLBs)Simple Combinational Logic Blocks (CLBs)Small number of inputs and outputsSmall number of inputs and outputsFocus was on implementing “random” logic efficientlyFocus was on implementing “random” logic efficiently

As capacities grew, other applications emergedAs capacities grew, other applications emergedFPGAs used as an alternative to custom IC’s for entire FPGAs used as an alternative to custom IC’s for entire applicationsapplicationsComputing with FPGAsComputing with FPGAs

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Evolution of the FPGAEvolution of the FPGA

FPGAs have changed to meet new application FPGAs have changed to meet new application demandsdemands

Carry chains, better support for multi-bit operationsCarry chains, better support for multi-bit operations

Integrated memories, such as the block RAMs Integrated memories, such as the block RAMs

Specialized units, such as multipliers, to implement Specialized units, such as multipliers, to implement functions that are slow/inefficient in CLBsfunctions that are slow/inefficient in CLBs

Newer devices incorporate entire CPUs: Newer devices incorporate entire CPUs: Xilinx Virtex II Pro has 1-4 Power PC CPUs Xilinx Virtex II Pro has 1-4 Power PC CPUs

Devices that don’t have CPU hardware generally support Devices that don’t have CPU hardware generally support synthesized CPUssynthesized CPUs

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Current FPGAs: Major ElementsCurrent FPGAs: Major Elements

ProgrammabilityProgrammabilityTechnology used to program deviceTechnology used to program device

Internal logic cell structureInternal logic cell structureCombinational and sequentialCombinational and sequential

Complexity Complexity

Routing mechanismsRouting mechanismsInterconnecting wires and their layoutInterconnecting wires and their layout

Current commercial FPGAs have the same general Current commercial FPGAs have the same general structure but differ among major components:structure but differ among major components:

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The Plan for TodayThe Plan for Today

We will look at a generalized overview of FPGAs We will look at a generalized overview of FPGAs and their structureand their structure

More of our examples than not will be from Xilinx More of our examples than not will be from Xilinx devicesdevices

Since that is what we use in the labSince that is what we use in the lab

Since they are recognized as a leading vendorSince they are recognized as a leading vendor

Over the next few meetings, we will look at greater Over the next few meetings, we will look at greater detail about the major FPGA elements and familiesdetail about the major FPGA elements and families

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General FPGA ArchitectureGeneral FPGA Architecture

Logic cell, often called a CLB – “configurable logic block”

Routing mechanism

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Field-Programmable Gate ArraysField-Programmable Gate Arrays

Based on Configurable Logic Blocks (CLB) as the Based on Configurable Logic Blocks (CLB) as the logic cells …logic cells … CLB CLB CLB CLBCLB CLB CLB

CLB CLB CLB CLBCLB CLB CLB






CLB

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Current FPGAs: Logic CellsCurrent FPGAs: Logic Cells

Transistor pairsTransistor pairsBasic small gatesBasic small gates

e.g., two-input NAND or XORe.g., two-input NAND or XOR

Multiplexers Multiplexers Look-up tables (LUTs)Look-up tables (LUTs)Wide-fan-in AND-OR structuresWide-fan-in AND-OR structuresMicroprocessor-like Microprocessor-like

Current commercial FPGAs use logic cells that are Current commercial FPGAs use logic cells that are based one one or more of the following:based one one or more of the following:

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Requires some form of programmable interconnect Requires some form of programmable interconnect at crossovers …at crossovers … CLB CLB CLB CLBCLB CLB CLB







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Current FPGAs: ProgrammingCurrent FPGAs: Programming

Static RAMStatic RAMSwitch is a pass transistor controlled by the state of the Switch is a pass transistor controlled by the state of the SRAM bitSRAM bit

EEPROMEEPROMSwitch is a floating-gate transistor that can be turned off Switch is a floating-gate transistor that can be turned off by injecting charge onto its floating gateby injecting charge onto its floating gate

AntifuseAntifuseSwitch is a device that, when electrically programmed, Switch is a device that, when electrically programmed, forms a low resistance pathforms a low resistance path

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Current FPGAs versus MPLDsCurrent FPGAs versus MPLDs

Programmable switches Programmable switches occupy larger chip areasoccupy larger chip areas

exhibit higher parasitic resistance and capacitance (power exhibit higher parasitic resistance and capacitance (power dissipation and propagation delay result)dissipation and propagation delay result)

Additional chip area required for switch Additional chip area required for switch programming circuitryprogramming circuitry

The more switches, the more flexibleThe more switches, the more flexible

Flexibility requires higher “overhead”Flexibility requires higher “overhead”

FPGAs are slower than MPLDsFPGAs are slower than MPLDs

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Current FPGAs: ProgrammingCurrent FPGAs: Programming

FPGAFPGA

SRAM-programmed

Antifuse-programmed

EPROM-programmed

Actel ACT1 & 2Quicklogic’s pASICCrosspoint’s CP20K

Island Cellular

Xilinx LCAAT&T OrcaAltera Flex

ToshibaPlesser’s ERAAtmel’s CLi

Altera’s MAXAMD’s MachXilinx’s EPLD

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FPGA ArchitecturesFPGA Architectures

FPGAs are commercially available in many different architectures and organizations.

Although each company’s offerings have unique characteristics, FPGA architectures can be generically classified into one of four categories:

Symmetrical Array

Row Based

Hierarchical PLD

Sea of Gates

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FPGA ArchitecturesFPGA ArchitecturesThe Configurable Logic Blocks (CLBs) are organized in a two dimensional array separated by horizontal and vertical wiring channels.

Each CLB contains flip-flop(s), multiplexers, and a combinatorial function block which operates as an SRAM based table look-up.

Connections between CLBs are customized by turning on pass transistors which selectively connect the CLBs to the interconnection resources

CLB

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FPGA ArchitecturesFPGA ArchitecturesPass transistors selectively connect the interconnect lines between the horizontal and vertical wiring channels. SRAM cells which are distributed around the chip hold the state of the interconnect switches. Surrounding the CLB array and interconnect channels are the programmable I/O blocks which connect to the package pins.

CLB

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Xilinx XC4000 FPGAXilinx XC4000 FPGA

Greater logic capacity per CLB is achieved using a two-level look-up table

Compared to earlier families, the routing resources have been more than doubled.

number of globally distributed signals has increased

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FPGA ArchitecturesFPGA ArchitecturesThis organization is similar to that This organization is similar to that found in the traditional style of found in the traditional style of Mask Programmed Gate Arrays Mask Programmed Gate Arrays (MPGAs). (MPGAs).

Vertical interconnect segments of Vertical interconnect segments of varying lengths are available. varying lengths are available.

Vertical segments in input tracks Vertical segments in input tracks are permanently connected to logic are permanently connected to logic module inputs, and vertical module inputs, and vertical segments in output tracks are segments in output tracks are permanently connected to logic permanently connected to logic module outputs. module outputs.

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FPGA ArchitecturesFPGA ArchitecturesLong vertical segments are Long vertical segments are available which are uncommitted available which are uncommitted and can be assigned during and can be assigned during routing. routing.

The horizontal wiring channel The horizontal wiring channel resources are also segmented into resources are also segmented into varying lengths. varying lengths.

The minimum horizontal segment The minimum horizontal segment length is the width of a single logic length is the width of a single logic module, and the maximum module, and the maximum horizontal segment length spans horizontal segment length spans the full channel.the full channel.

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Any segment that spans Any segment that spans more than one-third of the more than one-third of the row length is considered a row length is considered a “long horizontal segment”. “long horizontal segment”.

Dedicated routing tracks are Dedicated routing tracks are used for global clock used for global clock distribution and for power distribution and for power and ground tie-off and ground tie-off connections.connections.

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The Actel ACT family FPGAs a logic module matrix is arranged as rows of cells separated by horizontal wiring channels

This organization is similar to that found in the traditional style of Mask Programmed Gate Arrays (MPGAs)

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This architecture represents a hierarchical arrangement of CLBs using a two-dimensional array structure.

Interconnections are via a centralized programmable interconnect structure

CLBs can be cascaded

I/O structures not shown

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FPGA ArchitecturesFPGA ArchitecturesThe Altera Multiple Array MatriX (MAX) architecture represents a hierarchical arrangement of Erasable Programmable Logic Devices (EPLDs) using a two-dimensional array structure.

The design provides multiple level logic, uses a programmable routing structure, and is user reprogrammable based on EPROM or EEPROM technology.

LAB A LAB H

LAB B LAB G

LAB C LAB F

LAB D LAB E

P I A

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this design has a two-dimensional mesh array structure which resembles the gate array “sea of gates”

Static RAM programming technology is used to specify the function performed by each logic cell and to control the switching of connections between cells.

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FPGA ArchitecturesFPGA ArchitecturesThe CAL1024 design contains 1024 identical logic cells arranged in a 32 X 32 matrix. The design is considered to be a mesh-connected architecture since each cell is directly connected to its nearest north, south, east, and west neighbors.In addition to these direct connects, two global interconnect signals are routed to each cell to distribute clock and other “low skew requirement” control signals.

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Xilinx Spartan-3 die image; note the regularity…Xilinx Spartan-3 die image; note the regularity…

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Field Programmable Gate ArraysField Programmable Gate Arrays

Xilinx FPGAs are based on Look-up Tables (LUTs) as the CLB.

A LUT is simply a representation of a truth table:

three-input Look-Up Table

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

F 1 0 1 0 0 0 1 1

FPGAs are just a whole lot of LUTs with lots of interconnect

abc

f10100011LUT

three-input truth table

The function is programmable – any LUT can be programmed to be any function

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Synthesizing Functions to CLBsSynthesizing Functions to CLBs

Flexibility of CLBs is a big win -- much harder to Flexibility of CLBs is a big win -- much harder to map to technology with less-flexible blocksmap to technology with less-flexible blocks

Basically, can divide logic into n-input functions, Basically, can divide logic into n-input functions, map each onto a CLB.map each onto a CLB.

Tools may have special-purpose routines for Tools may have special-purpose routines for common blocks (like adders)common blocks (like adders)

Harder problem: Placing blocks to minimize Harder problem: Placing blocks to minimize communication, particularly when using carry communication, particularly when using carry chainschains

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FPGA OrganizationFPGA Organization

abc

fxxxxxxxx LUT

abc

fxxxxxxxx LUT

abc

fxxxxxxxx LUT

abc

fxxxxxxxx LUT

abc

fxxxxxxxx LUT

abc

fxxxxxxxx LUT

I/O1

I/O2

I/O3

I/O4

00110111

11011010

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FPGAsFPGAs

Xilinx FPGAs are based on SRAMXilinx FPGAs are based on SRAMLose programming when power is turned offLose programming when power is turned off

Can be programmed by a computer or by a special Can be programmed by a computer or by a special EPROMEPROM

CapacityMay have up to 10,000,000 gate equivalent

Up to 1,200 I/O pins

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FPGAsFPGAs

FPGAs must add some kind of switch to the FPGAs must add some kind of switch to the equation to be user programmable.equation to be user programmable.

The size and performance of the switch essentially The size and performance of the switch essentially determines the architecturedetermines the architecture

ULM (Universal Logic Module) must be as small ULM (Universal Logic Module) must be as small as possible to maximize versatility and utilizationas possible to maximize versatility and utilization

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What’s in a CLB?What’s in a CLB?

Look-Up Table (LUT)

State

OutInputs

Clock

Enable

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CLB VariablesCLB Variables

Number of inputs to LUTNumber of inputs to LUTTrade off number of CLBs required vs. size of CLB and Trade off number of CLBs required vs. size of CLB and routing arearouting area

How is logic implementedHow is logic implementedLUT vs. programmable and-or-invert vs. otherLUT vs. programmable and-or-invert vs. other

Technology used to hold configuration (program) of CLBTechnology used to hold configuration (program) of CLB

Flip-flop in CLB?Flip-flop in CLB?

Additional FunctionalityAdditional FunctionalityCarry chainsCarry chains

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Switch DetailSwitch Detail

Programmable Programmable Switch MatrixSwitch Matrix

Connections Connections are controlled are controlled by RAM bitsby RAM bits

More laterMore later

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Programmable Switch MatrixProgrammable Switch Matrix

programmable switch element

turning the corner, etc.

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The Fitter’s JobThe Fitter’s Job

Partition logic functions into CLBsPartition logic functions into CLBsArrange the CLBsArrange the CLBsInterconnect the CLBsInterconnect the CLBsMinimize the number of CLBs usedMinimize the number of CLBs usedMinimize the size and delay of interconnect usedMinimize the size and delay of interconnect usedWork with constraintsWork with constraints

““Locked” I/O pinsLocked” I/O pinsCritical-path delaysCritical-path delaysSetup and hold times of storage elementsSetup and hold times of storage elements

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Input-Output BlocksInput-Output Blocks

One IOB per FPGA pinOne IOB per FPGA pinAllows pin to be used as input, output, or bidirectional Allows pin to be used as input, output, or bidirectional (tri-state)(tri-state)

InputsInputsDirectDirect

RegisteredRegistered

Drive dedicated decoder logic for address recognitionDrive dedicated decoder logic for address recognition

IOB may also include logic for boundary scan IOB may also include logic for boundary scan (JTAG)(JTAG)

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I/O blocksI/O blocks

Looks like Looks like a CPLD a CPLD macrocellmacrocell

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Xilinx 4000-series FPGAsXilinx 4000-series FPGAs

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FPGAs: SummaryFPGAs: Summary

Historically, FPGA architectures and companies Historically, FPGA architectures and companies began around the same time as CPLDsbegan around the same time as CPLDs

FPGAs are closer to “programmable ASICs” - large FPGAs are closer to “programmable ASICs” - large emphasis on interconnection routingemphasis on interconnection routing

Timing is difficult to predict - multiple hops vs. the fixed Timing is difficult to predict - multiple hops vs. the fixed delay of a CPLD’s switch matrix.delay of a CPLD’s switch matrix.

But more “scalable” to large sizes.But more “scalable” to large sizes.

FPGA configurable logic blocks have a few inputs FPGA configurable logic blocks have a few inputs and 1-2 flip-flops, but there are many more of them and 1-2 flip-flops, but there are many more of them compared to the number of macrocells in a CPLD.compared to the number of macrocells in a CPLD.

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Common CPLD & FPGA ProblemsCommon CPLD & FPGA Problems

Pin lockingPin lockingSmall changes, and certainly large ones, can cause the fitter Small changes, and certainly large ones, can cause the fitter to pick a different allocation of I/O blocks and pinout.to pick a different allocation of I/O blocks and pinout.

Locking too early may make the resulting circuit slower or Locking too early may make the resulting circuit slower or not fit at all.not fit at all.

Running out of resourcesRunning out of resourcesDesign may “blow up” if it doesn’t all fit on a single device.Design may “blow up” if it doesn’t all fit on a single device.

On-chip interconnect resources are much richer than off-On-chip interconnect resources are much richer than off-chip.chip.

Larger devices are exponentially more expensive.Larger devices are exponentially more expensive.

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FPGAs: ProsFPGAs: Pros

Reasonably CheapReasonably CheapGood for low-volume parts, more expensive than IC for high-volume Good for low-volume parts, more expensive than IC for high-volume partsparts

Short Design Cycle (~1sec programming time)Short Design Cycle (~1sec programming time)

ReprogrammableReprogrammableCan download bug fix into units you’ve already shippedCan download bug fix into units you’ve already shipped

Large capacity (4 million gates or so, though we won’t use Large capacity (4 million gates or so, though we won’t use any that big)any that big)

FPGAs in the lab are “rated” at 300K gatesFPGAs in the lab are “rated” at 300K gates

More flexible than PLDs -- can have internal stateMore flexible than PLDs -- can have internal state

More compact than MSI/SSIMore compact than MSI/SSI

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FPGAs: ConsFPGAs: Cons

Lower capacity, speed and higher power Lower capacity, speed and higher power consumption than building an integrated circuitconsumption than building an integrated circuit

Sub-optimal mapping of logic into CLB’sSub-optimal mapping of logic into CLB’s

Less dense layout and placement due to programmabilityLess dense layout and placement due to programmability

Overhead of configurable interconnect and logic blocksOverhead of configurable interconnect and logic blocks

PLDs may be faster than FPGA for designs they can PLDs may be faster than FPGA for designs they can handlehandle

Need sophisticated tools to map design to FPGANeed sophisticated tools to map design to FPGA

cset 4650 field programmable logic devices dan solarek introduction to fpgas field programmable gate...

Documents

glue logic

current fpgas

configurable logic blocks

fpgaearly fpgas

gate arraysparallel

gate array technology

layoutcurrent commercial

generalized overview