CSET 4650 CSET 4650 Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan SolarekDan SolarekDan Solarek

Introduction to CPLDsIntroduction to CPLDsComplex Programmable Complex Programmable

Logic DevicesLogic Devices

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Logic Circuit ImplementationLogic Circuit Implementation

We can implement a logic design with many We can implement a logic design with many different implementation technologies.different implementation technologies.Different implementation technologies offer a Different implementation technologies offer a variety of design/performance tradeoffs.variety of design/performance tradeoffs.VHDL synthesis offers an easy way to target a VHDL synthesis offers an easy way to target a model towards specific implementations.model towards specific implementations.There are also retargetting tools which will convert a There are also retargetting tools which will convert a netlist from one technology to another (e.g., from a netlist from one technology to another (e.g., from a standard cell implementation to a Field standard cell implementation to a Field Programmable Gate Array implementation).Programmable Gate Array implementation).

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Logic Circuit ImplementationLogic Circuit Implementation

Available implementation technologies include:Available implementation technologies include:Full Custom ICsFull Custom ICs

Standard CellsStandard Cells

Gate ArraysGate Arrays

Field Programmable Gate Arrays (FPGAs)Field Programmable Gate Arrays (FPGAs)

Complex PLDs (CPLDs)Complex PLDs (CPLDs)

Simple Programmable Logic Devices (SPLDs)Simple Programmable Logic Devices (SPLDs)

Standard SSI/MSI LogicStandard SSI/MSI Logic

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Hierarchy of Logic ImplementationsHierarchy of Logic Implementations

AcronymsSPLD = Simple Prog. Logic Device PAL = Prog. Array of LogicCPLD = Complex PLDFPGA = Field Prog. Gate ArrayASIC = Application Specific IC

Common ResourcesCommon ResourcesConfigurable Logic Blocks (CLB)Configurable Logic Blocks (CLB)

Memory Look-Up Table (LUT)Memory Look-Up Table (LUT)AND-OR planesAND-OR planesSimple gatesSimple gates

Input / Output Blocks (IOB)Input / Output Blocks (IOB)Bidirectional, latches, inverters, pullup/pulldownsBidirectional, latches, inverters, pullup/pulldowns

Interconnect or RoutingInterconnect or RoutingLocal, internal feedback, and globalLocal, internal feedback, and global

Logic

StandardLogic

ASIC

ProgrammableLogic Devices

(FPLDs)

GateArrays

Cell-BasedICs

Full CustomICs

CPLDsSPLDs(e.g., PALs) FPGAs

today’s focus

examine brieflyexamine briefly

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Semicustom DevicesSemicustom DevicesGate ArraysGate Arrays

Gates already fabricated Gates already fabricated

Interconnecting metalization used to customize designInterconnecting metalization used to customize design

Cell-based ICs – Standard CellsCell-based ICs – Standard CellsSimilar to PCB layout, but using predefined cellsSimilar to PCB layout, but using predefined cells

More efficient, but requires full mask setMore efficient, but requires full mask set

These mask-programmed devices are ‘customized’ These mask-programmed devices are ‘customized’ by manufacturerby manufacturer

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Range of ASIC Design StylesRange of ASIC Design Styles

Gates

Routing Channel

Gates

Routing Channel

Gates

StandardALU

Standard Registers

Gates

Cus

tom

Con

trol

Log

ic

CustomRegister File

Custom DesignStandard CellGate Array

CustomALU

Generally, these devices are not field programmable or reprogrammable.

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Gate ArrayGate Array

A Gate Array consists of three parts:A Gate Array consists of three parts:

I/O pad areaI/O pad area

I/O buffer areaI/O buffer area

internal cell area internal cell area

Customized by Customized by metalization to metalization to interconnect basic interconnect basic gatesgates

Vendor does thisVendor does this

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Gate ArraysGate Arrays

Designer uses a library of standard cells. Designer uses a library of standard cells. The design is mapped onto an array of transistors which is already The design is mapped onto an array of transistors which is already created on a wafer; wafers with transistor arrays can be created ahead created on a wafer; wafers with transistor arrays can be created ahead of time. of time.

A routing tool creates the masks for the routing layers and A routing tool creates the masks for the routing layers and "customizes" the pre-created gate array for the user's design."customizes" the pre-created gate array for the user's design.

Transistor density can be almost as good as standard cell.Transistor density can be almost as good as standard cell.

Design time advantages are the same as for standard cell.Design time advantages are the same as for standard cell.

Performance can be very good; again, depends on quality of Performance can be very good; again, depends on quality of available library and routing tools.available library and routing tools.

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Gate ArraysGate Arrays

Fabrication costs are lower than standard cells or full custom Fabrication costs are lower than standard cells or full custom because the gate array wafers are mass produced.because the gate array wafers are mass produced.

the non recurring engineering costs are lower because only a few (1-the non recurring engineering costs are lower because only a few (1-3) unique routing masks have to be created for each design3) unique routing masks have to be created for each design

Fabrication time can be extremely short (1-2 weeks) because Fabrication time can be extremely short (1-2 weeks) because the wafers are already created and are only missing the the wafers are already created and are only missing the routing layers.routing layers.

the more routing layers, the higher the cost, the longer the fabrication the more routing layers, the higher the cost, the longer the fabrication time, but the better usage of the available transistors on the gate arraytime, but the better usage of the available transistors on the gate array

Almost all high volume production of complex digital Almost all high volume production of complex digital designs are done using Standard Cells or Gate Arrays.designs are done using Standard Cells or Gate Arrays.

gate arrays used to be more popular, but recently standard cells has gate arrays used to be more popular, but recently standard cells has shown a resurgence in useshown a resurgence in use

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Standard CellsStandard Cells

based on optimum-sized logic based on optimum-sized logic cellscells

library elements are prepared by library elements are prepared by the ASIC vendor at transistor level the ASIC vendor at transistor level (building block type) using (building block type) using various transistor sizes various transistor sizes

library elements are placed on the library elements are placed on the logic areas during physical logic areas during physical implementationimplementation

higher degree of integration higher degree of integration than gate arrays than gate arrays

faster than FPGAsfaster than FPGAs

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Standard CellsStandard Cells

One vendor’s list of standard cellsOne vendor’s list of standard cells

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Standard CellsStandard Cells

Designer uses a library of standard cellsDesigner uses a library of standard cellsan automatic place and route tool does the layoutan automatic place and route tool does the layout

designer does not have to be a VLSI expertdesigner does not have to be a VLSI expert

Transistor density and performance degradation Transistor density and performance degradation depends on type of design being done.depends on type of design being done.

not bad for random logicnot bad for random logic

can be significant for datapath type designscan be significant for datapath type designs

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Standard CellsStandard Cells

Quality of available libraries and design tools make Quality of available libraries and design tools make a significant difference in results.a significant difference in results.

Design time can be much faster than full custom Design time can be much faster than full custom because layout is automatically generated.because layout is automatically generated.

Still involves creation of custom chip Still involves creation of custom chip all masks must still be madeall masks must still be made

manufacturing costs same as full custom.manufacturing costs same as full custom.

Fabrication time is the same as for full custom.Fabrication time is the same as for full custom.

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Full Custom ICsFull Custom ICs

Designer hand draws geometries which specify transistors Designer hand draws geometries which specify transistors and other devices for an integrated circuit.and other devices for an integrated circuit.

Designer must be an expert in VLSI (Very Large Scale Integration) Designer must be an expert in VLSI (Very Large Scale Integration) design.design.

Can achieve very high transistor density (transistors per Can achieve very high transistor density (transistors per square micron); unfortunately, design time can be very long square micron); unfortunately, design time can be very long (many months).(many months).Involves the creation of a a completely new chip, which Involves the creation of a a completely new chip, which consists of about a dozen masks (for the photolitographic consists of about a dozen masks (for the photolitographic manufacturing process).manufacturing process).

Mask creation is the expensive part.Mask creation is the expensive part.

Offers the chance for optimum performance. Offers the chance for optimum performance. Performance is based on available process technology, designer skill, Performance is based on available process technology, designer skill, and CAD tool assistance.and CAD tool assistance.

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Full Custom ICsFull Custom ICs

Fabrication costs are highFabrication costs are highall custom masks must be made so non-recurring engineering costs all custom masks must be made so non-recurring engineering costs (NRE) is high (in the thousands of dollars)(NRE) is high (in the thousands of dollars)

if required number of chips is high then can spread these NRE costs if required number of chips is high then can spread these NRE costs across the chips.across the chips.

The first custom chip costs you about $200,000, but each The first custom chip costs you about $200,000, but each additional one is much cheaper.additional one is much cheaper.

Fabrication time from geometry submission to returned chips Fabrication time from geometry submission to returned chips is at least 6-8 weeks.is at least 6-8 weeks.

Full custom is currently the only option for mixed Full custom is currently the only option for mixed Analog/Digital chips.Analog/Digital chips.

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Three FPLD TypesThree FPLD Types

1.1. Simple Programmable Logic Device (SPLD)Simple Programmable Logic Device (SPLD) LSI deviceLSI device Less than 1000 logic gatesLess than 1000 logic gates

2.2. Complex Programmable Logic Device (CPLD)Complex Programmable Logic Device (CPLD) VLSI deviceVLSI device Higher logic capacity than SPLDsHigher logic capacity than SPLDs

3.3. Field Programmable Gate Array (FPGA)Field Programmable Gate Array (FPGA) VLSI deviceVLSI device Higher logic capacity than CPLDsHigher logic capacity than CPLDs

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SPLDsSPLDsSimple PLDsSimple PLDsPopular SPLD Architecture TypesPopular SPLD Architecture Types

Programmable Logic Array, PLAProgrammable Logic Array, PLAProgrammable Array Logic, PAL (Vantis)Programmable Array Logic, PAL (Vantis)General Array Logic, GAL (Lattice)General Array Logic, GAL (Lattice)

Architecture DifferencesArchitecture DifferencesAND versus OR implementationAND versus OR implementationProgrammability (e.g., EE)Programmability (e.g., EE)Fundamental logical blockFundamental logical block

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SPLDsSPLDsConventional programmable logic (PALs, PLAs, GALs) Conventional programmable logic (PALs, PLAs, GALs)

standard parts like GAL22V10 and PAL16R4 are available from standard parts like GAL22V10 and PAL16R4 are available from multiple vendorsmultiple vendors

Includes programmable logic cells to a limited degree Includes programmable logic cells to a limited degree (programming options in I/O cells, may have fixed AND/OR (programming options in I/O cells, may have fixed AND/OR gates for logic), limited routing network. gates for logic), limited routing network.

Lowest density of all programmable devices, however, can Lowest density of all programmable devices, however, can offer very high performance. offer very high performance.

SPLDs have nearly replaced TTL SPLDs have nearly replaced TTL logic which used to be the normal logic which used to be the normal approach to logic implementationapproach to logic implementation

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CPLDsCPLDs

Complex PLDsComplex PLDs

CompositionCompositiontypically composed of 2-64 SPLDstypically composed of 2-64 SPLDs

interconnected using sophisticated logicinterconnected using sophisticated logic

includes macrocells – more about these laterincludes macrocells – more about these later

Economical for designing large systemsEconomical for designing large systems

Fast – switching speedFast – switching speed

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CPLDsCPLDsPALs and GALs are available only in small sizesPALs and GALs are available only in small sizes

equivalent to a few hundred logic gatesequivalent to a few hundred logic gates

For bigger logic circuits, complex PLDs or CPLDs can be For bigger logic circuits, complex PLDs or CPLDs can be used. used. CPLDs contain the equivalent of several PALs/GALs CPLDs contain the equivalent of several PALs/GALs

linked by programmable interconnectionslinked by programmable interconnectionsall in one integrated circuit (IC)all in one integrated circuit (IC)

CPLDs can replace thousands, or even hundreds of CPLDs can replace thousands, or even hundreds of thousands, of individual logic gates thousands, of individual logic gates

increased integration densityincreased integration density

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CPLDsCPLDs

Complex PLD's have arrays of PLD's on one chip, with an Complex PLD's have arrays of PLD's on one chip, with an interconnection matrix connecting them.interconnection matrix connecting them.

Timing peformance can be more predictable than FPGAs Timing peformance can be more predictable than FPGAs because of simpler interconnect structure. because of simpler interconnect structure.

Density is normally less than most FPGAs (although high Density is normally less than most FPGAs (although high end CPLDs will have about the same densisty as low-end end CPLDs will have about the same densisty as low-end FPGAs).FPGAs).

Performance of CPLDs is usually Performance of CPLDs is usually better than FPGAs, but depends on better than FPGAs, but depends on vendor, number of cells in CPLD, vendor, number of cells in CPLD, and compared FPGA.and compared FPGA.

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CPLDsCPLDs

The block diagram at The block diagram at left for the Cypress left for the Cypress Semiconductor CPLD Semiconductor CPLD (37000 family) (37000 family) illustrates the general illustrates the general architecture of CPLDsarchitecture of CPLDs

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CPLDsCPLDs

CComplex omplex PProgrammable rogrammable LLogic ogic DDevicesevicesContain from 10-1000 macrocellsContain from 10-1000 macrocellsEach macrocell is equivalent to around 20 gatesEach macrocell is equivalent to around 20 gatesSupport up to 200 I/O pinsSupport up to 200 I/O pins

The key resource in a CPLD is the programmable interconnect

Tradeoff between space for macrocells and space for interconnectCareful design will limit the connections between macrocells

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FPGAsFPGAs

Field Programmable Gate ArraysField Programmable Gate Arrays

The term FPGA is a generic term used to describe The term FPGA is a generic term used to describe the highest density programmable logic devices the highest density programmable logic devices currently available.currently available.

Similar to microprocessors in complexitySimilar to microprocessors in complexity

Slower than CPLDs – switching speedsSlower than CPLDs – switching speeds

Very low mass production costVery low mass production cost

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FPGAsFPGAs

There are many different types from many different There are many different types from many different vendors.vendors.

Composition:Composition:64 to 10’s of thousands of logic blocks and flip-flops64 to 10’s of thousands of logic blocks and flip-flops

highest logic capacity of PLDshighest logic capacity of PLDs

A single FPGA can replace tens of normal PLDsA single FPGA can replace tens of normal PLDsi.e., 22V10 type PLDsi.e., 22V10 type PLDs

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FPGAsFPGAsThe principle difference between PLDs and FPGAs The principle difference between PLDs and FPGAs are:are:

Primitive FPGA 'logic cells' are more complex than PLD Primitive FPGA 'logic cells' are more complex than PLD cells.cells.Can program the routing between FPGA logic cells in Can program the routing between FPGA logic cells in addition to programming the logic cells themselves.addition to programming the logic cells themselves.Many FPGAs now offer embedded memory blocks in Many FPGAs now offer embedded memory blocks in addition to logic blocks or other special features such as addition to logic blocks or other special features such as fast carry logic chains.fast carry logic chains.

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FPGAsFPGAsDesign time advantages are the same as for standard cell.Design time advantages are the same as for standard cell.

Performance is usually several factors to an order of Performance is usually several factors to an order of magnitude lower than standard cell. magnitude lower than standard cell.

Performance depends heavily on quality of FPGA technology.Performance depends heavily on quality of FPGA technology.

Densities are an order of magnitude lower than standard cell Densities are an order of magnitude lower than standard cell but an order of magnitude higher than normal PLDs.but an order of magnitude higher than normal PLDs.

Very good for prototype design Very good for prototype design because many FPGAs are re-usable. because many FPGAs are re-usable.

Can be used to prototype and verify Can be used to prototype and verify designs before investing in technologies designs before investing in technologies with high start-up costs (e.g. full with high start-up costs (e.g. full custom). custom).

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FPGAsFPGAsCan manufacture the first few boards of a new product using Can manufacture the first few boards of a new product using FPGAs and then replace with Gate Arrays when the FPGAs and then replace with Gate Arrays when the production ramps up.production ramps up.FPGAs can be programmed on your desktop so fabrication FPGAs can be programmed on your desktop so fabrication time is not an issue. time is not an issue.

One of the attractions of FPGAs is the ability to prototype very One of the attractions of FPGAs is the ability to prototype very quicklyquickly

FPGAs offer the ability to fix bugs in a design without FPGAs offer the ability to fix bugs in a design without patching the Printed Circuit Board (PCB). patching the Printed Circuit Board (PCB).

Can be a career saver!Can be a career saver!

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Field-Programmable Gate Array (FPGA)Field-Programmable Gate Array (FPGA)

A field-programmable gate array (FPGA) is an A field-programmable gate array (FPGA) is an FPLD featuring a general structure that allows very FPLD featuring a general structure that allows very high logic capacity. high logic capacity.

CPLDs feature logic resources with a wide number of CPLDs feature logic resources with a wide number of inputs (AND planes)inputs (AND planes)

FPGAs offer narrower logic resourcesFPGAs offer narrower logic resources

FPGAs offer a higher ratio of flip-flops to logic FPGAs offer a higher ratio of flip-flops to logic resources than do CPLDs.resources than do CPLDs.

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Xilinx XC9500 CPLD Series

Devices designed for 2.5V, 3.3V, and 5V applications

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Programmability OptionsProgrammability Options

PLDs, CPLDs, and FPGAs have different types of PLDs, CPLDs, and FPGAs have different types of programmability.programmability.

initial programming and reprogramminginitial programming and reprogramming

One-time programmable: One-time programmable: device is programmed once and holds its programming device is programmed once and holds its programming "forever" "forever"

usually uses fuses to make/break linksusually uses fuses to make/break links

not reusable, but usually the cheapestnot reusable, but usually the cheapest

discard device if changes are to be madediscard device if changes are to be made

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Programmability OptionsProgrammability Options

UV-Erasable: UV-Erasable: programming is erasable with UV light programming is erasable with UV light

needs a ceramic package with a window above the chip needs a ceramic package with a window above the chip areaarea

package complexity adds expense to devicepackage complexity adds expense to device

usually remove socketed chip to erase/reprogram usually remove socketed chip to erase/reprogram

programming retained after power downprogramming retained after power downnon-volatile non-volatile

programming/erasing limited to 1000s of cyclesprogramming/erasing limited to 1000s of cycles

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Programmability OptionsProgrammability Options

Electrically Erasable: Electrically Erasable: both erasing and reprogramming is accomplished with an both erasing and reprogramming is accomplished with an electrical current electrical current

device can be programmed/erased on circuit board, no device can be programmed/erased on circuit board, no special packaging or IC socket is needed special packaging or IC socket is needed

erase time is much faster than UV erase erase time is much faster than UV erase

programming retained after power downprogramming retained after power downnon-volatilenon-volatile

programming/erasing limited to 1000s of cyclesprogramming/erasing limited to 1000s of cycles

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Electrically Erasable PLDsElectrically Erasable PLDs

Conventional PLDs are either Conventional PLDs are either One-time programmableOne-time programmable

UV ErasableUV Erasable

Must be placed Must be placed in a programmerin a programmer to program them to program them

EE PLDs can be programmed and erased in placeA small (four wire) connection to a computer is needed

Once programmed, will retain program indefinitely

Never have to take the chip out of its circuit

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Programmability OptionsProgrammability Options

Static Random Access Memory (SRAM) Static Random Access Memory (SRAM) Programming: Programming:

configuration bits are stored in SRAM configuration bits are stored in SRAM can be reprogrammed infinite number of timescan be reprogrammed infinite number of timesprogramming contents NOT retained after power downprogramming contents NOT retained after power down

FPGA must be 'configured' every time on power upFPGA must be 'configured' every time on power up

external non-volatile memory device required to hold external non-volatile memory device required to hold device programmingdevice programming

on power up contents of external device transferred to FPGA to on power up contents of external device transferred to FPGA to configure the device.configure the device.

Altera, Xilinx corporations offer this type of FPGAsAltera, Xilinx corporations offer this type of FPGAs

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FPLD Programming TechnologiesUser-programmable switches are the key to user customization of User-programmable switches are the key to user customization of FPLDs. FPLDs.

The first user-programmable switch developed was the fuse used in The first user-programmable switch developed was the fuse used in PLAs (only used in smaller devices).PLAs (only used in smaller devices).

For CPLDs, the main switch technologies (in commercial products) are For CPLDs, the main switch technologies (in commercial products) are floating gate transistors like those used in EPROM (erasable floating gate transistors like those used in EPROM (erasable programmable read-only memory) and EEPROM (electrically erasable programmable read-only memory) and EEPROM (electrically erasable PROM). PROM). For FPGAs, they For FPGAs, they are SRAM (static are SRAM (static RAM) and RAM) and antifuse.antifuse.

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FPLD Capacities

“Equivalent gates” refers loosely to the number of two-input NAND gates.

The chart serves as a guide for selecting a device for an application according to the logic capacity needed.

Each type of FPLD is inherently better suited for some applications than for others.

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Digital Technology TradeoffsDigital Technology Tradeoffs

S

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Which Implementation Technology?Which Implementation Technology?

Economic versus technical factorsEconomic versus technical factors

SPLDSSI/MSI

semicustomtechnologies

CPLDFPGA

GateArray

Std.Cell

FullCustom

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Evolution of ImplementationsEvolution of Implementations

1960

1970

1980

1990

2000

SSI

MSI

LSI

VLSI

‘standard components’

‘semicustom components’

Gate Array

Standard CellsSimple PLD

CPLD FPGA

parallel development

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Economic FactorsEconomic Factors

Overhead ...

Cost Testing

CostUnit Volume

cost NREcost Component

NRE = Non Recurring Engineering

Essentially the cost to design the device

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  SSI/MSI SPLD FPGA Gate array

Standard cell

Full custom

Gates/component

5 - 100

50 - 5K

100 -10K

500 -100K

10K -500K

100K -10M

Cost/gate High         Low

NRE cost ($) - 1-2K 2-10K 5-50K 10-100K 50K-5M

Development time (weeks)

- 1-2 1-2 2-20 5-50 20-200

Comparison of ImplementationComparison of Implementation

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Comparison of ImplementationsComparison of Implementations

Circuit cost as a function of volume

Discrete

Full custom

Volume

Cost

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Comparison of ImplementationsComparison of Implementations

Density (gates per chip)Density (gates per chip)Highest to lowest density: Full Custom, Standard Cell, Gate Array, Highest to lowest density: Full Custom, Standard Cell, Gate Array, FPGAs, CPLDs, SPLDs FPGAs, CPLDs, SPLDs

Performance Performance Highest to lowest performance: Full Custom, Standard Cell, Gate Highest to lowest performance: Full Custom, Standard Cell, Gate Array, SPLDs, CPLDs, FPGAs.Array, SPLDs, CPLDs, FPGAs.Performance of programmable technologies is in reverse order of Performance of programmable technologies is in reverse order of their densities.their densities.

Cost comparisonCost comparisonDepends heavily on volume. If only a few hundred are needed, then Depends heavily on volume. If only a few hundred are needed, then FPGAs can be cheaper. If thousands are needed, then non-FPGAs can be cheaper. If thousands are needed, then non-programmable technologies may be cheaper.programmable technologies may be cheaper.

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SummarySummary

Full custom ICs can yield the best density and overall Full custom ICs can yield the best density and overall performance.performance.Faster design time and ease of design are the main Faster design time and ease of design are the main advantages of gate arrays and standard cells over full advantages of gate arrays and standard cells over full custom.custom.Fast fabrication time and lower cost are the main Fast fabrication time and lower cost are the main advantages of gate arrays over standard cells.advantages of gate arrays over standard cells.Gate arrays offer much higher density over FPGAs Gate arrays offer much higher density over FPGAs and are cheaper than FPGAs in volume production.and are cheaper than FPGAs in volume production.

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SummarySummary

FPGAs primary advantage over gate arrays is 'instant' FPGAs primary advantage over gate arrays is 'instant' fabrication time (programmed on desktop). fabrication time (programmed on desktop). FPGAs are also cheaper than gate arrays in low FPGAs are also cheaper than gate arrays in low volume. volume.

Densities are reaching 100's of thousands of gates/chip.Densities are reaching 100's of thousands of gates/chip.Can be used to prototype full custom/standard cell designs.Can be used to prototype full custom/standard cell designs.

SPLDs still hold a speed advantage over most FPGAs SPLDs still hold a speed advantage over most FPGAs and are useful for high speed decoding and speed and are useful for high speed decoding and speed critical interface logic.critical interface logic.

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Summary

Most prototypes and many production designs now use FPLDs The most compelling advantages of FPLDs are

low startup costlow financial risk quick manufacturing turnaround easy design changes

The last two advantages are because the end user programs the device