cse/ee 462 l12 rom and pla first look.1
TRANSCRIPT
CSE/EE 462 L12 ROM and PLA First Look.1 Brockman, ND, 2006
CSE/EE 462: VLSI DesignFall 2006
A First Look at ROMs and PLAs
Jay Brockman
[Adapted from Mary Jane Irwin and Vijay Narananan, CSE Penn State
adaptation of Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
CSE/EE 462 L12 ROM and PLA First Look.2 Brockman, ND, 2006
Array-Structured Memory Architecture
column decode
sense amplifiers
row
dec
ode
row address
column address
Din/Dout
All cells on selected row sensed simultaneously
CSE/EE 462 L12 ROM and PLA First Look.3 Brockman, ND, 2006
MOS NOR ROM Cell Array
WL [0]
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
CSE/EE 462 L12 ROM and PLA First Look.4 Brockman, ND, 2006
MOS NOR ROM Layer Assignments
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
GND
Poly and diffusion is patterned for all cells
Use contacts to connect cells with zeros to metal columns
mirroringalternate rowssaves area
CSE/EE 462 L12 ROM and PLA First Look.5 Brockman, ND, 2006
Contact Programmable NOR ROM Layout
+ =
CSE/EE 462 L12 ROM and PLA First Look.6 Brockman, ND, 2006
Row Decoder
WL [0]
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
A1
A0
A1
A0
A1
A0
A1
A0
CSE/EE 462 L12 ROM and PLA First Look.7 Brockman, ND, 2006
Row Decoder
WL [0]
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
NOR
A1
A0NOR
NOR
NOR
A1 A0 A0
look familiar?
CSE/EE 462 L12 ROM and PLA First Look.8 Brockman, ND, 2006
Row Decoders
Collection of 2M complex logic gatesOrganized in regular and dense fashion
(N)AND Decoder
NOR Decoder
CSE/EE 462 L12 ROM and PLA First Look.9 Brockman, ND, 2006
4-input pass-transistor based column decoder
Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal pathDisadvantage: Large transistor count
A0S0
BL 0 BL 1 BL 2 BL 3
A1
S1
S2
S3
D
CSE/EE 462 L12 ROM and PLA First Look.10 Brockman, ND, 2006
Non-Volatile Memories The Floating-gate transistor (FAMOS)
Floating gate
Source
Substrate
Gate
Drain
n+ n+_p
tox
tox
Device cross-section Schematic symbol
G
S
D
CSE/EE 462 L12 ROM and PLA First Look.11 Brockman, ND, 2006
MOS NAND ROM
All word lines high by default with exception of selected row
WL [0]
WL [1]
WL [2]
WL [3]
VDD
Pull-up devices
BL[3]BL [2]BL [1]BL [0]
CSE/EE 462 L12 ROM and PLA First Look.12 Brockman, ND, 2006
NAND Flash Memory
Unit Cell
Word line(poly)
Source line(Diff. Layer)
Courtesy Toshiba
Gate
ONO
FGGateOxide
CSE/EE 462 L12 ROM and PLA First Look.13 Brockman, ND, 2006
NAND Flash Memory
Word linesSelect transistor
Bit line contact Source line contact
Active area
STI
Courtesy Toshiba
CSE/EE 462 L12 ROM and PLA First Look.14 Brockman, ND, 2006
6-transistor CMOS SRAM Cell
WL
BL
VDD
M5M6
M4
M1
M2
M3
BL
CSE/EE 462 L12 ROM and PLA First Look.15 Brockman, ND, 2006
6T-SRAM — Layout
VDD
GND
WL
BLBL
M1 M3
M4M2
M5 M6
CSE/EE 462 L12 ROM and PLA First Look.16 Brockman, ND, 2006
1-Transistor DRAM Cell
Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
M1
CS
WL
BL
CBL
VDD2VT
WL
X
sensing
BL
GND
Write 1 Read 1
VDD
VDD /2 V
V BL VPRE– VBIT VPRE–CS
CS CBL+------------= =V
CSE/EE 462 L12 ROM and PLA First Look.17 Brockman, ND, 2006
1-T DRAM Cell
Uses Polysilicon-Diffusion Capacitance
Expensive in Area
M1 wordline
Diffusedbit line
Polysilicongate
Polysiliconplate
Capacitor
Cross-section Layout
Metal word line
Poly
SiO2
Field Oxiden+ n+
Inversion layerinduced byplate bias
Poly
CSE/EE 462 L12 ROM and PLA First Look.18 Brockman, ND, 2006
SEM of poly-diffusion capacitor 1T-DRAM
CSE/EE 462 L12 ROM and PLA First Look.19 Brockman, ND, 2006
Advanced 1T DRAM Cells
Cell Plate Si
Capacitor Insulator
Storage Node Poly
2nd Field Oxide
Refilling Poly
Si Substrate
Trench Cell Stacked-capacitor Cell
Capacitor dielectric layerCell plateWord line
Insulating Layer
IsolationTransfer gate
Storage electrode
CSE/EE 462 L12 ROM and PLA First Look.20 Brockman, ND, 2006
MRAM
CSE/EE 462 L12 ROM and PLA First Look.21 Brockman, ND, 2006
The Radical Fringe: Carbon Nanotubes
Scientific American,Feb. 2005
CSE/EE 462 L12 ROM and PLA First Look.22 Brockman, ND, 2006
The Radical Fringe: Carbon Nanotubes
Developed by Nantera, being commercialized by LSI Logic