cs/ee 3700 : fundamentals of digital system design
DESCRIPTION
CS/EE 3700 : Fundamentals of Digital System Design. Chris J. Myers Lecture 11: Testing of Logic Circuits Chapter 11. Testing of Logic Circuits. Must test a circuit to check that it meets required functional and timing specification. Manufacturing process can introduce flaws. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/1.jpg)
CS/EE 3700 : Fundamentals of Digital System Design
Chris J. Myers
Lecture 11: Testing of Logic Circuits
Chapter 11
![Page 2: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/2.jpg)
Testing of Logic Circuits
• Must test a circuit to check that it meets required functional and timing specification.
• Manufacturing process can introduce flaws.• Testing applies a set of inputs, called tests,
and compare with expected outputs.• Challenge is to derive a small set of tests.• Exhaustive approach is impractical.
![Page 3: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/3.jpg)
Faults
• Many things can go wrong:– Transistor may be stuck open or closed.– Wire can be shorted to Vdd or Gnd.– Wire may simply be broken.– Two wires may get shorted together.– Logic gate may produce the wrong output.
![Page 4: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/4.jpg)
Stuck-At Model
• Stuck-at model assumes a fault manifests as some wire stuck at a logic value of 0 or 1.
• If w is stuck-at-0, it is denoted w/0.
• If w is stuck-at-1, it is denoted w/1.
• While this model does not work for all types of faults, works reasonably well.
![Page 5: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/5.jpg)
Single and Multiple Faults
• Dealing with multiple faults is difficult.
• Considering single faults only still detects majority of multiple faults.
• Fault detected when output value of faulty circuit differs from good circuit for a test.
• Complete set of test is called a test set.
![Page 6: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/6.jpg)
CMOS Circuits
• Transistors may be permanently open or shorted (closed).
• May or may not appear as a stuck-at fault.• May also cause permanent path between
Vdd and Gnd giving intermediate voltage.• May also lead to combinational circuit to
behave like a sequential one.• Will restrict ourselves to stuck-at model.
![Page 7: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/7.jpg)
Complexity of a Test Set
• Sequential circuits substantially more complex to test than combinational ones.
• In combinational case, we can apply all possible input valuations and check outputs.
• This approach is impractical and unnecessary for large circuits.
![Page 8: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/8.jpg)
Figure 11.1 Fault detection in a simple circuit
(a) Circuit
Test Fault detected
w 1 w 2 w 3 a/0 a/1 b/0 b/1 c/0 c/1 d/0 d/1 f /0 f /1
000
001
010
011
100
101
110
111
(b) Faults detected by the various input valuations
f
a
b
c d
w 1
w 2
w 3
![Page 9: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/9.jpg)
Figure 11.2 A sensitized path
f
a b
c
w 1
w 2 1 =
w 3 0 =
w 4 1 =
![Page 10: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/10.jpg)
Figure 11.3 Circuit for Example 11.1
fb
c
d
w1
w2
w3
w4
![Page 11: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/11.jpg)
Fig
ure
11.4
Det
ecti
on o
f fa
ults
b c
g
kh
f
w1
w2
w3
w4
(a)
Circ
uit
f
w1
w2
w3
w4
(b)
Det
ectio
n o
f
f
w1
w2
w3
w4
b0
faul
t
(c)
Det
ectio
n of
g1
faul
t
![Page 12: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/12.jpg)
Figure 11.5 Circuit with a tree structure
f
w 1
w 3
w 4
w 2
w 3
w 4
w 1
w 2
w 3
![Page 13: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/13.jpg)
Figure 11.6 Derivation of tests for the circuit in Figure 11.5
Product term TestNo. w 1 w 3 w 4 w 2 w 3 w 4 w 1 w 2 w 3 w 1 w 2 w 3 w 4
1 1 1 1 0 1 0 0 0 0 1 0 0 0 Stuck-at-0 2 0 1 0 1 1 1 1 1 0 0 1 0 1
tests 3 0 0 0 1 0 1 1 1 1 0 1 1 1
4 0 1 1 1 1 0 1 1 0 0 1 0 0
5 1 0 1 1 0 0 0 1 1 1 1 1 0 Stuck-at-1 6 1 1 0 0 1 1 0 0 0 1 0 0 1
tests 7 1 0 0 1 0 1 0 1 1 1 1 1 1
8 0 0 0 0 0 1 1 0 1 0 0 1 1
![Page 14: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/14.jpg)
Figure 11.7 All two-variable functions
w 1 w 2 f 0 f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f 10 f 11 f 12 f 13 f 14 f 15
00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
01 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
![Page 15: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/15.jpg)
Figure 11.8 The XOR circuit
w 1
w 2
d b
c
h
k
f
![Page 16: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/16.jpg)
Figure 11.9 The effect of various faults
Fault Circuit implements
b/0 f 5 = w 2
b/1 f 10 = w 2
c/0 f 3 = w 1
c/1 f 12 = w 1
d/0 f 0 = 0
d/1 f 7 = w 1 + w 2
h/0 f 15 = 1
h/1 f 4 = w 1 w 2
k/0 f 15 = 1
k/1 f 2 = w 1 w 2
![Page 17: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/17.jpg)
Figure 11.10 Effectiveness of random testing
Percentfaults
detected
Number of tests
![Page 18: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/18.jpg)
Testing Sequential Circuits
• Response of sequential circuit is dependent on both current input and present state.
• Could check all state transitions.
• Cannot determine state, not observable.
• Circuits must be designed to be testable.
![Page 19: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/19.jpg)
Fig
ure
11.1
1 S
can-
path
arr
ange
men
t
0
1
0
1
0
1
Com
bin
ati
onal
circ
uit
z 1
z k
w 1
w n
y 3 y 2 y 1
Y 3
Y 2
Y 1
Clo
ck
Sca
n-i
n
Norm
al
Sca
n
Sca
n-o
ut
D
Q
D
Q
D
Q
![Page 20: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/20.jpg)
Fig
ure
11.1
2 C
ircu
it f
or E
xam
ple
11.3
0 1 0 1
w
y 1y 2
z
Y1
Y2
Rese
tn
Sca
n-o
ut
Norm
al/Sca
n
Sca
n-i
n
Clo
ck
DQ Q
DQ Q
![Page 21: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/21.jpg)
Figure 11.13 The testing arrangement
x 0
Testvector
generator
Circuit under test
Testresult
compressor
Signature
x n 1 –
p 0
p m 1 –
![Page 22: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/22.jpg)
Figure 11.14 Pseudorandom binary sequence generator (PSRG)
x 3 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 ···
x 2 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ···
x 1 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 ···
x 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 ···
f 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 ···
(b) Generated sequence
(a) Circuit
x 3 x 2 x 1 x 0
Clock
f
PRBS
D Q
Q
D Q
Q
D Q
Q
D Q
Q
![Page 23: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/23.jpg)
Figure 11.15 Single-input compressor circuit
p
Clock
Signature
D Q
Q
D Q
Q
D Q
Q
D Q
Q
![Page 24: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/24.jpg)
Figure 11.16 Multiple-input compressor circuit (MIC)
Clock
Signature
p 3 p 2 p 1 p 0
D Q
Q
D Q
Q
D Q
Q
D Q
Q
![Page 25: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/25.jpg)
Figure 11.17 BIST in a sequential circuit
Combinational circuit
W
Flip-flopsand
multiplexers
SIC
MIC
X
0
1
Normal Test
y Y
Z-signature
Y-signature
Scan-out
Scan-in
Z
PRBSG-X
PRBSG-y
![Page 26: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/26.jpg)
Figure 11.18 A four-bit built-in logic block observer (BILBO)
D Q
Q
D Q
Q
D Q
Q
D Q
Q 0 1
M 2
M 1
S i n
G S
Clock
p 2 p 3 p 0 p 1
q 2 q 3 q 0 q 1
S o u t
![Page 27: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/27.jpg)
Figure 11.19 Using BILBO circuits for testing
Combinational network
Scan-out
Scan-in
CN1
Combinational network
CN2 BIL
BO
1
BIL
BO
2
![Page 28: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/28.jpg)
Boundary Scan
• Chips soldered into printed circuit boards do not allow easy access it inputs/outputs.
• Pins can be configured into a shift register to allow inputs and outputs to be scanned in.
• Now IEEE Standard 1149.1.
![Page 29: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/29.jpg)
Printed Circuit Boards
• Need CAD software to design them.
• Crosstalk – capacitively coupled wires.– Avoid long parallel wires.
• Power supply noise – power supply spikes.– Use bypass capacitors between Vdd and Gnd.
• Transmission-line effects – Use termination component on the line.
![Page 30: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/30.jpg)
Testing of PCBs
• Power Up – check for hot chips and correct power and ground voltages.
• Reset – put circuit into known start state.
• Low-level functional testing – use divide-and-conquer approach.
![Page 31: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/31.jpg)
Testing of PCBs
• Full functional testing – test system.– Manufacturing errors.– Incorrect specifications.– Misinterpretation of the data sheets.– Wrong data sheets.
• Timing – start with slow clock and gradually increase to desired frequency.
• Reliability – affected by timing, noise, crosstalk issues, and environment.
![Page 32: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/32.jpg)
Instrumentation
• Oscilloscope – displays voltage waveforms to show problems with delay and noise.
• Logic analyzer – allows examination of large groups of signals.
![Page 33: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/33.jpg)
Where to go from here . . .
• CS/EE 3710 – Computer Design Laboratory• CS/EE 3720 – Analog and Digital Interfacing• CS/EE 3810 – Computer Architecture• CS/EE 4710 – Senior Project• CS/EE 5710 – Digital IC Design• CS/EE 5720 – Analog IC Design• CS/EE 5740 – CAD for Digital Circuits• CS/EE 5750 – Asynchronous Circuit Design• CS/EE 5810 – Advanced Computer Architecture• CS/EE 5830 – VLSI Architecture
![Page 34: CS/EE 3700 : Fundamentals of Digital System Design](https://reader035.vdocuments.us/reader035/viewer/2022062309/56814457550346895db0f3af/html5/thumbnails/34.jpg)
New to the CE Program
• Tracks are no longer required.– Still must take 15 credits of CS/EE classes.
• New senior thesis option:– Must take EE 3900 Junior seminar in Fall
and prethesis in Spring (0.5 credits each).
– Senior year must take one year of senior thesis for a total of 4 credits.
– Do not need to take CS/EE 4710.
– Can lead into a joint BS/EE degree.