cse 260 exam

8/10/2019 CSE 260 exam

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1. (15 points). Draw a diagram for a circuit that implements the VHDL module shown below.Your diagram may include gates, muxes and one or more 8 bit subtractors (that is, a circuit

with two 8-bit inputs x and y and an 8 bit output equal to the difference x! y). Assume thatthe type of word is an 8 bit std_logic_vector.

entity foo is port(A, B: in word; U, V: out word); end foo;architecture bar of foo isfunction negate(en: std_logic; x: word) return word is begin

if en = '0' then return x;else return (x'range => '0') - x;end if;

end function negate;function absVal(x: word) return word is begin

return negate(x(x'high),x);end function absVal;function absDiff(x, y: word) return word is begin

return absVal(x-y);end function absDiff;begin

U <= absVal(A); V <= absDiff(absVal(A),B);

end bar;

CSE 260 – Digital Computers: Organization and Logical Design

Exam 2 Jon Turner 3/28/2012

8/10/2019 CSE 260 exam


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2. (10 points) An abbreviated testbench for the priority queue circuit that we discussed in classis shown below. Recall, the circuit can store eight (key,value) pairs. The testbench applies asequence of test inputs to the circuit and checks the circuit output using assertions. Fill inthe blanks in the test data.

architecture a1 of testPriQueue

type testVector is recordkey,val: std_logic_vector(3 downto 0); insert,delete: std_logic;smallVal: std_logic_vector(3 downto 0); empty, full: std_logic;

end record inVec;type testData is array(natural range <>) of testVector;constant td: testData := (-- key val insert delete smallVal empty full

(x"4", x"f", ‘1’, ‘0’, x”f”, ‘0’, ‘0’),

(x"3", x"e", ‘1’, ‘0’, x”e”, ‘0’, ‘0’),

(x"5", x"d", ‘1’, ‘0’, , , ), -- fill blanks

(x"6", x"c", ‘1’, ‘0’, , , ), -- fill blanks

(x"2", x"b", ‘1’, ‘0’, , , ), -- fill blanks

(x"1", x"a", ‘1’, ‘0’, , , ), -- fill blanks

(x"7", x"d", ‘1’, ‘0’, , , ), -- fill blanks

(x"8", x"9", ‘1’, ‘0’, , , ), -- fill blanks

(x"0", x"0", ‘0’, ‘1’, , , )); -- fill blanks...

beginpriq: priQueue port map(clk, reset, insert, delete, key, value,

smallVal, busy, empty, full);process begin wait for pause;reset <= '1'; wait for clkPeriod;reset <= ‘0’; wait for clkPeriod;for i in td'low to td'high loop

key <= td(i).key; value <= td(i).value;insert <= td(i).insert; delete <= td(i).delete; wait for clkPeriod;assert (busy = ‘1’) report ... wait for clkPeriod;assert (smallVal = td(i).smallVal and empty = td(i).empty

and full = td(i).full and busy = ‘0’) report ...end loop;

end process;end a1;

8/10/2019 CSE 260 exam


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3. (20 points) Complete the block diagram on the next page so that it implements the VHDLspecification shown below. You may add gates or multiplexors to the diagram. The body ofthe architecture is reproduced on the next page for your convenience.

entity tripleUpCount is portclk, reset: std_logic;

A: std_logic_vector(7 downto 0);event: out std_logic;eventCount: out std_logic_vector(7 downto 0)

end tripleUpCount;architecture a1 of tripleUpCount begintype stateType is (s0, s1, s2); signal state: stateType;signal ev: std_logic;signal prevA, count: std_logic_vector(7 downto 0);begin

process(clk) beginif rising_edge(clk) then

prevA <= A;if reset = ‘1’ then

state <= s0; count <= (others => ‘0’);else

case state is when s0 => if A > prevA then state <= s1; end if; when s1 => if A < prevA then state <= s0;

elsif A > prevA then state <= s2;end if;

when s2 => if A > prevA then count <= count + 1;elsif A < prevA then state <= s0;end if;

when others =>end case;

end if;end if;

end process;event <= ‘1’ when state = s2 and A > prevA else ‘0’;eventCount <= count;

end a1;

8/10/2019 CSE 260 exam


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beginprocess(clk) begin

if rising_edge(clk) thenprevA <= A;if reset = ‘1’ then

state <= s0; count <= (others => ‘0’);else

case state is when s0 => if A > prevA then state <= s1; end if; when s1 => if A < prevA then state <= s0;

elsif A > prevA then state <= s2;end if;

when s2 => if A > prevA then count <= count + 1;elsif A < prevA then state <= s0;

end if; when others =>end case;

end if;end if;

end process;event <= ‘1’ when state = s2 and A > prevA else ‘0’;eventCount <= count;

end a1;

reset

clk

A

D

>C

8 bit reg(count)

increment

A+1 A

compare

X

Y

>

<

D

>C

8 bit reg

(state)

event

eventCo

D

>C

8 bit reg(prevA)

0

1

0

1

0

1

1

0

compare

=s2

=s1

=s0

s00

1

8/10/2019 CSE 260 exam


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8/10/2019 CSE 260 exam


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4. (20 points) A partial implementation of the binary input module that we’ve been using inour labs is shown below. Fill in the missing parts of the implementation. Your VHDL shouldbe complete and syntactically correct. You may continue on the next page. Make note of theprovided comments. Be sure to specify all the output signals of binaryInMod.

entity binaryInMod is port(

-- inputs from S3 boardclk: in std_logic;btn: in buttons;knob: in knobSigs;-- signals provided to internal circuitresetOut: out std_logic;dBtn: out std_logic_vector(3 downto 1); -- debounced buttons 1-3pulse: out std_logic_vector(3 downto 1);-- pulse version of 1-3inBits: out word); -- value controlled by knob

end binaryInMod;

architecture a1 of binaryInMod is

component debouncergeneric (width: integer := 8);port(

clk: in std_logic;dIn: in std_logic_vector(width-1 downto 0);dOut: out std_logic_vector(width-1 downto 0)

);end component;

component knobIntf port( -- interface to knobclk, reset: in std_logic;knob: in knobSigs; -- input signals from knobtick: out std_logic; -- goes high each time knob turns

clockwise: out std_logic; -- high if knob is turning clockwisedelta: out word); -- equal to 1, 16, 16^2 or 16^3

-- each press on knob changes valueend component;

signal dbb: buttons;signal reset: std_logic;signal tick, clockwise: std_logic;signal bits, delta: word;

signal prevDbb: buttons;

signal knobBits: word;

8/10/2019 CSE 260 exam


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begindb: debouncer generic map(width => 4) port map(clk, btn, dbb);ki: knobIntf port map(clk, reset, knob, tick, clockwise, delta);

reset <=

resetOut <=

dBtn <=

process (clk) beginif rising_edge(clk) then

end a1;

8/10/2019 CSE 260 exam


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5. (12 points). Convert the expression shown below to sum-of-products form, then use the K-map to get the simplest sum-of-products expression you can find.

AB’C ’ + ( A + B’(C + D’))’ + BC ’

Use the K-map below to simplify the specified expression (the first summation lists theminterms, the second lists the don’t cares).

!m(1,2,4,5,8,13) !d(0,6,9,10,12,15)

AB

00 01

CD

11 10

00

01

11

10

AB

00 01

CD 11 10

00

01

11

10

8/10/2019 CSE 260 exam


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6. (8 points) Consider the circuit shown below. What is the minimum delay through thiscircuit, assuming that every gate has a delay of 1 ns?

What is the maximum delay?

Suppose every gate has a delay that can vary between 1 and 3 ns. What is the minimumdelay in this case?

What is the maximum delay?

A

B

C

Y

X

8/10/2019 CSE 260 exam


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7. (12 points) The diagram shows a generic state machine labeled with various timingparameters (for example, the minimum delay from an input to a flip flop input is 2 ns andthe maximum delay from a flip flop output to a flip flop input is 5 ns.

Is this circuit subject to hold time violations? Justify your answer.

What is the smallest safe clock period for this circuit?

If the clock goes from low to high at time t0, during what time interval must the inputsignals be stable?

If the clock goes from low to high at time t0, during what time interval is it possible for theoutputs to be changing?

current state

D

>C

clk

nextstate synchronous

outputs

inputs 2-7 ns

3-5 ns1-4 ns

flip flop prop delay: 2-5 nssetup time: 1 nshold time: 0.5 ns

clock skew: 1 ns

next statelogic

synchronousoutput logic

cse 260 exam

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