CSE 140L Lecture 4Flip-Flops, Shifters and Counters

Professor CK Cheng

CSE Dept.

UC San Diego

1) F-F2) Shift register3) Counter (Asynchronous)4) Counter (Synchronous)

Flip-Flops

DFF

D

CE

C

CLR

Q

CLR CE D C Q 1 X X X 0 0 0 X X No change 0 1 1 1 0 1 0 0

Asynchronous Clear

Inputs Output

Clock Enable

CLK = 0 CLK = 1

D Q

CLK

CLK

t

t

t

tsetup thold

D

Q

tcq

D-FF Timing

Input Timing Constraints• Setup time: tsetup = time before the clock edge that

data must be stable (i.e. not changing)

• Hold time: thold = time after the clock edge that data must be stable

• Aperture time: ta = time around clock edge that data must be stable (ta = tsetup + thold)

CLK

tsetup

D

thold

ta

Output Timing Constraints• Propagation delay: tpcq = time after clock edge that

the output Q is guaranteed to be stable (i.e., to stop changing)

• Contamination delay: tccq = time after clock edge that Q might be unstable (i.e., start changing)

CLK

tccqtpcq

Q

Setup Time Constraint• The setup time constraint: The maximum delay from

register R1 through the combinational logic.

• The input to register R2 must be stable at least tsetup before the clock edge.

CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2

Tc ≥ tpcq + tpd + tsetup

tpd ≤ Tc – (tpcq + tsetup)

Hold Time Constraint• The hold time constraint depends on the minimum delay

from register R1 through the combinational logic.

• The input to register R2 must be stable for at least thold after the clock edge.

thold < tccq + tcdtcd > thold - tccq

CLK

Q1

D2

tccq tcd

thold

CL

CLKCLK

Q1 D2

R1 R2

2) A 3 Bit Shift Register

DQ

CLK

DQ

DQ

0 0 X X X 1 1 0 X X 2 0 1 0 X3 1 0 1 0

4 1 1 0 15 0 1 1 0

6 0 0 1 1 7 1 0 0 1

Time Steps A B C D

AB C D

Signal A is given as input.

3) A 3 Bit Counter (Asynchronous)

TQ

CLK

TQ

TQ

CLK

tA

C

Bt

t

1 0 1 0

1 1 0 0

B C

t1 1 1 1

7 6 5 4

A

1 1 1

Reset A(0) = B(0) = C(0) = 0

0 0 0 0 0

1 1 1 1 7

2 1 1 0 63 1 0 1 5

4 1 0 0 45 0 1 1 3

6 0 1 0 2

7 0 0 1 1

Time C B A