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FINALTERM EXAMINATION

FALL 2006

CS501 - ADVANCE COMPUTER ARCHITECTURE

Marks: 75

Time: 120min

StudentID/LoginID: ______________________________

Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date:

Please read the following instructions carefully before attempting any of the questions:

1. Students are allowed to use calculators in this exam.

2. Attempt all questions. Marks are written adjacent to each question.

3. Do not ask any questions about the contents of this examination from anyone.

a. If you think that there is something wrong with any of the questions, attempt it to the best of your understanding.

b. If you believe that some essential piece of information is missing, make an appropriate assumption and use it to solve the problem.

c. Write all steps, missing steps may lead to deduction of marks.

4. Exam is Closed Book. No handouts or extra material is allowed in exam hall other than rough sheet which will be provided by the examiner.

**WARNING: Please note that Virtual University takes serious note of unfair means. Anyone found involved in cheating will get an `F` grade in this course.

For Teacher's use only Question 1 2 3 4 5 6 7 8 9 10 Total

Marks Question 11 12 13 14 15 16

Marks Question

Marks

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Question No: 1 ( Marks: 1 ) - Please choose one The _____________ RTN describes the overall effect of instructions on the programmer visible registers. ►

Abstract

►

Concrete

►

Absolute

►

Basic

Question No: 2 ( Marks: 1 ) - Please choose one The instruction set is of _____________ importance in governing the structure and function of the pipeline. ►

Least

►

Primary

►

Secondary

►

No

Question No: 3 ( Marks: 1 ) - Please choose one ____________ is the most general and least useful performance metrics for RISC machines. ►

MIPS

►

Instruction Count

►

Number of registers

►

Clock Speed

Question No: 4 ( Marks: 1 ) - Please choose one A __________ provides four functions: Select, DataIn, DataOut and Read/Write. ►

ALU

►

Bus

►

Register

►

Memory Cell

Question No: 5 ( Marks: 1 ) - Please choose one

We can classify or partition the SRC instructions by their overall ______________ behavior. ►

Register transfer

►

Memory transfer

►

Execution

►

Logical

Question No: 6 ( Marks: 1 ) - Please choose one The ____________ RTN describes detailed register transfer steps in the data path that produce the overall effect. ►

Abstract

►

Concrete

►

Absolute

►

Basic

Question No: 7 ( Marks: 1 ) - Please choose one All members of the MC68000 family are ____________ processors. ►

32-bit

►

16-bit

►

64-bit

►

8-bit

Question No: 8 ( Marks: 1 ) - Please choose one _________________ operations refers to a processor that can issue more than one instruction simultaneously. ►

Macro

►

Micro

►

Scalar

►

Superscalar

Question No: 9 ( Marks: 1 ) - Please choose one Exception which are _______________ occur in response to events that are paced by the internal

processor clock. ►

Asynchronous

►

Synchronous

►

Internal

►

External

Question No: 10 ( Marks: 1 ) - Please choose one In the hazard detection by hardware, resolved by pipeline stalls, if the instructions are in the adjoining stages, then the hazard must be detected in stage __________. ►

4

►

2

►

3

►

1

Question No: 11 ( Marks: 15 ) a) What are the approaches used to design a Control unit? Briefly compare them. [5] b) Evaluate the instruction z = 16(a -b) + 32(c+58) with the 3 address machine.[5] c) What is the difference between “branch” and “branch link” instructions of SRC? [5] Question No: 12 ( Marks: 10 ) A hard disk with 5 platters has 1024 tracks per platter, 512 sectors per track and 512 bytes/sector. a) What is the total capacity of the disk? [8] b) How many platters are required for a 80GB disk if there are 1024 bytes/sector, 2048 sectors per track and 4096 tracks per platter. [2] Question No: 13 ( Marks: 10 ) Consider a memory system having the following specifications. Find its total cost and cost per byte of memory. [10]

Memory type Total bytes Cost per byte

SRAM 512 KB 50$ per MB

DRAM 256 MB 2$ per MB

Disk 3 GB 10$ per GB

Question No: 14 ( Marks: 10 ) Give comparison of advantages and disadvantages of serial and parallel transfer of data between the CPU and an I/O device. [10] Question No: 15 ( Marks: 10 ) What are different I/O techniques? Briefly describe the comparison of Interrupt driven I/O and Polling. [3+7] Question No: 16 ( Marks: 10 ) Assume a network with a bandwidth of 2500Mbits/sec. It has a sending overhead of 200μsec and a receiving overhead of 160μsec. Assume two machines connected together. It is required to send a 15,000 byte message from one machine to the other (including header), and the message format allows 15, 00 bytes in a single message. Calculate the total latency to send the message from one machine to another assuming they are 25m apart (as in a SAN). Next, perform the same calculation but assume the machines are 750m apart (as in a LAN).Finally, assume they are 1500Km apart (as in a WAN). Assume that signals propagate at 1/3 of the speed of light in a conductor, and that the speed of light is 300,000Km/sec.

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CS501 Advanced Computer Architecture Final Term Examination - August 2004

Time Allowed: 150 Minutes


1. Attempt all questions. Marks are written with each question. 2. Do not ask any questions about the contents of this examination from anyone.

a. If you think that there is something wrong with any of the questions, attempt it to the best of your understanding. b. If you believe that some essential piece of information is missing, make an appropriate assumption and use it to solve the problem. c. Write all steps, missing steps may lead to deduction of marks.

Total Marks: 100 Total Questions: 9 Question No. 1 Marks : 15

Consider a hard disk that rotates at 6000 rpm. The seek time to move the head between adjacent tracks is 1 ms. There are 64 sectors per track stored in linear order. Assume that the read/write head is initially at the start of sector 1 on track 7. (a) How long will it take to transfer sector 1 on track 7 to sector 1 on track 9? (b) How long will it take to transfer all the sectors on track 12 to corresponding sectors on track 13?

Question No. 2 Marks : 10

Briefly describe five important features of RISC machines.


What will be the logic levels on the external FALCON-A buses when each of the given FALCON-A instruction is executing on the processor? Complete the table given. All numbers are in the hexadecimal number system, unless noted otherwise. Assume that all memory content is properly aligned, i.e. memory addresses start at address divisible by 2. This table contains a partial memory map showing the addresses and the corresponding data values.

The next table shows the register map showing the contents of all the CPU registers. Another important thing to note is that memory storage is big-endian.


(a) Drawing a timing diagram, briefly explain the sequence of steps that take place during a synchronous transfer between a master device and a slave device. (b) List one advantage and one disadvantage of DMA ?


Given a 16-bit parallel output port attached with the FALCON-A CPU as shown in the figure below. The port is mapped onto address DEh of the FALCON-A's I/O space. Sixteen LED branches are used to display the data being received from the FALCON-A's data bus. Every LED branch is wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED on; a 0 turns it off. (a) Which LEDs will be ON when the instruction out r7, 222 executes on the CPU? Assume r7 contains ABCDh. Briefly explain your answer.

(b) Identify the changes needed to map the above output port at address A0h and A1h of the FALCON-A's I/O space (instead of DEh and DFh )


Consider a DRAM with 2048 rows and a refresh time of 20ms. (a) Find the frequency of row refresh operations. (b) What fraction of the DRAM's time is spent on refreshing if each refresh takes 100ns.


of 2 Assume a network with a bandwidth of 1500Mbits/sec. It has a sending overhead of 80µsec and a receiving overhead of 100µsec. Assume two machines connected together. It is required to send a 15,000 byte message from one machine to the other (including header), and the message format allows 15, 00 bytes in a single message. Calculate the total latency to send the message from one machine to another assuming they are 20m apart (as in a SAN). Next, perform the same calculation but assume the machines are 700m apart (as in a LAN). Finally, assume they are 1000Km apart (as in a WAN). Assume that signals propagate at 66% of the speed of light in a conductor, and that the speed of light is 300,000Km/sec.

Given a 16-bit parallel output port attached with the FALCON-A CPU as shown in the figure below. The port is mapped onto address DEh of the FALCON-A's I/O space.


Total Marks: 100 Total Questions: 07










Final Term Examination – Spring 2005

CS501 Advance Computer Architecture

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Question No. 5 Marks : 15 Define an I/O port. Which functions are performed by it? Question No. 4 Marks : 15

A= B + C x D

Write the code to implement the following expressions on 3, 2, 1, and 0 address machines.


Find the bandwidth of a memory system that has a latency of 30ns, a pre charge time of 10ns and transfers 3 bytes of data per access.


(b) Identify the changes needed to map the above output port at address D0h and D1h of the FALCON-A's I/O space (instead of DEh and DFh )

Executes on the CPU? Assume r1 contains A2C9h. Briefly explain your answer. out r1, 123 (a) Which LEDs will be ON when the instruction

Sixteen LED branches are used to display the data being received from the FALCON-A's data bus. Every LED branch is wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED on; a 0 turns it off.

A magnetic disk has an average seek time of 8 ms. The transfer rate is 50 MB/sec. The disk rotates at 10,000 rpm and the controller overhead is 0.3 msec. Find the average time to read or write 1024 bytes.


+0.875

Convert the following decimal numbers to IEEE single precision floating- point numbers. Report the results as hexadecimal values. You need not extend the calculations of the significant value beyond its most significant 8 bit.


Write a note on complications related to pipelining.

Give control signals for the add instructions.


Assume that three I/O devices are connected to a 32-bit, 10 MIPS CPU. The first device is a hard drive with a maximum transfer rate of 2MB/sec. It has a 32-bit bus. The second device is a floppy drive with a transfer rate of 30KB/sec over a 16-bit bus, and the third device is a keyboard that must be polled thirty five times per second. Assuming that the polling operation requires 15 instructions for each I/O device, determine the percentage of CPU time required to poll each device.


Total Marks: 100 Total Questions: 7







1. Attempt all questions. Marks are written with each question.



Final Term Examination - February 2005

CS501 Advanced Computer Architecture

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Executes on the CPU? Assume r1 contains AA79h. Briefly explain your answer.

(a) Which LEDs will be ON when the instruction out r1, 101

Given a 16-bit parallel output port attached with the FALCON-A CPU as shown in the figure below. The port is mapped onto address 65h of the FALCON-A's I/O space. Sixteen LED branches are used to display the data being received from the FALCON-A's data bus. Every LED branch is wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED on; a 0 turns it off.


Suppose we have 10 magnetic tapes, each containing 20GB. Assume that there are enough tape readers to keep any network busy. How long will it take to transmit the data over a distance of 3Km? The choices are category 5 twisted-pair wires at 100Mbits/sec, multimode fiber at 1500Mbits/sec and single-mode fiber at 3000Mbits/sec.


Write different schemes related to virtual memory organization.


Note: Fill the given table only. If you require other control signals to complete the table, do it as rough work. Marks will be given only for the required fields in the table.

Convert the following decimal numbers to IEEE single precision floating- point numbers. Report the results as hexadecimal values. You need not extend the calculations of the significant value beyond its most significant 8 bit. -0.5625


Explain all categories in classification of hazards.


(b) Identify the changes needed to map the above output port at address C0h and C1h of the FALCON-A's I/O space (instead of 65h and 66h)

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MID-TERM EXAMINATION SEMESTER FALL 2004

CS501-Advance Computer Architecture (S4)

Total Marks:50 Duration:60mins

StudentID/LoginID

Name

PVC Name/Code

Date

Maximum Time Allowed: (1 Hour)


1. Attempt all questions. Marks are written adjacent to each question. 2. Do not ask any questions about the contents of this examination from anyone.

a. If you think that there is something wrong with any of the questions, attempt it to the best of your understanding. b. If you believe that some essential piece of information is missing, make an

appropriate assumption and use it to solve the problem. c. Write all steps, missing steps may lead to deduction of marks.



For Teacher’s use only Question Q1 Q2 Q3 Q4 Q5 Total Marks

Question No: 1 Marks: 10

Consider a machine having a 200 MHz clock and three instruction types with following parameters. Now suppose that two different compilers generate code for the same program. The instruction count for each is given as follows:

Code Sequence from compiler 1

Code Sequence from compiler 2

Instruction

Type Instruction Count (millions of instructions)

Control Instructions 9 7 ALU Instructions 11 6

Data Transfer Instructions 5 8 Calculate the Execution Time and MIPS for the two code sequences. The following information is given:

Instruction Type CPI Control 2

ALU 3 Data Transfer 4


The following figure gives a partial “Alphabetical Listing of the SRC instruction set” along with the corresponding 5-bit op-codes.

(a) Hand assemble the following SRC assembly language instruction showing all work

and r5, r2, r13

(b) Reverse assemble the following SRC machine language instruction showing all work. The given number is a hexadecimal number.

A844002Ch Question No: 3 Marks: 10

The following table shows a partial summary of the ISA for the FALCON-A. Write an assembly language program using the FALCON-A assembly language to evaluate the expression: z = 9*x + y Note: x, y and z are names of memory locations. Your program should not change the source operands. Do not worry about the contents of x and y. There is no need to worry about assembler directives. Comments in your code may be helpful.

mnemonic opcode

5bits

operand1

3 bits

operand2

3 bits

Operand3

3 bits

const 1

5 bits

const 2

8 bits add 00000 ra rb rc - - addi 00001 ra rb - C1 - sub 00010 ra rb rc - - subi 00011 ra rb - C1 - mul 00100 ra rb rc - - div 00101 ra rb rc - - mov 00110 ra rb - - - movi 00111 ra - - - C2 and 01000 ra rb rc - - andi 01001 ra rb - C1 or 01010 ra rb rc - - ori 01011 ra rb - C1 -

shiftl 01100 ra rb - C1 - shiftr 01101 ra rb - C1 - not 01110 ra rb - - - asr 01111 ra rb - C1 - jpl 10000 ra - - - C2 jmi 10001 ra - - - C2 jnz 10010 ra - - - C2 jz 10011 ra - - - C2

jump 10100 ra - - - C2 call 10110 ra rb - - - ret 10111 ra - - - - in 11000 ra - - - C2 out 11001 ra - - - C2

store 11100 ra rb - C1 - load 11101 ra rb - C1 - halt 11111 - - - - -


The following diagram shows the uni-bus implementation of the FALCON-A CPU. Write the structural RTL description for the ‘or’ instruction including the instruction fetch phase. Assume that a timing generator with up to eight timing intervals is available.


Write short answers to the following questions:

(a) What are features of superscalar architecture? (b) What is the difference between VLIW and superscalar architecture? (c) What is a micro-instruction? (d) What is a micro-program? (e) Explain the operation of branch prediction unit.

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Largest Online Community of VU Students MIDTERM EXAMINATION

FALL 2006

CS501 - ADVANCE COMPUTER ARCHITECTURE

Marks: 45

Time: 60min


Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date:



2. Do not ask any question about the contents of this examination from any one.

a. If you think that there is something wrong with any of the questions, attempt it

to the best of your understanding.

b. If you believe that some essential piece of information is missing, make an

appropriate assumption and use it to solve the problem.



For Teacher's use only Question 1 2 3 4 5 6 7 8 Total

Marks Question No: 1 ( Marks: 1 ) - Please choose one

http://www.vupages.com/

http://forum.vupages.com/

The code size of 2-address instruction is ________________. ►

5 bytes

►

7 bytes

►

3 bytes

►

2 bytes

Question No: 2 ( Marks: 1 ) - Please choose one The data movement instructions ___________ data within the machine and to or from input/output devices. ►

Store

►

Load

►

Move

►

None of Above

Question No: 3 ( Marks: 1 ) - Please choose one Register-register instructions use ____________ memory operands out of a total of 3 operands ►

1

►

3

►

0

►

2

Question No: 4 ( Marks: 1 ) - Please choose one _____________all memory systems are dumb, in that they respond to only two commands: read or write. ►

Virtually

►

Logically

►

Physically

► None of Above

Question No: 5 ( Marks: 1 ) - Please choose one Flip-flop is a ____________device, capable of storing one bit of Information ►

Bi-stable

►

Unit-stable

►

Stable

►

Storage

Question No: 6 ( Marks: 10 ) The following table shows a partial summary of the ISA for the SRC. Write an assembly language program using the SRC assembly language to evaluate the expression: Z= (9 + 32a) - (16b + c) Note: a, b and c are names of memory locations. Your program should not change the source operands. Do not worry about the contents of a and b. There is no need to worry about assembler directives. Comments in your code may be helpful.

Question No: 7 ( Marks: 15 ) What is function of control signals in CPU, briefly describe the control signals required for fetch operation in SRC.

Question No: 8 ( Marks: 15 ) Describe the three categories of hazards.

CS501-Advance Computer Architecture Midterm Special 2006

www.vujannat.ning.com Q1 _____________all memory systems are dumb, in that they respond to only two commands: read or write Virtually Logically Physically None of These Q 2 Consider two programs having three types of instructions given as follows: [10] Number of Program 1 Program 2 Data transfer instructions 7 12 Control instructions 3 5 ALSU instructions 6 3

Instructions Type CPI Control 5 ALSU 3 Data Transfer 4

Compare both the programs for the following parameters:

1. Instruction count ( IC ) 2. Speed of execution ( ET )

Q 3 To access an operand in memory, the CPU must first generate an address, which it then issues to the __________ MEMORY REGISTER

DATA BUS ALL OF ABOVE Q 4 ___________ or Branch instructions affect the order in which instructions are performed, or control the flow of the program Control DATA MOVMENT Arithmetic LOGICAL Q5

Reverse assemble the following SRC machine language instructions: [10] 68C2003A h

Q6 An instruction that specifies one operand in memory and one operand in a register would be known as a __________ address instruction. 2-1/2 1-1/2 0 2 Q7 The data movement instructions ___________ data within the machine and to or from input/output devices Store LOAD MOVE NONE OF ABOVE. Q8 Write short answers to the following questions: [3 x 5]

a. What is the advantage of a linker in the development of assembly language programs?

Solution:- The linker:

When developing large programs, different people working at the same time can develop separate modules of functionality. These modules can then be ‘linked’ to form a single module that can be loaded and executed. The modularity of programs, that the linking step in assembly language makes possible, provides the same convenience as it does in higher-level languages; namely abstraction and separation of concerns. Once the functionality of a module has been verified for correctness, it can be re-used in any number of other modules. The programmer can focus on other parts of the program. This is the so-called “modular” approach, or the “top-down” approach.

b. Define term “Single stepping”. Solution:-

Single stepping: Single stepping and breakpoints that allow the examination of the status of

the program and registers at desired points during execution. c. Define term “Type checking”. Solution:-

Type Checking:- High-level languages provide various primitive data types, such as integer, Boolean and a string, that a programmer can use. Type checking provides for the verification of proper usage of these data types. It allows the compiler to determine memory requirements for variables and helping in the detection of bad programming practices.

On the other hand, there is generally no provision for type checking at the machine level, and hence, no provision for type checking in assembly language. The machine only sees strings of bits. Instructions interpret the strings as a type, and it is usually limited to signed or unsigned integers and floating point numbers. A given 32-bit word might be an instruction, an integer, a floating-point number, or 4 ASCII characters. It is the task of the compiler writer to determine how high-level language data types will be implemented using the data types available at the machine level, and how type checking will be implemented.

d. Define term “Instruction set”.

Solution:- Instruction Set A collection of all possible machine language commands that a computer can understand and execute is called its instruction set. Every processor has its own unique instruction set. Therefore, programs written for one processor will generally not run on another processor. This is quite unlike programs written in higher-level languages, which may be portable. Assembly/machine languages are generally unique to the processors on which they are run, because of the differences in computer architecture. Three ways to list instructions in an instruction set of a computer:

• by function categories • by an alphabetic ordering of mnemonics • by an ascending order of op-codes e. Why computer logic design is different from classical logic design?

Solution:- Classical logic design versus computer logic design:

The tr itional sequential circuit design techniques for a finite state machine are not very p ctical when it comes to the design of a computer, in spite of the fact that a compumuch

adra
ter is a finite state machine. The reason is that employing these techniques is too complex as the computer can assume hundreds of states.

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1

FINALTERM EXAMINATION SPRING 2006

CS501 - ADVANCE COMPUTER ARCHITECTURE (Session - 1 )

Marks: 80

Time: 120min


Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date: Friday, August 25, 2006



2. Do not ask any question about the contents of this examination from any one.

a. If you think that there is something wrong with any of the questions, attempt it

to the best of your understanding.

b. If you believe that some essential piece of information is missing, make an

appropriate assumption and use it to solve the problem.



For Teacher's use only Question 1 2 3 4 5 6 7 8 9 10 Total

Marks Question No: 1 ( Marks: 3 ) - Please choose one


2

16k x4 static RAM Chip is arranged in the form of four _____________ cells. ►

16x512

►

32x512

►

256x512

►

64x256

Question No: 2 ( Marks: 3 ) - Please choose one In a DRAM cell, the storage capacitor will discharge in around ______________ ►

4 -15 ms

►

2 - 10 ms

►

5-20 ms

►

10-25 ms

Question No: 3 ( Marks: 3 ) - Please choose one 1-bit sign, 8-bit exponent, 23-bit fraction and a bias of 127 is used for ___________ Binary Floating Point Representation ►

Double precision

►

Single Precision

►

All of above

►

Half Precision

Question No: 4 ( Marks: 3 ) - Please choose one The average rotational latency if the disk rotated at 20,000rpm is _____________ ►

0.5 ms

► 3.5 ms


3

►

2.5 ms

►

1.5 ms

Question No: 5 ( Marks: 3 ) - Please choose one A hard disk with 5 platters has 1024 tracks per platter, 512 sectors per track and 512 bytes/sector. What is the total capacity of the disk? ►

1.5 GB

►

1 GB

►

2 GB

►

3 GB

Question No: 6 ( Marks: 20 ) a) Consider two programs having three types of instructions given as follows: [15]

Number of Program 1 Program 2 Data transfer instructions 4 6 Control instructions 6 9 ALSU instructions 8 7

Instruction Type CPI Control 5 ALSU 4 Data Transfer 3

Compare both the programs for the following parameters:

1. Instruction count 2. Speed of execution

b) Give short answers: [5]

1. When exceptions must be disabled? 2. How machine check exceptions are generated?

Question No: 7 ( Marks: 10 )


4

Consider a memory system having the following specifications. Find its total cost and cost per byte of memory.

Memory type Total bytes Cost per byte

SRAM 768 KB 40$ per MB

DRAM 512 MB 4$ per MB

Disk 4 GB 5$ per GB

Question No: 8 ( Marks: 10 ) Assume that three I/O devices are connected to a 32-bit, 10 MIPS CPU. The first device is a hard drive with a maximum transfer rate of 1MB/sec. It has a 32-bit bus. The second device is a floppy drive with a transfer rate of 25KB/sec over a 16-bit bus, and the third device is a keyboard that must be polled thirty times per second. Assuming that the polling operation requires 20 instructions for each I/O device, determine the percentage of CPU time required to poll each device. Question No: 9 ( Marks: 10 ) Given a 16-bit parallel output port attached with the FALCON-A CPU as shown in the figure below. The port is mapped onto address DEh of the FALCON-A's I/O space. Sixteen LED branches are used to display the data being received from the FALCON-A's data bus. Every LED branch is wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED on, a 0 turns it off. (a) Which LEDs will be ON when the instruction [6] out r5, 201 executes on the CPU? Assume r5 contains BC69h. Briefly explain your answer.


5

(b) Identify the changes needed to map the above output port at address C0h and C1h of the FALCON-A's I/O space (instead of DEh and DFh ) [4] Question No: 10 ( Marks: 15 ) a. Briefly describe the following errors with respect to serial communication. [9] i- Frame error ii- Parity iii-Overrun b. List down the advantages of Virtual Memory [6]

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