cs3350b computer organization chapter 2: synchronous ...cs3350b computer organization chapter 2:...
TRANSCRIPT
CS3350B Computer OrganizationChapter 2: Synchronous Circuits
Prelude
Alex Brandt
Department of Computer ScienceUniversity of Western Ontario, Canada
Thursday January 24, 2019
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 1 / 12
Outline
1 Everything on a Computer is a Number
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 2 / 12
Radix RepresentationsRadix is the base number in some numbering system.In a radix ๐ representation digits (๐๐) are from the set {0, 1, . . . , ๐ โ 1}
๐ฅ = ๐๐โ1 ร ๐๐โ1 + ๐๐โ2 ร ๐๐โ2 + โ โ โ + ๐1 ร ๐1 + ๐0 ร ๐0
๐ = 10 รโ decimal, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}๐ = 2 รโ binary, {0, 1}๐ = 8 รโ octal, {0, 1, 2, 3, 4, 5, 6, 7}๐ = 16 รโ hexadecimal, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, ๐, ๐, ๐, ๐, ๐, ๐}
Refresh: Decimal to Binary
(13)10 = (1 ร 101) + (3 ร 100)(1101)2 = (1 ร 23) + (1 ร 22) + (0 ร 21) + (1 ร 20) = 8 + 4 + 0 + 1 = (13)10
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 3 / 12
Unsigned Binary Integers
Unsigned Integers รโ the normal representation
An ๐-bit number:
๐ฅ = ๐ฅ๐โ12๐โ1 + ๐ฅ๐โ22๐โ2 +โฏ + ๐ฅ121 + ๐ฅ020
Has a factor up to 2๐โ1.Has a range: 0 to (2๐ โ 1)Example
0000 0000 0000 0000 0000 0000 0000 10112= 0 +โฏ + 1 ร 23 + 0 ร 22 + 1 ร 21 + 1 ร 20
= 0 +โฏ + 8 + 0 + 2 + 1 = 1110
Using 32 bits: 0 to +4,294,967,295
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 4 / 12
Signed Binary Integers (1/2)How to encode a negative sign?
Oneโs Compliment: Invert unsigned representation to get negative.Get value by inverting all bits then multiply by โ1.Leading bit decides if negative or not.All positive numbers have the same representation as unsigned.
In oneโs compliment:(0101)2 = (0101)2 = 5(1101)2 = โ1 ร (0010)2 = โ2(0000)2 = (0000)2 = 0(1111)2 = โ1 ร (0000)2 = โ0 ????
Oneโs compliment is rarely used:Signed zero.Weird borrowing required in arithmetic.
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 5 / 12
Signed Binary Integers (2/2)
How to encode a negative sign?
Twoโs Compliment: Invert all the bits with respect to 2๐
Same as treating leading bit as negative in expansion.Leading bit decides if negative or not.All positive numbers have the same representation as unsigned.
In twoโs compliment:(0101)2 = (0101)2 = 5(1101)2 = โ1 ร 23 + (0101)2 = โ8 + 5 = -3(0000)2 = (0000)2 = 0(1111)2 = โ1 ร 23 + (0111)2 = โ1
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 6 / 12
Twoโs Compliment
Advantages:Arithmetic is the same whether positive or negative:
(0101)2 = 5+ (1101)2 = โ3(0010)2 = 2 (Throw away carry bit)
No signed 0.One extra value represented with same number of bits.
For an ๐-bit number:Range of values is โ2๐โ1 to 2๐โ1 โ 1
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 7 / 12
Same Bits Different Numbers
It is important to realize that the same bit pattern can represent differentnumbers.
(1001 1010)2 รโ (154)10 interpretted as unsignedรโ (โ102)10 interpretted as twoโs compliment
Can be disastrous in programming!
unsigned int a = (1 << 31); // a = 2147483648int b = a; // b = -2147483648
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 8 / 12
Signed Negation
In twoโs compliment, bit-wise complement then add 1.
6 = (0110)2 = (0 ร 23) + (1 ร 22) + (1 ร 21) + (0 ร 20)โ compliment
(1001)2 = (โ1 ร 23) + (0 ร 22) + (0 ร 21) + (1 ร 20) = โ8 + 1โ add one(1001)2 + (0001)2 = (1010)2 = โ8 + 0 + 4 + 0 = โ6
Also works in reverse! (from negative to positive)รซ Still, compliment then add 1.รซ โ6 = (1010)2 โ (0101)2 + 1โ (0110)2 = 6
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 9 / 12
Signed Extension
Signed Extension:Represent a number using more bits but keep numerical value.Very easy in twoโs compliment!Copy the signed bit to the left until desired number of bits.
Examples: 8-bit to 16-bit2: 0000 0010 โ 0000 0000 0000 0010-2: 1111 1110 โ 1111 1111 1111 1110-10: 1111 0110 โ 1111 1111 1111 0110
Note: Truncation (representing a number using less bits) is tricky and youmust know what youโre doing.
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 10 / 12
Logical Shift
Logical Shift:Shift the bits left or right a specified number of times.Fills the vacancies with 0s on shift left and shift right.Throw away any bits that flow out.<< (shift left) and >> (shift right) in C (unsigned).
Examples (in 8 bits):2 << 3 = (0000 0010) << 3 = (0001 0000) = 16.8 >> 2 = (0000 1000) >> 2 = (0000 0010) = 2.-4 >> 1 = (1111 1100) >> 1 = (0111 1110) = 126.
รซ This last one is ambiguous if it is logical or arithmetic shift. Inhigh-level programming languages the right shift operator is usually anarithmetic shift...
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 11 / 12
Arithmetic Shift
Arithmetic Shift:Shift the bits left or right a specified number of times.Fills the vacancies with 0s on shift left.Fills the vacancies with 1s on shift right if number is negative.Fills the vacancies with 0s on shift right if number is positive.Throw away any bits that flow out.<< (shift left) and >> (shift right) in C (signed).
Examples (in 8 bits):2 << 3 = (0000 0010) << 3 = (0001 0000) = 16.8 >> 2 = (0000 1000) >> 2 = (0000 0010) = 2.-4 >> 1 = (1111 1100) >> 1 = (1111 1110) = -2.
Alex Brandt Chapter 2: Synchronous Circuits, Prelude Thursday January 24, 2019 12 / 12
CS3350B Computer OrganizationChapter 2: Synchronous Circuits
Part 1: Gates, Switches, and Boolean Algebra
Alex Brandt
Department of Computer ScienceUniversity of Western Ontario, Canada
Tuesday January 29, 2019
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 1 / 28
Outline
1 Introduction
2 Logic Gates
3 Boolean Algebra
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 2 / 28
Layers of Abstraction
After looking at high-level CPU and Memory we will now go down to thelowest level (that we care about).
Circuit Design vs Digital (Logic) Designรซ Design of individual circuits vs Using circuits to implement some logic.
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 3 / 28
Circuit Design
Why do we care?Appreciate the limitations of hardware.Understand why some things are fast and some things are slow.Need circuit design to understand logic design.Need logic design to understand CPU Datapath.
If you are ever working with:Assembly, ISAs,Embedded Systems and circuits,Specialized computer/logic systems,
you will need circuit and logic design.
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 4 / 28
Digital Circuits
Everything is digital: represented by discrete, individual values.รซ No gray areas or ambiguity.
Must convert an analog โ continuously variable โ signal to digital.
For us, the analog signal is electricity (voltage).รซ โHighโ voltage โ 1รซ โLowโ voltage โ 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 5 / 28
Physicality of Circuits
In the end, everything is a switch.
โInputโ โ AโOutputโ โ Z
If A is 0/false then switch is open.If A is 1/true then switch is closed.
This circuit implements:
A โก Z
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 6 / 28
Transistors: Electrically Controlled Switches
MOS-FET: Metal-Oxide-Semiconductor Field-Effect TransistorHas a source (S), a drain (D), and a gate (G).Applying voltage to G allows current to flow between S and D.In reality, transistors, logic gates, SRAM, use CMOS(Complimentary-MOS). But we donโt care about transistors really...
Flipping a transistor is much faster than moving a physical switch.รซ Speed of switching a transistor directly related to speed of a CPU
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 7 / 28
Outline
1 Introduction
2 Logic Gates
3 Boolean Algebra
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 8 / 28
Logic as Circuits
Propositional Logic: A set of propositions (truth values) combined bysome logical connectives.
Truth values โก Binary digital signalLogical connectives โก Logic gates
Logic Gate: A circuit implementing some logical expression/function.
The basics: AND (โง), OR (โจ), NOT (ยฌ).
Arity of a function/gate is the number of inputs.
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 9 / 28
Gates as Switches
Both A and B must be true/1to get the circuit to complete.
Either A or B can be true/1 toget the circuit to complete.
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 10 / 28
Logic Gates In Detail: AND
AB
C
A โง B โก C
A โ B โก C
Truth Table for AND
A B A โง B โก C0 0 00 1 01 0 01 1 1
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 11 / 28
Logic Gates In Detail: OR
AB
C
A โจ B โก C
A + B โก C
Truth Table for OR
A B A โจ B โก C0 0 00 1 11 0 11 1 1
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 12 / 28
Logic Gates In Detail: NOT
A C
ยฌ A โก C
A โก C
Truth Table for NOT
A ยฌ A โก C0 11 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 13 / 28
More Interesting Logic Gates: NAND
AB
C
ยฌ(A โง B) โก C
A โ B โก C
๐ด โ๏ธ ๐ต
Truth Table for NAND
A B A โ B โก C0 0 10 1 11 0 11 1 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 14 / 28
More Interesting Logic Gates: NOR
AB
C
ยฌ(A โจ B) โก C
A + B โก C
Truth Table for NOR
A B A + B โก C0 0 10 1 01 0 01 1 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 15 / 28
More Interesting Logic Gates: XOR (Exclusive OR)
AB
C
A โ B โก C
Truth Table for XOR
A B A โ B โก C0 0 00 1 11 0 11 1 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 16 / 28
Outline
1 Introduction
2 Logic Gates
3 Boolean Algebra
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 17 / 28
The Algebra of Logic Gates
Due to the equivalence of truth values and binary digital signals,Boolean Algebra is heavily used discussing circuitry.
Associativity:(๐ด +๐ต) +๐ถ โก ๐ด + (๐ต +๐ถ)(๐ด โ ๐ต) โ ๐ถ โก ๐ด โ (๐ต โ ๐ถ)Commutativity:
๐ด +๐ต โก ๐ต +๐ด
๐ด โ ๐ต โก ๐ต โ ๐ดDistributivity:
๐ด + (๐ต โ ๐ถ) โก (๐ด +๐ต) โ (๐ด +๐ถ)๐ด โ (๐ต +๐ถ) โก (๐ด โ ๐ต) + (๐ด โ ๐ถ)
Identity:๐ด + 0 โก ๐ด
๐ด โ 1 โก ๐ด
Annihilation:๐ด + 1 โก 1๐ด โ 0 โก 0
Idempotence:๐ด +๐ด โก ๐ด
๐ด โ ๐ด โก ๐ด
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 18 / 28
Boolean Algebra: More Interesting Laws
Absorption:
๐ด โ (๐ด +๐ต) โก ๐ด
๐ด + (๐ด โ ๐ต) โก ๐ด
Double Negation
๐ด โก ๐ด
Complementation:
๐ด +๐ด โก 1๐ด โ ๐ด โก 0
De Morganโs Laws:
๐ด +๐ต โก ๐ด โ ๐ต๐ด โ ๐ต โก ๐ด +๐ต
Look familiar?รซ Definitions of NOR and NAND.
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 19 / 28
Proving De Morganโs Laws
Proof by Exhaustion:รซ The easiest way to prove something is to write out each expressionโs
truth table.
๐ด +๐ต โก ๐ด โ ๐ต
A B A + B ๐ด +๐ต
0 0 0 10 1 1 01 0 1 01 1 1 0
A B ๐ด ๐ต ๐ด โ ๐ต0 0 1 1 10 1 1 0 01 0 0 1 01 1 0 0 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 20 / 28
Simplifying Expressions with Boolean Algebra (1/2)
๐ฅ๐ฆ๐ง + ๐ฅ๐ฆ๐ง
๐ฅ๐ฆ๐ง + ๐ฅ๐ฆ๐ง โก ๐ฅ๐ฆ(๐ง + ๐ง) Factor ๐ฅ๐ฆโก ๐ฅ๐ฆ(1) Complementation of ๐งโก ๐ฅ๐ฆ Identity with ๐ฅ๐ฆ
โ
๐ฅ ๐ฆ ๐ง ๐ฅ๐ฆ๐ง ๐ฅ๐ฆ๐ง ๐ฅ๐ฆ๐ง + ๐ฅ๐ฆ๐ง
0 0 0 1 0 10 0 1 0 1 10 1 0 0 0 00 1 1 0 0 01 0 0 0 0 01 0 1 0 0 01 1 0 0 0 01 1 1 0 0 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 21 / 28
Simplifying Expressions with Boolean Algebra (2/2)
Sometimes a truth table is too challenging...รซ For ๐ฃ variables a truth table has 2๐ฃ rows.
(๐ฅ + ๐ง) (๐๐๐๐ + ๐ฅ๐ง) รโ 6 variables, 64 rows
Instead we can simplify using the laws of Boolean algebra:
(๐ฅ + ๐ง) (๐๐๐๐ + ๐ฅ๐ง) โก ๐ฅ๐ง (๐๐๐๐ + ๐ฅ๐ง) De Morganโs Lawโก ๐ฅ๐ง (๐๐๐๐ + ๐ฅ๐ง) Double negation of ๐ฅ and ๐งโก ๐ฅ๐ง Absorption
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 22 / 28
Simplifying Expressions for Simplified Circuits
๐ฆ = ((๐๐) + ๐) + ๐
๐ฆ โก (๐๐ + ๐) + ๐โก ๐ (๐ + 1) + ๐ Factor ๐โก ๐ (1) + ๐ Annihilaltionโก ๐ + ๐ Identity
โ
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 23 / 28
Canonical FormsDifferent standard or canonical forms.
Conjunctive Normal Form (CNF) โ AND of ORsรซ โProduct-of-sumsโ
Disjunctive Normal Form (DNF) โ ORs of ANDsรซ โSum-of-productsโ
CNF (๐ + ๐) โ (๐ + ๐) โ (๐ + ๐)DNF ๐๐ + ๐๐ + ๐๐
Every variable should appear in every sub-expression.รซ Products for DNF, Sums for CNF.รซ Some authors call this "Full DNF" or "Full CNF".
Every boolean expression can be converted to a canonical form.DNF more useful and practical โ truth tables.
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 24 / 28
Truth Tables and Disjunctive Normal FormsWe can get a DNF expression directly from a truth table.
๐, ๐, ๐ are inputs, ๐ is output.Create one product term for every entry in the table with ๐ โก 1.Put ๐ฅ in product if ๐ฅ is false in that row.Put ๐ฅ in product if ๐ฅ is true in that row.OR all products together.
๐ ๐ ๐ ๐0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 11 0 1 01 1 0 01 1 1 1
รโ ๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 25 / 28
Functional Completeness
Functional Completeness - A set of functions (operators) which canadequately describe every operation and outcome in an algebra.
For Boolean algebra the classical set of operators: {+, โ ,ยฌ} isfunctionally complete but not minimal.
Thanks to De Morganโs Law we only need one of AND or OR.
The sets {+,ยฌ} and {โ ,ยฌ} are both functionally complete andminimal.
รซ minimal - removing any one of the operators would make the setfunctionally incomplete.
NAND alone is functionally complete; so is NOR alone.
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 26 / 28
NAND is Functionally Complete
NAND alone is functionally complete.NAND โก โ๏ธTo prove functional completenesssimply show that the operators ofthe set can mimic the functionalityof the set {+, โ ,ยฌ}.
ยฌ๐ โก๐ | ๐
๐ โ ๐ โก๐|๐ โก (๐|๐ ) | (๐|๐ )๐ +๐ โก๐ + ๐ โก๐ โ ๐ โก (๐ โ๏ธ๐) โ๏ธ (๐ โ๏ธ๐ )
๐ ๐ ๐ โ ๐ ๐ โ ๐0 1 0 11 0 1 0
X Y ๐ด โก๐|๐ ๐ด|๐ด0 0 1 00 1 1 01 0 1 01 1 0 1
X Y ๐ ๐ ๐ โ๏ธ๐0 0 1 1 00 1 1 0 11 0 0 1 11 1 0 0 1
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 27 / 28
Summary
Boolean algebra can simplify circuits.Remove variables that the output does not depend on.Simplifies expression, removing needless gates.Space and time complexity improved!
Truth tables, canonical forms, functional completeness.
Help generating truth tables:http://turner.faculty.swau.edu/mathematics/materialslibrary/truth/
Alex Brandt Chapter 2: Synchronous Circuits, Part 1: Gates & Boolean Algebra Tuesday January 29, 2019 28 / 28
CS3350B Computer OrganizationChapter 2: Synchronous Circuits
Part 2: Stateless Circuits
Alex Brandt
Department of Computer ScienceUniversity of Western Ontario, Canada
Tuesday February 05, 2019
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 1 / 27
Outline
1 Combinational Circuits
2 Adders and Subtractors
3 MUX and DEMUX
4 Arithmetic Logic Units
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 2 / 27
Stateless Circuits are Combinational Circuits
Stateless โ No memory.Combinational โ Output is a combination of the inputs alone.
Combinational circuits are formed from a combination of logic gates andother combinational cirtcuits.
รซ Modular Design,รซ Reuse,รซ Simple to add new components.
Sometimes, these are called functional blocks, they implement functions.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 3 / 27
Increasing Arity
Arity: the number of inputs to a gate, function, etc.
How can we build an ๐-way add from simple 2-input and gates?รซ Simply chain together ๐ โ 1 2-way gates.
Example: 5-way AND
Works for AND, OR, XOR. Doesnโt work for NAND, NOR.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 4 / 27
Block Diagrams
A block diagram or schematic diagram can use used to express thehigh-level specification of a circuit.
How many inputs, how many bits for each input?How many outputs, how many bits for each output?What does the circuit do? Formula or truth table.
๐น โก ๐๐๐ + ๐๐๐
๐ ๐ ๐ ๐น
0 0 0 10 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 5 / 27
From Blocks to Gates (1/2)
๐ ๐ ๐ ๐น
0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1
1 Generate truth table.
2 Get canonical form:
๐น โก ๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐
3 Simplify if possible:
๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐
โก ๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐
โก ๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐ + ๐๐๐โก ๐๐ + ๐๐ + ๐๐
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 6 / 27
From Blocks to Gates (2/2)
๐ ๐ ๐ ๐น
0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1
3 Simplify if possible:
๐น โก ๐๐ + ๐๐ + ๐๐
4 Draw your circuit from simplifiedformula.
This is called a majority circuit. Output istrue iff majority of inputs are true.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 7 / 27
Outline
1 Combinational Circuits
2 Adders and Subtractors
3 MUX and DEMUX
4 Arithmetic Logic Units
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 8 / 27
1 Bit Adder
Adder interprets bits as a binary number and does addition.
๐ = ๐๐๐(๐, ๐)๐ = carry (overflow) bit
๐ ๐ ๐ c0 0 0 00 1 1 01 0 1 01 1 0 1
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 9 / 27
1 Bit Full Adder
Full Adder does addition of 3 inputs: a, b, and carry๐๐.รซ Previous adder was a half adder.
๐ =๐๐๐ (๐, ๐, ๐๐๐)๐ = ๐๐ + (๐๐๐ (๐, ๐) โ ๐๐๐)
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 10 / 27
1 Bit Full Adder using Half Adders
A full adder can be built from half adders.รซ Modular design, reuse, simplified view.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 11 / 27
n-Bit Full Adder
๐-bit adder: Add ๐ bits with carry.รซ Just like long addition done by hand.รซ Combine ๐ full adders, adding bit by bit, carrying the carry from
lowest-ordered bit to highest-ordered bit.รซ Final carry bit is ๐๐.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 12 / 27
Addition Overflow (1/2)
Overflow occurs when arithmetic results in a number strictly larger thancan fit in the predetermined number of bits.
For unsigned integers, overflow is detected by ๐๐ being 1.For signed (i.e. twos-compliment) integers, overflow more interesting.
Example: Addition in 4 bits.
1000 (carry bits)1101+ 0110
10011 โ ๐๐ is 1. Overflow?
โ 3+ 63 โ No overflow
Discard last carry bit
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 13 / 27
Addition Overflow (1/2)
Overflow occurs when arithmetic results in a number strictly larger thancan fit in the predetermined number of bits.
For unsigned integers, overflow is detected by ๐๐ being 1.For signed (i.e. twos-compliment) integers, overflow more interesting.
Example: Addition in 4 bits.
1000 (carry bits)1101+ 0110
10011 โ ๐๐ is 1. Overflow?
โ 3+ 63 โ No overflow
Discard last carry bit
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 13 / 27
Addition Overflow (2/2)In twos-compliment when is there overflow?
Most significant bit encodes a negative number in twoโs compliment.If both operands are positive and ๐๐โ1 โก 1 then we have overflow.If one positive and one negative, overflow impossible.
รซ Their sum is always closer to zero than either of the operands.If both operands are negative and ๐๐ โก 1 then we have overflow.
1000 โ Overflow0101+01101011
1000+100010000 โ Overflow
10001101+ 0110
10011 โ No overflow
Overflow in twoโs compliment: ๐๐ XOR ๐๐โ1.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 14 / 27
n-bit Subtractor (1/2)
๐-bit subtractor: Subtract two ๐-bit numbers.We want ๐ = ๐ โ ๐.Start with an ๐-bit adder.XOR ๐ with a control signal for subtraction.
รซ signal is 1 for subtraction, 0 for addition.
XOR works as conditional inverter.รซ A XOR B โก C รโ if (B) then A โก C else A โก C.
A B A โ B โก C0 0 00 1 11 0 11 1 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 15 / 27
n-bit Subtractor (2/2)
Control signal SUB acts as ๐0.รซ Recall: signed negation. Invert and add one.รซ XOR does invert.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 16 / 27
Outline
1 Combinational Circuits
2 Adders and Subtractors
3 MUX and DEMUX
4 Arithmetic Logic Units
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 17 / 27
MultiplexerA multiplexer โmuxโ conditionally chooses among its inputs to set valueof output.
Uses control signal to control which input is chosen.Still no state, output depending only on inputs: input bits and controlsignal.
2-way multiplexer
If ๐ โก 0 then ๐ โก ๐.If ๐ โก 1 then ๐ โก ๐.
Notice actual value of ๐ and ๐ have no effect on decision.รซ 0 and 1 in multiplexer is not the value of ๐ or ๐ but the โindexโ.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 18 / 27
2-way Multiplexer
How to encode this โif-thenโ behaviour without actual conditionals?
๐ โก๐๐๐(๐, ๐, ๐ )โก ๐ ๐(๐ + ๐) + ๐ ๐(๐ + ๐)โก ๐ ๐ + ๐ ๐
Note: ๐ โ (๐ + ๐ ) encodes โ๐ independent of what the value of ๐ isโ.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 19 / 27
4-way Multiplexer
๐ โก๐๐๐(๐, ๐, ๐, ๐, ๐)โก ๐ 1๐ 0๐ + ๐ 1๐ 0๐+๐ 1๐ 0๐ + ๐ 1๐ 0๐
The index of each input is now 0 through 3.Need 2 bits to choose among 4 inputs.Control signalโs bit-width is now 2.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 20 / 27
Big Data Multiplexer
Bit-width of input and output must match, but bit-width of control signalonly determined by number of inputs to choose from.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 21 / 27
Demultiplexer
Demultiplexer โdemuxโ conditionally chooses among its outputs.รซ Opposite of MUX.รซ Un-selected outputs are set to 0.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 22 / 27
Outline
1 Combinational Circuits
2 Adders and Subtractors
3 MUX and DEMUX
4 Arithmetic Logic Units
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 23 / 27
Arithmetic Logic Unit
An ALU is a black-box type circuit which can do many differentarithmetic or logic operations on its inputs.
รซ Not many at one time, but selectively acts as many.
Depending on the implementation can do addition, subtraction,multiplication, division, logical AND, logical OR, shifting, etc.
Use a control signal to choose which operation to perform.
Essentially a big collection of MUX and combinational blocks for eachoperation.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 24 / 27
Simple ALU Circuit
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 25 / 27
Optimizing ALU
Remember, every additional gate increases delay and space. Instead,optimize via the normal four step process:
1 Generate a truth table,2 Get canonical from from truth table,3 Simplify expression,4 Make circuit.
Another option: programmable logic array.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 26 / 27
Programmable Logic ArrayA programmablelogic array (PLA)directly implements atruth table/canonicaldisjunctive normalform.
Each AND row isa truth table row.Each OR columnis one output bit.Each โ is aprogrammable(i.e. optional)join of the inputto the circuit.
Alex Brandt Chapter 2: Synchronous Circuits, Part 2: Stateless Circuits Tuesday February 05, 2019 27 / 27
CS3350B Computer OrganizationChapter 2: Synchronous Circuits
Part 3: State Circuits
Alex Brandt
Department of Computer ScienceUniversity of Western Ontario, Canada
Thursday February 07, 2019
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 1 / 37
Outline
1 Digital Signals
2 The Clock
3 Flip-Flops and Registers
4 Finite State Machines
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 2 / 37
Digital Signals
We digitalize an analog (voltage) signal to encode binary.โHighโ voltage โ 1.โLowโ voltage โ 0.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 3 / 37
Transmitting Digital Signals
For our purposes:Transmission is continuous. Thereโs always something on the wire.Transmission/switching is effectively instantaneous.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 4 / 37
Grouping Signals To Encode Many Bits
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 5 / 37
Signals and Circuits
Unfortunately for us,combinational circuitscause propagation delay.
The more complexthe circuit the longerthe delay.Every gate addssome delay.
2 5 3 -3
2 1 2 3
4 6 5 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 6 / 37
Dealing with Delay
Problems with propagation delay:Inputs transmit (change) instantaneously, but output does not.When can the next circuit read the output and ensure it is getting thecorrect value?
Synchronize the circuits via a clock.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 7 / 37
Outline
1 Digital Signals
2 The Clock
3 Flip-Flops and Registers
4 Finite State Machines
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 8 / 37
The Clock Signal
The clock is a digital signal which has a precise timing for switchingbetween 1/0.
Synchronous circuits use the clock to sync their executions, decide whento read inputs/outputs.
รซ Heartbeat of a synchronous system.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 9 / 37
How to Synchronize
Circuits usually synchronize to the rising edge of the clock.รซ The transition from 0 to 1.รซ Depending on the system, can instead sync on the falling edge.
0,0 1,0 0,1 1,0
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 10 / 37
Clock Multipliers
We know that CPU and memory operate at difference speeds. So how dothey synchronize?
One central clock used.Central clock is as slow as the slowest component.Faster components use a clock multiplier.
A clock multiplier multiplies the central clock frequency so that acomponent has many internal cycles for a single clock cycle of the entiresystem.
Note: this is simply a technicality of implementation. Generally, we stilldiscuss speeds based on frequency the CPU experiences. Our old metricsstill work as they always have.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 11 / 37
Outline
1 Digital Signals
2 The Clock
3 Flip-Flops and Registers
4 Finite State Machines
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 12 / 37
Circuits that Remember
Sometimes values on a wire (i.e. a bit) cannot be maintained indefinitelyon that wire. Values must change.
Computer memory is circuits which remember.Circuits implement memory but are also used within other circuits tohold state.
รซ Modular design.
Flip-flop: a circuit which implements a single bit of memory.รซ All flip-flops based on a simple design: inputs, combined with current
state, give next state.รซ Essentially, the implementation of static RAM (SRAM).
Register: a storage for multiple bits of memory.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 13 / 37
Edge-Triggered Flip-Flop
A flip-flop which looks at its input on the edge of clock.รซ Rising edge or positive edge (usually), orรซ Falling edge or negative edge.
This is a delay flip-flop
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 14 / 37
D Flip-Flop
Delay flip-flop: takes input and, with some delay, sets output equal tothe input.
รซ Simplest (conceptually) flip-flop.รซ Requires constant updating to maintain state.รซ Grabs input on rising edge and outputs that until next clock cycle.รซ Current state does not affect next state.
D Q Q๐๐๐ฅ๐ก
0 - 01 - 1
Flip-flops usually produce next state and negation of next statesimultaneously.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 15 / 37
T Flip-Flop
Toggle flip-flop: if input is 1, toggle current state.รซ Uses current state to determine next state.รซ ๐ โก 0โ โHoldโ. Next state is same as current.รซ ๐ โก 1โ โToggleโ. Next state is opposite of current.
T Q Q๐๐๐ฅ๐ก
0 0 00 1 11 0 11 1 0
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 16 / 37
SR Flip-Flop
Set-Reset flip-flopรซ Two inputs, S (set), R (reset), synchronized by a clock.รซ ๐ โก 1โ โSetโ. Next state is 1.รซ ๐ โก 1โ โResetโ. Next state is 0.รซ ๐ โก 0 โง๐ โก 0โ โHoldโ.
S R Q Q๐๐๐ฅ๐ก
0 0 - Q0 1 - 01 0 - 11 1 - -
Can not have both ๐ and ๐ set to 1. . .
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 17 / 37
SR Technicalities
E โenableโ โโ clock
๐ โก ๐ โก ๐ธ โก 1 รโ 1 +๐ โก 0 โก 1 +๐ รโ ๐ โก ๐ ???
We get undefined behaviour. This is weird and can destabilize the system.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 18 / 37
JK Flip-Flop
JK flip-flopรซ Two inputs, J (set), K (reset), synchronized by a clock.รซ Same as SR except with toggle.รซ ๐ฝ โก 1 โง๐พ โก 1โ โToggleโ.
J K Q Q๐๐๐ฅ๐ก
0 0 - Q0 1 - 01 0 - 11 1 - ๐
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 19 / 37
Registers
A register is just a collection of flip-flops.Technically, this is a shift register.๐-bits รโ ๐ flip-flops.Clock pulse connected to all flip-flops.Can be encoded using any type of flip-flop.
This example is a parallel in, parallel out register.Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 20 / 37
PIPO Registers
Parallel In, Parallel Out Register: All inputs bits come in in parallel,and output bits get output in parallel.
Most common.Input/output of each flip-flop is independent.Can be encoded using any type of flip-flop.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 21 / 37
SIPO RegistersSerial In, Parallel Out Register: One input bit at a time, output all bitsat once.
Input bit moves through chain of flip-flops.Transitions at each clock.
This example uses D flip-flops.Sometimes it is useful to clear the entire register without waiting ๐cycles for ๐ bits of data to shift out.Additional control signals can be used to set all flip-flops to 1 (๐) orall flip-flops to 0 (๐ ).
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 22 / 37
SISO/PISO Registers
Serial In, Serial Out Register: A linear chain of flip-flops.Output of one flip-flop is the input of the next.One input bit and one output bit.Kind of like a conveyor belt of bits.
Parallel In, Serial Out Register: A linear chain of flip-flops + controlcircuits.
Data loaded in parallel: ๐ flip-flops load ๐ bits at once.Data output in serial: Acts as SISO for output.
รซ Output one bit at a time.รซ Bits are shifted one over on each output.
Requires clock and additional write/shift control signal.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 23 / 37
Timing a Flip-Flop
All gates/circuits introduce propagation delay.
For flip-flops this propagation delay is called clk-to-q delay.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 24 / 37
Timing a Flip-Flop: Data Stability
Input to a flip-flop must have a stable value around the rising edge of theclock.
รซ Before the rising edge: setup time.รซ After the rising edge: hold time.
setup hold
Despite how itโs shown here, hold time is less than clk-to-q delay.Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 25 / 37
Putting it all Together: Accumulator
An accumulator: continually adds input value to its stored value.
This doesnโt work.Would spin once per circuitโs propagation delay, not once per input.Need clock to synchronize reading from input.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 26 / 37
Clocked Accumulator
Insert register to store output.
Only need to clock the register,not the combinational circuit.
Clock on register determineswhen output of circuit actuallygets stored.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 27 / 37
Timing the Accumulator
adderdelay clk-to-q
setup
Clock must be slow enough to include:Adder delay,Clk-to-q,Setup time.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 28 / 37
Synchronous Circuits: Clock Frequency
(Max Clock Freq.)Min. Clock Period = Combinational Circuit Propagation Delay
+ Setup Time+ Clk-To-Q
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 29 / 37
Pipeline for Performance (1/2)
Delay of adder and shifter is very long.Forces clock cycle to be very long.Slows down other circuits in this synchronous system.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 30 / 37
Pipeline for Performance (2/2)
Split add and shift into two different tasks.Insert register between to store results temporarily.Increase clock frequency.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 31 / 37
General Synchronous Systems
All systems follow a general pattern:A chain of logic circuit blocks, separated by registers, controlled by asingle clock.Foreshadowing for MIPS pipeline.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 32 / 37
Outline
1 Digital Signals
2 The Clock
3 Flip-Flops and Registers
4 Finite State Machines
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 33 / 37
Finite State Machines: Introduction
We know FSMs from logic, formal languages, complexity.
Each state of the machine is anode.Inputs trigger change of stateand an output.This is a Mealy machine:outputs occur on transitions.Moore machines are equivalent.
รซ Output is based on currentstate.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 34 / 37
Finite State Machines: As Circuits
FSMs have three components: state, input, output.Just like synchronous circuit.Registers, input bits, output bits.Clock controls when inputs read โ transitions.PS: present state, NS: next state.
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 35 / 37
Finite State Machines: Implementing The LogicNext state and output is always just some Boolean combination of inputand output. Use our normal 4-step process:
1. Build a truth table,2. Get canonical form,3. Simplify,4. Draw circuit.
PS In NS Out00 0 01 000 1 01 101 - 10 010 0 10 110 1 11 111 0 10 011 1 11 1
โโ FSM state diagram
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 36 / 37
FSMs are Synchronous Systems are FSMs
Essentially every synchronous system can be modelled by an FSM.รซ Would become absurdly large in most circumstances.
A valid design strategy for integrated circuits and specializedhardware includes:
1 Turn problem into FSM.2 Turn FSM into truth table.3 Turn truth table into circuit.
Full Example: An elevator-controlling circuit.รซ https://www.cs.princeton.edu/courses/archive/spr06/
cos116/FSM_Tutorial.pdf
Alex Brandt Chapter 2: Synchronous Circuits, Part 3: State Circuits Thursday February 07, 2019 37 / 37