cs2100 12 basic datapath
TRANSCRIPT
CS2100 Computer Organisation
Basic Datapath
CS2100 Basic Datapath 2
REVIEW: EDGE-TRIGGERED D FLIP-FLOP
Value of D is sampled on negative clock edge.
Q outputs sampled value for the rest of cycle.
CS2100 Basic Datapath 3
REVIEW: D LATCH VS D FLIP FLOP
CS2100 Basic Datapath 4
SINGLE CYCLE DATAPATH
Not used in reality! Only for teaching purposes.
All instructions execute in a single cycle of the clock (negative edge to
negative edge)
clk
T
CS2100 Basic Datapath 5
THE INSTRUCTION PROCESSING CYCLE
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INSTRUCTION FETCH
➤Obtain the instruction to be executed➤From where?
Ans: where PC is pointing to!➤Need to read from instruction memory (main memory)
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INSTRUCTION DECODE
➤ Decode instruction to find out what to do➤ Input: the instruction to be executed➤ Output: the control signals to the other parts of
the processor telling various units what to do so that together they execute this instruction– Examples: what register(s) to read, what ALU
operation to perform
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OPERAND FETCH
➤ Get the operands needed by the instruction to compute on
➤ Read from the registers– Registers are kept together in the register file (RISC
architecture)
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EXECUTE
➤ Do it!
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RESULT STORE
➤Write result of computation back to the register file
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THE INSTRUCTION PROCESSING CYCLE
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➤ Our implementation of the MIPS is simplified– memory-reference instructions: lw, sw – arithmetic-logical instructions: add, sub, and, or, slt– control flow instructions: beq, j
➤ Generic implementation– use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC)
– decode the instruction (and read registers)– execute the instruction
➤ All instructions (except j) use the ALU after reading the registers
THE PROCESSOR: DATAPATH & CONTROL
FetchPC = PC+4
DecodeExec
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CLOCKING METHODOLOGIES
➤ The clocking methodology defines when signals can be read and when they are written– An edge-triggered methodology
➤ Typical execution– read contents of state elements – send values through combinational logic– write results to one or more state elements
CS2100 Basic Datapath 14
CLOCKING METHODOLOGIES
Stateelement
1
Stateelement
2
Combinationallogic
clock
one clock cycle
➤ Assumes state elements are written on every clock cycle; if not, need explicit write control signal– write occurs only when both the write control is asserted and the
clock edge occurs
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FETCHING INSTRUCTIONS
➤ Fetching instructions involves– reading the instruction from the Instruction Memory– updating the PC to hold the address of the next
instruction
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FETCHING INSTRUCTIONS
ReadAddress
Instruction
InstructionMemory
Add
PC
4
– PC is updated every cycle, so it does not need an explicit write control signal
– Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal
CS2100 Basic Datapath 17
SEQUENTIAL LOGIC
ReadAddress
Instruction
InstructionMemory
Add
PC
4
CLK
CS2100 Basic Datapath 18
SEQUENTIAL LOGIC
ReadAddress
Instruction
InstructionMemory
Add
PC
4
CLK
CS2100 Basic Datapath 19
SEQUENTIAL LOGIC
ReadAddress
Instruction
InstructionMemory
Add
PC
4
CLK
CS2100 Basic Datapath 20
FETCHING STRAIGHT LINE CODE
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THE FIRST REGISTER - PC
➤ Build from an array of D-flip-flops
CLK
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DECODING INSTRUCTIONS
➤ Decoding instructions involves– sending the fetched instruction’s opcode and function field
bits to the control unit
Instruction
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ControlUnit
CS2100 Basic Datapath 23
DECODING INSTRUCTIONS
– reading two values from the Register File• Register File addresses are contained in the instruction
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DEMAND ON THE REGISTER FILE
➤ Must be able to:– Read two registers– Write one register
at the same time!➤ Technically, we need two read ports and one write port➤ Each port includes
– Register number to be read from/written to– Control signals
REGISTER FILE
R0 – the constant 0 Q
R1 QDEN
R2 QDEN
R31 QDEN
.
.
.
MUX
MUX
32
32
32
32
.
.
.
.
.
.
32
32
sel(rs2)
sel(rs1)
5
5
CLK
DEMUX
32
wd
sel(ws)
5
rd1
rd2
Two read ports
One write port
WE
CS2100 Basic Datapath 26
EXECUTING R FORMAT OPERATIONS
➤ R format operations (add, sub, slt, and, or)
– perform the (op and funct) operation on values in rs and rt– store the result back into the Register File (into location rd)
R-type:
31 25 20 15 5 0
op rs rt rd functshamt
10
CS2100 Basic Datapath 27
EXECUTING R FORMAT OPERATIONS
Instruction
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
overflowzero
ALU controlRegWrite
– The Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File
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THE ALU
➤ A combination of adder, multiplier, shifter, logical operations etc.
➤ Operations to be done selected by control signals– Control signals generated during decode time
➤ Additional outputs– Is it zero? – Did an overflow occur?– Typically the flags:
• Zero
• Carry
• Overflow
• Negative
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DEALING WITH IMMEDIATES
Some MIPS instructions require zero-extension, some require sign extension - control signals have to be generated during decode
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EXECUTING LOAD AND STORE OPERATIONS
➤ Load and store operations involves– compute memory address by adding the base register (read from
the Register File during decode) to the 16-bit signed-extended offset field in the instruction
– store value (read from the Register File during decode) written to the Data Memory
– load value, read from the Data Memory, written to the Register File
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EXECUTING LOAD AND STORE OPERATIONS
Instruction
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
overflowzero
ALU controlRegWrite
DataMemory
Address
Write Data
Read Data
SignExtend
MemWrite
MemRead
16 32
CS2100 Basic Datapath 32
ADDING MEMORY OPERATIONS
InstructionFetch
InstructionDecode
OperandFetch
Execute
ResultStore
InstructionFetch
InstructionDecode
OperandFetch
Execute
MemoryRead/Write
ResultStore
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EXECUTING BRANCH OPERATIONS
➤ Branch operations involves– compare the operands read from the Register File during decode
for equality (zero ALU output)– compute the branch target address by adding the updated PC to
the 16-bit signed-extended offset field in the instr
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EXECUTING BRANCH OPERATIONS
Instruction
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
zero
ALU control
SignExtend16 32
Shiftleft 2
Add
4 Add
PC
Branchtargetaddress
(to branch control logic)
CS2100 Basic Datapath 35
EXECUTING JUMP OPERATIONS
➤ Jump operation involves– replace the lower 28 bits of the PC with the lower 26 bits of the
fetched instruction shifted left by 2 bits
ReadAddress
Instruction
InstructionMemory
Add
PC
4
Shiftleft 2
Jumpaddress
26
4
28
CS2100 Basic Datapath 36
CREATING A SINGLE DATAPATH FROM THE PARTS
➤ Assemble the datapath segments and add control lines and multiplexors as needed
➤ Single cycle design – fetch, decode and execute each instructions in one clock cycle– no datapath resource can be used more than once per
instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders)
– multiplexors needed at the input of shared elements with control lines to do the selection
– write signals to control writing to the Register File and Data Memory
➤ Cycle time is determined by length of the longest path
CS2100 Basic Datapath 37
FETCH, R, AND MEMORY ACCESS PORTIONS
MemtoReg
ReadAddress
Instruction
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovfzero
ALU controlRegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemReadSign
Extend16 32
ALUSrc
CS2100 Basic Datapath 38
ADDING THE CONTROL
➤ Selecting the operations to perform (ALU, Register File and Memory read/write)
➤ Controlling the flow of data (multiplexor inputs)
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➤ Observations– op field always
in bits 31-26– addr of registers
to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16); for lw and sw rs is the base register
– addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions
– offset for beq, lw, and sw always in bits 15-0
I-Type:
ADDING THE CONTROL
op rs rt address offset
31 25 20 15 0
R-type:
31 25 20 15 5 0
op rs rt rd functshamt
10
J-type:31 25 0
op target address
SINGLE CYCLE DATAPATH WITH CONTROL UNIT
ReadAddress Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend
16 32
MemtoReg
ALUSrc
Shift
left 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
0
00
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnitInstr[31-26]
Branch
CS2100 Basic Datapath 41
R-TYPE INSTRUCTION DATA/CONTROL FLOW
CS2100 Basic Datapath 42
LOAD WORD INSTRUCTION DATA/CONTROL FLOW
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BRANCH INSTRUCTION DATA/CONTROL FLOW
ADDING THE JUMP OPERATION
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Controls
Instruction [31-26]
R-type
0000001 0 0 1 0 0 0 1 0 0
lw
1000110 1 1 1 1 0 0 0 0 0
sw
101011X 1 X 0 0 1 0 0 0 0
beq
000100X 0 X 0 0 0 1 0 1 0
j
000010X X X 0 0 0 0 0 0 1
Re
gD
st
AL
US
rc
Me
mto
Re
g
Re
gW
rite
Me
mR
ea
d
Me
mW
rite
Bra
nc
h
AL
UO
p1
AL
UO
p2
Ju
mp
CS2100 Basic Datapath 46
ALU operations
➤Assume 4 bit ALU control lines– 0000 → AND– 0001 → OR– 0010 → add– 0110 → subtract– 0111 → set less than– 1100 → NOR
CS2100 Basic Datapath 47
How ALU depends on ALUop
OPcode ALUop Operation Funct field Desired op ALU control
lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch eq XXXXXX subtract 0110
R-type 10 add 100000 add 0010
R-type 10 subtract 100010 subtract 0110
R-type 10 AND 100100 and 0000
R-type 10 OR 100101 or 0001
R-type 10 slt 101010 slt 0111
CS2100 Basic Datapath 48
Truth table for ALUop
ALUOp1 ALUOp0 Funct Operation (output)
0 0 XXXXXX 0010
X 1 XXXXXX 0110
1 X XX0000 0010
1 X XX0010 0110
1 X XX0100 0000
1 X XX0101 0001
1 X XX1010 0111
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READING ASSIGNMENT
➤ The Processor: Datapath and Control– Read up COD Chapter 5.
CS2100 Basic Datapath 50
END