DATA MANIPULATION

1

2.1 COMPUTER ARCHITECTURE

Data Manipulation2

COMPUTER ARCHITECTURE

Central Processing Unit (CPU)

Arithmetic Logic Unit (ALU)

Registers

General-purpose

Special-purpose

Control Unit

Input/output (I/O) Unit

2-3

MODERN INTEL AND AMD CPUS

Intel Core i7 AMD Phenom II X4

4

45NM PROCESSOR WAFER

2-5

Data Bus

Address Bus

Control Bus123

0 4567

9AB

8

EF

CD

CONSTITUENT COMPONENTS OF A CPU

I/O Unit

Control UnitProgram Counter (PC)

Instruction Register (IR)

Other Other

Other Other

Other Other

Registers

ALU

2-6

A BUS

2-7

COMPUTER BUSES

Collection of wires that connect the components of

a computer to one another

Address

Data

Control

Power (usually ignored)

2-8

CPU AND MEMORY

CONNECTED VIA A BUS

S

y

s

t

e

m

M

e

m

o

r

y

CPU

Bus

2-9

ADDING TWO VALUES STORED IN SYSTEM MEMORY

IS A FIVE-STEP PROCESS

Step 1 Get the first value to be added from memory and store

it in a register.

Step 2 Get the second value to be added from memory and

store it in another register.

Step 3 Activate the circuitry in the ALU responsible for

addition. Add the values from Steps 1 & 2 and store

the sum in a third register.

Step 4 Write the contents of register holding the result back to

some address in memory.

Step 5 Halt.

2-10

STORED PROGRAMS

Programs can be encoded as a sequence of bits

and stored in system memory

Obvious today

Not always so

Early computers were hard-wired

Difficult to re-program

von Neumann architecture

Memory is an array of individually-addressable cells that

store both instructions and data

Control unit interprets and executes instructions

2-11

ENIAC BEING PROGRAMMED

BY EARLY COMPUTERS

2-12

VON NEUMANN ARCHITECTURE

S

y

s

t

e

m

M

e

m

o

r

y

I

/

O

D

e

v

i

c

e

s

ALU

Control Unit

CPU

2-13

TYPES OF MEMORY

Registers

Cache

System Memory

Mass Storage

P

r

i

c

e

Q

u

a

n

t

i

t

y

S

p

e

e

d

2-14

2.2 MACHINE LANGUAGE

Data Manipulation15

MACHINE LANGUAGE

Machine instruction: a command recognized by the CPU and encoded as a bit pattern

Machine language: the set of machine instructions a particular CPU recognizes

Flavors:

Reduced Instruction Set Computer (RISC)

Complex Instruction Set Computer (CISC)

Instruction categories:

Data transfer

Arithmetic/logic

Control 2-16

EXAMPLE: DIVIDING VALUES STORED IN MEMORY

Step 1 LOAD a register with value from memory.

Step 2 LOAD another register with another value from

memory.

Step 3 If this second value equals zero, JUMP to Step 6.

Step 4 Divide the contents of the first register by the contents

of the second register putting the quotient in a third

register.

Step 5 Store the contents of the third register in memory.

Step 6 HALT.2-17

AN ILLUSTRATIVE MACHINE LANGUAGE

We will be using the hypothetical machine

described in Appendix C of the book:

16 one-byte, general-purpose registers

256 one-byte memory cells

Two-byte instructions

2-18

ARCHITECTURE OF THE MACHINE IN

APPENDIX C

Registers

ALU

Control Unit

PC

IR

0123

4567

89AB

CDEF

2-19

INSTRUCTION AND DATA TEMPLATES

0 0 1 1 0 1 0 1 1 0 1 0 0 1 1 1

1 1 0 0 1 0 0 00 1 0 1 0 1 1 1

opcode operand operand operand

Instruction Template

mantissaexponent

exponent

Integer Template Floating-Point Template

2-20

EXAMPLE: ADDING VALUES STORED IN MEMORY

Encoded

InstructionTranslation

156C LOAD register 5 with the bit pattern found at address

6C.

166D LOAD register 6 with the bit pattern found at address

6D.

5056 ADD contents of registers 5 and 6 and put the sum in

register 0.

306E STORE the contents of register 0 in address 6E.

C000 HALT.

2-21

2.3 PROGRAM EXECUTION

Data Manipulation22

THE MACHINE CYCLE

Fetch

• [PC] → IR

• Increment PC

Decode

• Interpret IR

• Fetch operand(s)

Execute

• Carry out instruction

2-23

PROGRAMS VS DATA

Everything in memory is encoded in strings of 1’s

and 0’s

There is no differentiation between data and code

The control unit interprets the contents of certain

cells as instructions and other cells as data

Programs can even modify themselves during execution

2-24

EXAMPLE PROGRAM WALK-THROUGH (PG. 98)

Registers

ALU

Control Unit

PC

IR

0123

4567

89AB

CDEF

2-25

2.4 ARITHMETIC/LOGIC INSTRUCTIONS

Data Manipulation26

LOGICAL OPERATIONS

1 0 0 1 1 0 1 0

AND 1 1 0 0 1 0 0 1

1 0 0 0 1 0 0 0

1 0 0 1 1 0 1 0

XOR 1 1 0 0 1 0 0 1

0 1 0 1 0 0 1 1

1 0 0 1 1 0 1 0

OR 1 1 0 0 1 0 0 1

1 1 0 1 1 0 1 1

2-27

BIT MAPS

A bit map is a way of using a value in the computer

by assigning each bit in the value some meaning

We could store the day of the week in a byte

7 6 5 4 3 2 1 0

Not

Used

Satu

rday

Fri

day

Thurs

day

Wednesday

Tuesday

Monday

Sunday

2-28

MASKS

Using a mask we can extract the status of any

given bit(s) in a string of bits

The following example tests to see if it’s Friday yet:

Bit Map 0 0 0 0 0 0 1 0

Mask (AND) 0 0 1 0 0 0 0 0

Result 0 0 0 0 0 0 0 0

2-29

BIT SHIFTING

Circular Shifts

Also called rotations

Logical Shifts

Left or right

Also called arithmetic shifts

2-30

2.5 COMMUNICATING WITH

OTHER DEVICES

Data Manipulation31

CONTROLLERS ATTACHED TO A

MACHINE’S BUS

2-32

MOTHERBOARD

BLOCK DIAGRAM

2-33

X58 CHIPSET ARCHITECTURE

2-34

MEMORY-MAPPED I/O

In many computers I/O devices are read from and

written just as memory is

A certain amount of address space is set aside for

communicating with memory-mapped devices

These addresses reside at the top of the addressable

memory range

232 = 4,294,967,296 or 4,096 MB

264 = 18,446,744,073,709,551,616

18 quintillion bytes

18 petabytes PB

17,592,186,044,416 MB

2-35

MISSING RAM

2-36

DIRECT MEMORY ACCESS (DMA)

Allows certain hardware subsystems to access

system memory independently of the CPU

Historically the CPU would have been responsible

for every bit transferred in the computer

DMA allows peripherals to transfer blocks of data to

and form memory without CPU intervention

2-37

HANDSHAKING

Two-way communication between the processor

and a peripheral device

Status word: a bit map used to communicate

between the system and the external device

One bit may indicate an out-of-paper error

Another signals the printer is ready for more data

The controller monitors the status and passes

important messages along to the CPU

2-38

PARALLEL VS SERIAL COMMUNICATION

1-bit at a time

Simple to implement

Lower bandwidth than

parallel

Able to transmit over

longer distances than

parallel

Multiple bits at a time

Higher bandwidth than

serial

Trickier to implement

Limited distance

Propagation delay

“Noisy”

Mutual inductance

Capacitance

Serial Parallel

39

2.6 OTHER ARCHITECTURES

Data Manipulation41

PIPELINING

Technique for speeding up execution of a program

Each stage of the machine cycle can run in parallel

on different instructions

Bubbles

Stalls

Bad prediction

2-42

PIPELINING

t0 t1 t2 t3 t4 t5 t6 t7 t8

Fetch

Decode

Execute

Write

Completed

Fetch

Decode

Execute

Write

Completed

With

out

Pip

elin

ing

With

Pip

elin

ing

2-43

PARALLEL PROCESSING AND

MULTIPROCESSOR MACHINES

Parallel processing means to execute multiple

threads or processes simultaneously

Pipelining is a step in this direction

True parallel processing require more than one

CPU

Several strategies

Multiple, independent processors sharing memory while

executing separate processes

Multiple cores operating on the same data at the same

time executing the same set of instructions

A single core operating on multiple data sets at the

same time 2-44