cs 61c: great ideas in computer architecture (machine structures) single-cycle processor design

CS 61C: Great Ideas in Computer Architecture (Machine Structures)

Single-Cycle Processor DesignInstructors:

Randy H. KatzDavid A. Patterson

http://inst.eecs.Berkeley.edu/~cs61c/fa10

04/21/23 1Fall 2010 -- Lecture #26

Agenda

• MIPS-lite Datapath• Administrivia• Technology Break• CPU Timing

04/21/23 2Fall 2010 -- Lecture #26

Agenda

• MIPS-lite Datapath• Administrivia• Technology Break• CPU Timing

04/21/23 3Fall 2010 -- Lecture #26

• ADDU and SUBU– addu rd,rs,rt– subu rd,rs,rt

• OR Immediate:– ori rt,rs,imm16

• LOAD and STORE Word– lw rt,rs,imm16– sw rt,rs,imm16

• BRANCH:– beq rs,rt,imm16

op rs rt rd shamt funct

061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits

op rs rt immediate

016212631

6 bits 16 bits5 bits5 bits

op rs rt immediate

016212631


op rs rt immediate

016212631


The MIPS-lite Subset

04/21/23 4Fall 2010 -- Lecture #26

• RTL gives the meaning of the instructions

• All start by fetching the instruction

{op , rs , rt , rd , shamt , funct} MEM[ PC ]

{op , rs , rt , Imm16} MEM[ PC ]

Inst Register Transfers

ADDU R[rd] R[rs] + R[rt]; PC PC + 4

SUBU R[rd] R[rs] – R[rt]; PC PC + 4

ORI R[rt] R[rs] | zero_ext(Imm16); PC PC + 4

LOAD R[rt] MEM[ R[rs] + sign_ext(Imm16)]; PC PC + 4

STORE MEM[ R[rs] + sign_ext(Imm16) ] R[rt]; PC PC + 4

BEQ if ( R[rs] == R[rt] ) then PC PC + 4 + (sign_ext(Imm16) || 00) else PC PC + 4

Register Transfer Language (RTL)

04/21/23 5Fall 2010 -- Lecture #26

Processor Design Process

• Five steps to design a processor:Step 1: Analyze instruction set to determine datapath

requirementsStep 2: Select set of datapath components & establish

clock methodologyStep 3: Assemble datapath components that meet the

requirementsStep 4: Analyze implementation of each instruction to

determine setting of control points that realizes the register transfer

Step 5: Assemble the control logic

04/21/23 Fall 2010 -- Lecture #26 6

Step 1: Requirements of the Instruction Set

• Memory (MEM)– Instructions & data (will use one for each)

• Registers (R: 32 x 32)– Read RS– Read RT– Write RT or RD

• PC• Extender (sign/zero extend)• Add/Sub/OR unit for operation on register(s) or extended

immediate• Add 4 (+ maybe extended immediate) to PC• Compare registers?

04/21/23 Fall 2010 -- Lecture #26 7

Generic Steps of Datapath

instruction

memory

+4

rtrs

rd

registers

ALU

Data

memory

imm

1. InstructionFetch

2. Decode/ Register

Read

3. Execute 4. Memory 5. Register Write

PC

04/21/23 8Fall 2010 -- Lecture #26

Step 2: Components of the Datapath

• Combinational Elements• Storage Elements + Clocking Methodology• Building Blocks

04/21/23 Fall 2010 -- Lecture #26 9

32

32

A

B32

Sum

CarryOut

CarryIn

Adder

32A

B32

Y32

Select

MU

X

Multiplexer

32

32

A

B32

Result

OP

ALU

ALU

Adder

ALU Needs for MIPS-lite + Rest of MIPS• Addition, subtraction, logical OR, ==:

ADDU R[rd] = R[rs] + R[rt]; ...

SUBU R[rd] = R[rs] – R[rt]; ...

ORI R[rt] = R[rs] | zero_ext(Imm16)...

BEQ if ( R[rs] == R[rt] )...

• Test to see if output == 0 for any ALU operation gives == test. How?

• P&H also adds AND, Set Less Than (1 if A < B, 0 otherwise)

• ALU follows Chapter 5

04/21/23 10Fall 2010 -- Lecture #26

Storage Element: Idealized Memory

• Memory (idealized)– One input bus: Data In– One output bus: Data Out

• Memory word is found by:– Address selects the word to put on Data Out– Write Enable = 1: address selects the memory

word to be written via the Data In bus• Clock input (CLK) – CLK input is a factor ONLY during write operation– During read operation, behaves as a combinational logic

block: Address valid Data Out valid after “access time”

04/21/23 Fall 2010 -- Lecture #26 11

Clk

Data In

Write Enable

32 32DataOut

Address

Storage Element: Register (Building Block)

• Similar to D Flip Flop except– N-bit input and output– Write Enable input

• Write Enable:– Negated (or deasserted) (0): Data Out will not

change– Asserted (1): Data Out will become Data In on

positive edge of clock

clk

Data In

Write Enable

N N

Data Out

04/21/23 12Fall 2010 -- Lecture #26

Storage Element: Register File• Register File consists of 32 registers:

– Two 32-bit output busses:busA and busB

– One 32-bit input bus: busW• Register is selected by:

– RA (number) selects the register to put on busA (data)– RB (number) selects the register to put on busB (data)– RW (number) selects the register to be written

via busW (data) when Write Enable is 1• Clock input (clk)

– Clk input is a factor ONLY during write operation– During read operation, behaves as a combinational logic block:

• RA or RB valid busA or busB valid after “access time.”

04/21/23 Fall 2010 -- Lecture #26 13

Clk

busW

Write Enable

3232

busA

32busB

5 5 5RW RA RB

32 x 32-bitRegisters

Step 3: Assemble DataPath Meeting Requirements

• Register Transfer Requirements Datapath Assembly

• Instruction Fetch• Read Operands and Execute

Operation• Common RTL operations– Fetch the Instruction:

mem[PC]– Update the program counter:

• Sequential Code:PC PC + 4

• Branch and Jump:PC “something else”

04/21/23 Fall 2010 -- Lecture #26 14

32

Instruction WordAddress

InstructionMemory

PCclk

Next AddressLogic

Step 3: Add & Subtract• R[rd] = R[rs] op R[rt] (addu rd,rs,rt)

– Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields

– ALUctr and RegWr: control logic after decoding the instruction

• … Already defined the register file & ALU

32Result

ALUctr

clk

busW

RegWr

3232

busA

32busB

5 5 5

Rw Ra Rb

32 x 32-bitRegisters

Rs RtRd

ALUop rs rt rd shamt funct

061116212631


04/21/23 15Fall 2010 -- Lecture #26

Agenda

• MIPS-lite• Administrivia• Technology Break• CPU Design

04/21/23 16Fall 2010 -- Lecture #26

Agenda

• MIPS-lite• Administrivia• Technology Break• CPU Design

04/21/23 17Fall 2010 -- Lecture #26

Agenda

• MIPS-lite• Administrivia• Technology Break• CPU Timing

04/21/23 18Fall 2010 -- Lecture #26

Clocking Methodology

• Storage elements clocked by same edge• Flip-flops (FFs) and combinational logic have some delays

– Gates: delay from input change to output change – Signals at FF D input must be stable before active clock edge to allow signal to

travel within the FF (set-up time), and we have the usual clock-to-Q delay• “Critical path” (longest path through logic) determines length of clock

period

04/21/23 Fall 2010 -- Lecture #26 19

Clk

.

.

.

.

.

.

.

.

.

.

.

.

Register-Register Timing: One Complete Cycle

04/21/23 Fall 2010 -- Lecture #26 20

Clk

PCRs, Rt, Rd,Op, Func

ALUctr

Instruction Memory Access Time

Old Value New Value

RegWr Old Value New Value

Delay through Control Logic

busA, BRegister File Access Time

Old Value New Value

busWALU Delay

Old Value New Value

Old Value New Value

New ValueOld Value

Register WriteOccurs Here32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

ALU

5Rd

Logical Operations with Immediate

04/21/23 Fall 2010 -- Lecture #26 21

• R[rt] = R[rs] op ZeroExt[imm16]

op rs rt immediate016212631


immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

ALU

5Rd

But we’re writing to Rt register??

15

Logical Operations with Immediate

04/21/23 Fall 2010 -- Lecture #26 22

• R[rt] = R[rs] op ZeroExt[imm16]



immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

• Already defined 32-bit MUX; Zero Ext?

What about Rt register read??

32

ALUctr

clk

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

Rd

ZeroExt 3216imm16

ALUSrc

01

0

1

ALU5

RegDst

Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]

Example: lw rt,rs,imm16

04/21/23 Fall 2010 -- Lecture #26 23



32

ALUctr

clk

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

Rd

ZeroExt 3216imm16

ALUSrc

01

0

1

ALU

5

RegDst

Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]

Example: lw rt,rs,imm16

04/21/23 Fall 2010 -- Lecture #26 24



32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

ALU 0

1WrEn Adr

DataMemory

5

?

RTL: The Add Instruction

04/21/23 Fall 2010 -- Lecture #26 25

add rd, rs, rt– MEM[PC] Fetch the instruction from memory– R[rd] = R[rs] + R[rt]The actual operation– PC = PC + 4 Calculate the next instruction’s address

op rs rt rd shamt funct061116212631


Instruction Fetch Unit at the Beginning of Add

• Fetch the instruction from Instruction memory: Instruction = MEM[PC]– same for

all instructions

imm16

clk

PC

00

4 nPC_sel

PC Ext

AdderAdder

Mux

Inst Address

InstMemory Instruction<31:0>

04/21/23 26Fall 2010 -- Lecture #26

Single Cycle Datapath during Add

R[rd] = R[rs] + R[rt]

op rs rt rd shamt funct061116212631

32

ALUctr=ADD

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=1

Extender

3216imm16

ALUSrc=0ExtOp=x

MemtoReg=0

clk

Data In32

MemWr=0

zero01

0

1

=

ALU 0

1WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=+4 instrfetchunitclk

04/21/23 27Fall 2010 -- Lecture #26

Instruction Fetch Unit at End of Add• PC = PC + 4– Same for all

instructions except: Branch and Jump

imm16

clk

PC

00

4 nPC_sel=+4

PC Ext

AdderAdder

Mux

Inst Address

InstMemory

04/21/23 28Fall 2010 -- Lecture #26

Single Cycle Datapath during Or Immediateop rs rt immediate

016212631

• R[rt] = R[rs] OR ZeroExt[Imm16]

32

ALUctr=

clk

busW

RegWr=

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=

Extender

3216imm16

ALUSrc=ExtOp=

MemtoReg=

clk

Data In32

MemWr=

zero01

0

1

=

ALU 0

1WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel= instrfetchunitclk

04/21/23 29Fall 2010 -- Lecture #26

04/21/23 Fall 2010 -- Lecture #26 30

• R[rt] = R[rs] OR ZeroExt[Imm16]op rs rt immediate

016212631

Single Cycle Datapath during Or Immediate

32

ALUctr=OR

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=0

Extender

3216imm16

ALUSrc=1ExtOp=zero

MemtoReg=0

clk

Data In32

MemWr=0

zero01

0

1

=

ALU 0

1WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs


Single Cycle Datapath during Load

• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate

016212631

32

ALUctr=

clk

busW

RegWr=

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=

Extender

3216imm16

ALUSrc=ExtOp=

MemtoReg=

clk

Data In32

MemWr=

zero01

0

1

=

ALU 0

1WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel= instrfetchunitclk

04/21/23 31Fall 2010 -- Lecture #26

Single Cycle Datapath during Load

• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate

016212631

32

ALUctr=ADD

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=0

Extender

3216imm16

ALUSrc=1ExtOp=sign

MemtoReg=1

clk

Data In32

MemWr=0

zero01

0

1

=

ALU 0

1WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs


04/21/23 32Fall 2010 -- Lecture #26

Summary: Datapath’s Control Signals• ExtOp: “zero”, “sign”• ALUsrc: 0 regB;

1 immed• ALUctr: “ADD”, “SUB”,

“OR”

• MemWr: 1 write memory• MemtoReg: 0 ALU; 1 Mem• RegDst: 0 “rt”; 1 “rd”• RegWr: 1 write register

04/21/23 Fall 2010 -- Lecture #26 33

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

ALU 0

1WrEn Adr

DataMemory

5

imm16

clk

PC

00

4nPC_sel

PC Ext

AdderAdder

Mux

Inst Address

0

1

cs 61c: great ideas in computer architecture (machine structures) single-cycle processor design

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