cs 362: computer design lecture 8: muxes& …...enable –cont’d •because the decoder will...
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CS 362: Computer DesignLecture 8: Muxes & Decoders
Mitchell TheysUniversity of Illinois at Chicago
September 20, 2018
Digital Logic
• Previously: Established rules of booleanalgebra and digital logic
• Today: Building stuff!
Decoder
• Interprets n inputs (ABC) as a n bit binary number
• Where ABC represents number x, sets output Dx to 1, all other outputs to 0
i0 is 0 and i1 is 1. Which output is 1?
A. y0
B. y1
C. y2
D. y3
E. More than one of the above
i1
i0
y3
y2
y1y0
For n inputs, a decoder will have __ outputs
A. n
B. 2n
C. 4n
D. 2n
E. None of the above
Decoder Truth Table
i1 i0 y0 y1 y2 y3
0 0
0 1
1 0
1 1
i1
i0
y3
y2
y1y0
Creating a Decoder
• Each input sends both its signal, and the inverse of its signal
A D1
D0
Building Decoders
• Each input sends both its signal, and the inverse of its signal
• Signals are ANDedtogether according to the minterm for each output
i1 i0 y0 y1 y2 y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
3‐to‐8 Decoder
3‐to‐8 Decoder, A is our MSB
3‐to‐8 Decoder, B
C corresponds to the lowest order bit for the input. In our 3 bit decoder, if C is 1, we should send 0 to _ and 1 to _
Clicker 0 1
A D0, D1, D2, D3 D4, D5, D6, D7
B D4, D5, D6, D7 D0, D1, D2, D3
C D0, D2, D4, D6 D1, D3, D5, D7
D D1, D3, D5, D7 D0, D2, D4, D6
3‐8 Decoder, C
Enable
• Will one of the outputs of the decoder always have a 1 on the output?– A – Yes– B – No
Enable – cont’d
• Because the decoder will always have an output of 1, we can add an enable to get all outputs to be 0.
i2
i1
y7
y6
y5y4
y3
y2
y1y0
i0
e
Now if e = 0, all outputs will be 0
When e = 1, the device behaves as a decoder
We will add enables to devices whenever we want this type of functionality
Decoder Questions?
Multiplexer
• Select one signal from a group of 2n inputs, to be output on a single output line.
Recall: Datapath
• Anywhere we have multiple inputs, we use a multiplexer
Recall: Datapath
• Anywhere we have multiple inputs, we use a multiplexer
Multiplexer
• Lines D0,…,D7 are the data input lines and F is the output line.
• Lines A, B, and C are called the select lines. They are interpreted as a three bit binary number, which is used to choose one of the D lines to be output on line F.
Multiplexer Truth TableA B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F is d0 if a’b’c’ is 1, else F = 0 is equivalent to
A. f = d0
B. f = a’b’c’d0
C. f = a’b’c + d0
D. None of the above
A B C F
0 0 0 d0
0 0 1 d1
0 1 0 d2
0 1 1 d3
1 0 0 d4
1 0 1 d5
1 1 0 d6
1 1 1 d7
Multiplexor Sum of Minterms
• f = A B C F
0 0 0 d0
0 0 1 d1
0 1 0 d2
0 1 1 d3
1 0 0 d4
1 0 1 d5
1 1 0 d6
1 1 1 d7
What is the correct boolean formula for this multiplexor?
• S is the selector, 1 selects B, 0 selects A
A. c = s(a+ b)
B. c = sa + sb
C. c = s’a + sb
D. None of the above
1‐bit 2 to 1Multiplexor
• c = s’a + sb
Using the values below, what is the value of y?
A. 0
B. 1
s0 s1 i0 i1 i2 i3
0 1 0 1 0 1
Arbitrarily Large Multiplexer
• If there are n data inputs, there will need to be log2n selector inputs.
• The multiplexer consists of– A decoder that generates n signals, each indicating a different control value
– An array of n AND gates, each combining one of the inputs with a signal from the decoder
– A single large OR gate that incorporates the outputs of the AND gates
8 input multiplexor
Scaling Up
• Have to perform combinatorial operations over an entire word (32‐bits) of input.
• Bus: a collection of data lines that is treated together as a single logical signal.
• Example: A multiplexor is used to choose which of the two buses (each 32 bits wide) will be written into the Result register
Replicating a 1‐bit Multiplexer 32 times
Will the Select value be the same for each mux?
A. Yes
B. No
C. It depends
Rapid Prototyping
• Using a decoder, how could we implement F(A,B,C) =∑m(2,3,5)?
i2
i1
y7
y6
y5y4
y3
y2
y1y0
i0
Rapid Prototyping – cont’d
• Using an 8‐to‐1 multiplexor, how could we implement F(A,B,C) =∑m(2,3,5)?
i7
i6
i5i4
i3
i2
i1i0
out
s2 s1 s0
Which of the following values can we put on the input of a multiplexor (or
any device we have discussed)
• A – 1• B – 0 • C – a literal• D – a complemented literal• E – all of the these
Rapid Prototyping – cont’d
• Using a 4‐to‐1 multiplexor, how could we implement F(A,B,C) =∑m(2,3,5)?
i3
i2
i1i0
out
s1 s0
Rapid Prototyping – cont’d
• Using a 4‐to‐1 multiplexor, how could we implement F(A,B,C) =∑m(2,3,5,6)?
i3
i2
i1i0
out
s1 s0