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CS 230: Computer CS 230: Computer Organization and Organization and

Assembly LanguageAssembly LanguageAviral

ShrivastavaDepartment of Computer Science and

EngineeringSchool of Computing and Informatics

Arizona State University

Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

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AnnouncementsAnnouncements• Project 3

– MIPS Assembler

• Midterm– Thursday, Oct 2009

• MIPS ISA and Programming• Function calls and register conventions• Assembling MIPS Instructions• 2’s complement number system• FP number system

• Finals– Tuesday, Dec 08, 2009

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Computer OrganizationComputer Organization

• We have leaned the ISA of the processor till now– Given an algorithm, express it in terms of the processor ISA

Instruction Set Architecture

software

hardware

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High-level language program (in C) swap (int v[], int k) . . .

Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31

Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

Below the ProgramBelow the Program

C - Compiler

Assembler

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Datapath & ControlDatapath & Control• We're ready to look at an implementation of the

MIPS• Simplified to contain only:

– memory-reference instructions: lw, sw – arithmetic-logical instructions: add, sub, and, or,

slt– control flow instructions: beq, j

• Generic implementation:– use the program counter (PC) to supply the

instruction address and fetch the instruction from memory (and update the PC)

– decode the instruction (and read registers)– execute the instruction

• All instructions (except j) use the ALU after reading the registers– Why? memory-reference? arithmetic? control flow?

FetchPC = PC+4

DecodeExec

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Abstract Abstract Implementation ViewImplementation View

• Two types of functional units:– elements that operate on data values (combinational)– elements that contain state (sequential)

• Single cycle operation• Split memory (Harvard) model - one memory for

instructions and one for data

Address Instruction

InstructionMemory

Write Data

Reg Addr

Reg Addr

Reg Addr

Register

File ALU

DataMemory

Address

Write Data

Read DataPC

Read Data

Read Data

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32-bit ALU32-bit ALU

• Supports all the Arithmetic/Logic operations

32

32

32

operation

result

a

b

ALU

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ALU DesignALU Design

+

A1

B1

result1

less

+

A0

B0

result0

less

+

A31

B31

result31

less

. . .

0

0

set

zero

. . .

add/subtop

overflow

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Fetching InstructionsFetching Instructions• Fetching instructions involves

– reading the instruction from the Instruction Memory– updating the PC to hold the address of the next instruction

– PC is updated every cycle, so it does not need an explicit write control signal

– Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal

ReadAddress

Instruction

InstructionMemory

Add

PC

4

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Decoding InstructionsDecoding Instructions

• Decoding instructions involves– sending the fetched instruction’s opcode and function field

bits to the control unit

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ControlUnit

−reading two values from the Register File•Register File addresses are contained in the

instruction

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Executing R Format Executing R Format OperationsOperations

• R format operations (add, sub, slt, and, or)

– perform the indicated (by op and funct) operation on values in rs and rt

– store the result back into the Register File (into location rd)

– Note that Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

overflowzero

ALU controlRegWrite

R-type:

31 25 20 15 5 0

op rs rt rd functshamt

10

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Load and Store Load and Store OperationsOperations

• Load and store operations

– compute a memory address by adding the base register (in rs) to the 16-bit signed offset field in the instruction

• base register was read from the Register File during decode

• offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value

– store value, read from the Register File during decode, must be written to the Data Memory

– load value, read from the Data Memory, must be stored in the Register File

I-Type: op rs rt address offset

31 25 20 15 0

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Load and Store Load and Store OperationsOperations

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

overflowzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

SignExtend

MemWrite

MemRead

16 32

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Executing Branch Executing Branch OperationsOperations

• Branch operations have to

– compare the operands read from the Register File during decode (rs and rt values) for equality (zero ALU output)

– compute the branch target address by adding the updated PC to the sign extended16-bit signed offset field in the instruction• “base register” is the updated PC• offset value in the low order 16 bits of the instruction

must be sign extended to create a 32-bit signed value and then shifted left 2 bits to turn it into a word address

I-Type: op rs rt address offset

31 25 20 15 0

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Executing Branch Executing Branch OperationsOperations

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

zero

ALU control

SignExtend16 32

Shiftleft 2

Add

Branchtargetaddress

(to branch control logic)

Add

4

PC

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Executing Jump Executing Jump OperationsOperations

• Jump operations have to

– replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits

ReadAddress

Instruction

InstructionMemory

Shiftleft 2

Jumpaddress

26

4

28

J-Type: op

31 25 0

jump target address

Add

4

PC

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Adding the pieces Adding the pieces togethertogether

ReadAddress

Instruction

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovfzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

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Multiplexor InsertionMultiplexor Insertion

MemtoReg

ReadAddress

Instruction

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovfzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

ALUSrc

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Clock DistributionClock Distribution

MemtoReg

ReadAddress

Instruction

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovfzero

ALU control

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

ALUSrc

System Clock

clock cycle

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Adding the Branch Adding the Branch PortionPortion

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovfzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

MemtoRegALUSrc

ReadAddress

Instruction

InstructionMemory

Add

PC

4 Shiftleft 2

Add

PCSrc

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26

Adding the Jump Adding the Jump PortionPortion

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovfzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

MemtoRegALUSrc

ReadAddress

Instruction

InstructionMemory

Add

PC

4 Shiftleft 2

Add

PCSrc

0

1Shiftleft 2

Jump

28PC+4[31-28]

32

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26

Instr[25-0]

MIPS Machine (with MIPS Machine (with Controls) Controls)

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

32

PC+4[31-28]

28

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Yoda says…Yoda says…

Use your feelings, Obi-Wan, and find him you will