Roll No.......................

Total No. of Questions : 091

*,'\p*[Total No. of Pages : 02

B.Tech. {Sern. - 3'd)COMPUTER ARCfIITECTURE

SUB.IITCT CODE : CS - 2O1 'Paper ID : [AO451]

lNote : Please lill subject code and paper ID on OMR]

fime : 03 Hours Maximum Marks : 60

Instruction to Candidates:

l) Section - A is Compulsory.

2) Attempt any Four questions from Section - B.

3) Attempt gny T\vo questions from Section - C.

Section - AQI) (10x2 =20)

a) Conveft the following logic function into mintem

ABC,DE, + AB, C,DE, + ABCDE, + AB,CD, E,

b) Define the tems real time computer* progess control computer

c) Give the layered view of a computer system.

d) What is the role of Shift Registers in digital computers?

e) Perform the subtraction with the following unsigned binary number bytaking the 2's compliment of the subkahend

1010100 - 1010100

1) Explain the meaning of the memory - ret'erence instruction STA.

g) What is the difference between miclo program and micro code?

h) What do you mean by software interrupt?

i) How Cache Memory is useful in memory hierarchy?

j) What do you mean by Intemrpt - initiated I/O concept?

Section - B(4x5=20)

Q2). Explain in brief about MIMD machines. ,Q3) Give an overview of CISC Architecture.

J-110 t81291 P,r.o. -

Ql) A computer en.rploys RAM chips of 256 x 8 and ROM chips of 1024 x 8. Thecomputer systelnneeds 2K bytes of R A,M,4K bytes of ROM, and four interfaceunits, each with four registers. A memory - mapped I/O configuration is used.The two highest-order bits of rhe addrEss bus are assigned 00 for RAM, 0lfor ROM, and. 10 for intedace registers. Give the address rlange ir hexadecimaltbr RAM, ROM. and interface.

C5) A DMA controller transfers 16 - bit words ro memory using cycle stealing.The words are assembled from a det ice that transmits characters at a rate of2400 characters per second. The CPU is fetching and executing instxctionsat an average rate of 1 million instructions per second. By how much will the .

CPU be slowed down because of the DMA transfer?

Q6) Discuss the hard.**. t*r*r""J,;:; of division for signed-masritude data.

(2x10=20)

Q7) Explun in detail the main features of at least two perfonnance eyaluationbenchmarks.

Q8) (a) Explain why poor load balancing leads to less-than-linear speedup?(b) A given processor has 32 registers, ir'ses 16-bit immediates, and has 1,12

instructions in its ISA. In a given program, 20% of the instluctions takeone input register and have one outpur register. 30% have two inputregisters and one output registel 257o have one output and one inputregister and take all immediate input as rvell, and the remaining 257rhave one immediate input register,rnh o,.,a ortput r"gister. For each of'the fbur types of instructions, how maly bits are required? Assume thatthe ISA requires th.rt all instrLrctiors be a l-lrltiple of 8 bits in ]ength.

Q9) (a) How does pipelining improve perfonnance'l

(b) What is the lesult of the following operatiors wlten executed on a S,bitprocessor that uses a 2's complement representation for negative integers?

LSH 14, 3

ASH 17..5

LSH 23. -2ASH -23. -2

\

{<>'=+.!2.I-410