CS 152b Final Report

Group 6

BackgroundGroup 6 staff

The R2-Yu2 processorRandy Grant – Technical leadRobert Johnson – VHDL masterAnthony (moo) Yu – Datapath guruGeorge Yu – Software designer

Our goal was to design and implement a functional 16-bit RISC processor using the Xilinx software. The constrains on our chip design was that it must be able to run on a Xess board and must adhere to the standards specified by our primary customer Young Cho Enterprises out of UCLA.

Instruction Set Architecture

R-Type Instructions

I-Type InstructionsJ-Type Instructions

No Op Instruction

PipelineInstruction Read

Instruction Decode

ALU

Memory

Register Write Back

Instruction Cache

Multiplexor selects proper cache entry for controller

32 Word Direct Mapped Cache Instructions are read-only, so no

write-back or write-through schemes are needed

Each cache entry has 1 bit valid flag, 11 bits tag, 16 bits data

Cache Controller processes hits and misses

Demuxliplexor sets write signal for each cache entry (Max one bit high)

28 bit registers store cache entries

Implemented in structural and behavioral VHDL

Instruction Cache

Cache integration with datapathMemory accesses and cache lookups done in parallel

On a hit, the next instruction comes from the cache

On a miss, the next instruction comes from memory and is also pulled into the cache

Given more time, we would further modify the integration of the cache with the datapath to increase the benefit of the cache addition

Instruction CacheStalling the

PipelineHold the PC value by feeding a zero increment       

Allow any JMP or BEQ instructions to alter it-send NOPs through the pipeline

Resume normal execution once hit goes high

Typical CompilerScanner Takes in input file and tokenizes the input

Parser Transforms token stream into a grammatical phrases

Code Generation Creates assembly code from the grammar

Linker Turns the assembly code into the native bit code of the computer

Our Compiler Solution

Implemented a stack for embedded structures

Combined parsing and scanning into a single array of struct (tokenlist), which stored all the tokens

Implementing a StackInitial state of the

memoryPush registersw r1, 51(r0)

sw r2, 52(r0)

sw r3, 53(r0)

sw r4, 54(r0)

sw r5, 55(r0)

sw r6, 56(r0)

sw r7, 57(r0)

Heapstart = Heapstart + 7

Pop Registerlw r7, 57(r0)

lw r6, 56(r0)

lw r5, 55(r0)

lw r4, 54(r0)

lw r3, 53(r0)

lw r2, 52(r0)

lw r1, 51(r0)

Heapstart = Heapstart - 7

Our Compiler Design

addi r1, r0, 0

addi r2, r0, 48

addi r3, r0, 1

L3: sw r1, 51(r0)

sw r2, 52(r0)

sw r3, 53(r0)

sw r4, 54(r0)

sw r5, 55(r0)

sw r6, 56(r0)

sw r7, 57(r0)

lw r4, 51(r0)

add r1, r0, r4

addi r2, r0, 49

addi r3, r0, 1

L4: sw r1, 59(r0)

sw r2, 60(r0)

sw r3, 61(r0)

sw r4, 62(r0)

sw r5, 63(r0)

sw r6, 64(r0)

sw r7, 65(r0)

lw r5, 0(r3)

lw r6, 0(r4)

slt r7, r6, r5

beq r7, r0, L5

sw r1, 66(r0)

sw r2, 67(r0)

sw r3, 68(r0)

sw r4, 69(r0)

sw r5, 70(r0)

sw r6, 71(r0)

sw r7, 72(r0)

sw r5, 50(r0)

add r5, r6, r0

sw r5, 0(r3)

lw r6, 50(r0)

sw r6, 0(r4)

lw r7, 72(r0) L5: lw r7, 65(r0)

lw r6, 71(r0) lw r6, 64(r0)

lw r5, 70(r0) lw r5, 63(r0)

lw r4, 69(r0) lw r4, 62(r0)

lw r3, 68(r0) lw r3, 61(r0)

lw r2, 67(r0) lw r2, 60(r0)

lw r1, 66(r0) lw r1, 59(r0)

beq r2, r1, L6 jmp L4

add r1, r1, r3

L6: lw r7, 57(r0)

lw r6, 56(r0)

lw r5, 55(r0)

lw r2, 52(r0)

lw r1, 51(r0)

beq r2, r1, L7

add r1, r1, r3

jmp L3

L7: hlt

Conclusion

In Conclusion the Group 6 16-bit RISC Processor Meets and

Exceeds Design Requirements!

ReferencesCache ReferenceComputer Organization & Design The Hardware/Software Interface by Patterson & Hennessy

VHDL Referencehttp://www.ee.ucla.edu/~young/csm152b/vhdl_comp.pdf

Compiler Referencehttp://cs.wisc.edu/~bodik/cs536/Notes/1.Overview.html

Thank YouFor viewing this presentation you qualify for Group 6’s special offerFor a limited time only you can get a copy of the Group 6 processor schematic for only $999.95

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