9/29/2016 CS152,Fall2016

CS152ComputerArchitectureandEngineering

Lecture 9- VirtualMemory

JohnWawrzynekElectricalEngineeringandComputerSciences

UniversityofCaliforniaatBerkeley

http://www.eecs.berkeley.edu/~johnwhttp://inst.eecs.berkeley.edu/~cs152

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LasttimeinLecture8

§ Protectionandtranslationrequiredformultiprogramming– Baseandboundswasearlysimplescheme

§ Page-basedtranslationandprotectionavoidsneedformemorycompaction,easyallocationbyOS– Butneedtoindirect inlargepagetableoneveryaccess

§ Addressspacesaccessedsparsely– Canusemulti-level pagetabletoholdtranslation/protectioninformation,butimpliesmultiplememoryaccesses perreference

§ Addressspaceaccesswithlocality– Canuse“translation lookasidebuffer”(TLB)tocacheaddresstranslations(sometimes knownas“addresstranslationcache”)

– StillhavetowalkpagetablesonTLBmiss,canbehardwareorsoftwaretalk

§ VirtualmemoryusesDRAMasa“cache”ofdiskmemory,allowsverycheapmainmemory

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MemoryManagement

§ Canseparateintoorthogonalfunctions:– Translation(mappingofvirtualaddresstophysicaladdress)– Protection(permissiontoaccesswordinmemory)– Virtualmemory(transparentextensionofmemoryspaceusingslowerdiskorflashstorage)

§ Butmostmodernsystemsprovidesupportforalltheabovefunctionswithasinglepage-basedsystem

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ModernVirtualMemorySystemsIllusionofalarge,private,uniformstore

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Protection&Privacyseveralusers,eachwiththeirprivateaddressspaceandoneormoresharedaddressspaces

pagetable≡ namespace

DemandPagingProvidestheabilitytorunprogramslargerthantheprimarymemory

Hidesdifferences inmachineconfigurations

Thepriceisaddresstranslationoneachmemoryreference

OS

useri

PrimaryMemory

SecondaryStorage

VA PAmappingTLB

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HierarchicalPageTable

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Level1PageTable

Level2PageTables

DataPages

pageinprimarymemorypageinsecondarymemory

RootofCurrentPageTable

p1

offset

p2

VirtualAddress

(ProcessorRegister)

PTEofanonexistentpage

p1 p2 offset01112212231

10-bitL1index

10-bitL2index

PhysicalM

emory

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Page-BasedVirtual-MemoryMachine(HardwarePage-TableWalk)

§ Assumespagetablesheldinuntranslated physicalmemory

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PCInst.TLB

Inst.Cache D Decode E M

DataCache W+

PageFault?

Protectionviolation?PageFault?

Protectionviolation?

DataTLB

MainMemory(DRAM)

MemoryControllerPhysicalAddress

PhysicalAddress

PhysicalAddress

PhysicalAddress

Page-TableBaseRegister

VirtualAddress Physical

Address

VirtualAddress

HardwarePageTableWalker

Miss? Miss?

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AddressTranslation:puttingitalltogether

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VirtualAddress

TLBLookup

PageTableWalk

UpdateTLBPageFault(OSloadspage)

ProtectionCheck

PhysicalAddress(tocache)

miss hit

thepageis∉ memory ∈ memory denied permitted

ProtectionFault

hardwarehardwareorsoftwaresoftware

SEGFAULTWhere?

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PageFaultHandler

§WhenthereferencedpageisnotinDRAM:– Themissingpageislocated(orcreated)– Itisbroughtinfromdisk,andpagetableisupdated

• AnotherjobmayberunontheCPUwhilethefirstjobwaitsfortherequested pagetobereadfromdisk

– Ifnofreepagesareleft,apageisswappedout• LRUorPseudo-LRUreplacementpolicy,implemented insoftware

§ Sinceittakesalongtimetotransferapage(msecs),pagefaultsarehandledcompletelyinsoftwarebytheOS– Untranslated addressingmodeisessential toallowkerneltoaccesspagetables

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HandlingVM-relatedexceptions

§ HandlingaTLBmissneedsahardwareorsoftwaremechanismtorefillTLB

§ Handlingapagefault(e.g.,pageisondisk)needsarestartableexceptionsosoftwarehandlercanresumeafterretrievingpage– Preciseexceptionsareeasytorestart– Canbeimprecisebutrestartable, butthiscomplicatesOSsoftware

§ Handlingaprotectionviolationmayabortprocess

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PCInstTLB

Inst.Cache D Decode E M

DataTLB

DataCache W+

TLBmiss?PageFault?Protectionviolation?

TLBmiss?PageFault?Protectionviolation?

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AddressTranslationinCPUPipeline

§NeedtocopewithadditionallatencyofTLB:– slowdowntheclock?– pipelinetheTLBandcacheaccess?– virtualaddresscaches?– parallelTLB/cacheaccess?

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PCInstTLB

Inst.Cache D Decode E M

DataTLB

DataCache W+

TLBmiss?PageFault?Protectionviolation?

TLBmiss?PageFault?Protectionviolation?

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Virtual-AddressCaches

§ one-stepprocessincaseofahit(+)§ cacheneeds tobeflushedonacontextswitchunlessaddress space

identifiers (ASIDs)includedintags(-)§ aliasingproblemsduetothesharingofpages(-)§ maintainingcachecoherence (-) (see laterincourse)

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CPU PhysicalCacheTLB Primary

MemoryVA PA PA

Alternative: place the cache before the TLB

CPUVA (StrongARM)Virtual

CachePA

TLBPrimaryMemoryVA

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VirtuallyAddressedCache(VirtualIndex/VirtualTag)

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PC

Inst. TLB

Inst.Cache D Decode E M Data

Cache W+

DataTLB

MainMemory(DRAM)

MemoryControllerPhysicalAddress

InstructiondataPhysicalAddress

PhysicalAddress

Page-Table Base Register

VirtualAddress

VirtualAddress

HardwarePageTableWalker

Miss?Miss?

Translate on miss

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AliasinginVirtual-AddressCaches

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VA1

VA2

PageTables

DataPages

PA

VA1

VA2

1stCopyofDataatPA

2ndCopyofDataatPA

Tag Data

Two virtual pages share one physical page

Virtualcachewouldhavetwocopiesofsamephysicaldata.Writestoonecopynotvisibletoreadsofother!

GeneralSolution: Preventaliasescoexisting incache

Software(i.e.,OS)solutionfordirect-mapped cache

VAsofsharedpagesmustagreeincacheindexbits;thisensuresallVAsaccessingsamePAwillconflictindirect-mappedcache(earlySPARCs)

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ConcurrentAccesstoTLB&Cache(VirtualIndex/PhysicalTag)

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Index LisavailablewithoutconsultingtheTLB⇒ cacheandTLBaccessescanbeginsimultaneously!

TagcomparisonismadeafterbothaccessesarecompletedCases: L+b =k,L+b <k,L+b >k

VPN Lb

TLB Direct-mapCache2L blocks

2b-byteblockPPNPageOffset

=hit? DataPhysicalTag

Tag

VA

PA

Index

k

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Virtual-IndexPhysical-TagCaches:AssociativeOrganization

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Howdoesthisschemescaletolargercaches?

VPN aL=k-b b

TLB Direct-map2L blocks

PPN PageOffset=

hit?

Data

Phy.Tag

Tag

VA

PA

Index

kDirect-map2L blocks

2a

=2a

Afterthe PPN isknown,2a physicaltagsarecompared

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ConcurrentAccesstoTLB&LargeL1TheproblemwithL1>Pagesize

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Can VA1 and VA2 bothmapto samePA?

VPN aPageOffset b

TLB

PPN PageOffset b

Tag

VA

PA

VirtualIndexL1PAcacheDirect-map

= hit?

PPNa Data

PPNa DataVA1

VA2

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CS152Administrivia

§PS2andLab2outdueTuesday§Quiz2,NextThursdayOct6th

– Lectures6-9,PS2,Lab2,readings

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AsolutionviaSecondLevelCache

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UsuallyacommonL2cachebacksupbothInstructionandDataL1caches

L2is“inclusive”ofbothInstructionandDatacaches• InclusivemeansL2hascopyofanylineineitherL1

CPUL1DataCache

L1InstructionCache UnifiedL2

CacheRF Memory

MemoryMemoryMemory

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Anti-AliasingUsingL2 [MIPSR10000,1996]

§ L2stores the“a”bitsforL1residents.§ SupposeVA1andVA2bothmaptoPAandVA1is

alreadyinL1,L2(VA1≠ VA2)§ AfterVA2isresolved toPA,acollisionwillbe

detected inL2.§ VA1willbepurgedfromL1andL2,andVA2willbe

loaded⇒ noaliasing!19

VPN aPageOffset b

TLB

PPN PageOffset b

Tag

VA

PA

VirtualIndexL1PAcacheDirect-map

= hit?

PPNa Data

PPNa Data

VA1

VA2

Direct-Mapped L2

PAa1 Data

PPN

intoL2tag

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Anti-AliasingusingL2foraVirtuallyAddressedL1

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VPN PageOffset b

TLB

PPN PageOffset b

Tag

VA

PA

VirtualIndex&Tag

PhysicalIndex&Tag

L1VACache

L2PACacheL2“contains”L1

PAVA1 Data

VA1 Data

VA2 Data

“VirtualTag”

Physically-addressedL2canalsobeusedtoavoidaliasesinvirtually-addressedL1

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AtlasRevisited

§ OnePhysicalAddressRegister(PAR)foreachphysicalpage

§ PAR’scontaintheVPN’softhepagesresidentinprimarymemory

§ Advantage:Thesizeisproportional tothesizeoftheprimarymemory

§ Whatisthedisadvantage?– Lookupissloworexpensive

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VPN

PAR’s

PPN

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PowerPC:HashedPageTable(”InvertedPageTable”)

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§ Eachhashtableslothas8PTE's<VPN,PPN> thataresearchedsequentially

§ Ifthefirsthashslotfails,analternate hashfunctionisusedtolookinanotherslot

Allthesestepsaredoneinhardware!§ HashedTableistypically2to3timeslargerthan

thenumberofphysicalpages§ ThefullbackupPageTableismanaged insoftware

BaseofTable

hashOffset + PAofSlot

PrimaryMemory

VPNPPN

PageTableVPN d 80-bitVA

VPN

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VMfeaturestrackhistoricaluses:§ Baremachine,onlyphysicaladdresses

– Oneprogramownedentiremachine§ Batch-stylemultiprogramming

– SeveralprogramssharingCPUwhilewaitingforI/O– Base&bound:translationandprotectionbetweenprograms(supportsswapping entireprogramsbutnotdemand-pagedvirtualmemory)

– Problemwithexternal fragmentation(holes inmemory),neededoccasionalmemorydefragmentation asnewjobsarrived

§ Timesharing– Moreinteractiveprograms,waitingforuser.Also,morejobs/second.– Motivatedmovetofixed-sizepagetranslationandprotection,noexternalfragmentation(butnowinternal fragmentation,wastedbytesinpage)

– Motivatedadoptionofvirtualmemorytoallowmorejobstosharelimitedphysicalmemoryresourceswhileholdingworkingsetinmemory

§ VirtualMachineMonitors– Runmultipleoperatingsystems ononemachine– Ideafrom1970sIBMmainframes,nowcommononlaptops

• e.g.,runWindowsontopofMacOSX– Hardwaresupportfortwolevelsoftranslation/protection

• GuestOSvirtual->GuestOSphysical->Hostmachinephysical

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VirtualMemoryUseToday- 1

§ Servers/desktops/laptops/smartphones havefulldemand-pagedvirtualmemory– Portabilitybetweenmachineswithdifferentmemorysizes– Protectionbetweenmultiple usersormultipletasks– Sharesmallphysicalmemoryamongactivetasks– Simplifies implementation ofsomeOSfeatures

§ Vectorsupercomputershavetranslationandprotectionbutrarelycompletedemand-paging

§ (OlderCrays:base&bound, Japanese&CrayX1/X2:pages)– Don’twasteexpensiveCPUtimethrashingtodisk(makejobsfitinmemory)– Mostlyruninbatchmode(runsetofjobsthatfitsinmemory)– Difficulttoimplement restartable vectorinstructions

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VirtualMemoryUseToday- 2

§ MostembeddedprocessorsandDSPsprovidephysicaladdressingonly– Can’taffordarea/speed/power budgetforvirtualmemorysupport– Oftenthereisnosecondarystoragetoswapto!– Programscustomwrittenforparticularmemoryconfigurationinproduct– Difficulttoimplement restartable instructionsforexposedarchitectures

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Acknowledgements

§ Theseslidescontainmaterialdeveloped andcopyrightby:– Arvind(MIT)– KrsteAsanovic(MIT/UCB)– JoelEmer(Intel/MIT)– JamesHoe(CMU)– JohnKubiatowicz(UCB)– DavidPatterson(UCB)

§ MITmaterialderivedfromcourse6.823§ UCBmaterialderivedfromcourseCS252

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