cs 140 lecture 9 sequential networks
DESCRIPTION
CS 140 Lecture 9 Sequential Networks. Professor CK Cheng CSE Dept. UC San Diego. Sequential Networks. Combinational. D. B. C. A. CLK. CLK. Components F-Fs Specification Implementation: Excitation Table. Specification. Finite State Machine: Input Output Relation State Diagram - PowerPoint PPT PresentationTRANSCRIPT
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CS 140 Lecture 9Sequential Networks
Professor CK Cheng
CSE Dept.
UC San Diego
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Combinational
CLK CLK
A B C D
Sequential Networks
1. Components F-Fs2. Specification3. Implementation: Excitation Table
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Specification
• Finite State Machine: – Input Output Relation– State Diagram– State Table
• Circuit: – Logic Diagram– Netlist– Boolean Expression
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Netlist State Table State Diagram Input Output Relation
y(t) = Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)Q1(t)Q1(t+1) = D1(t) = x(t) + Q0(t)
xQ0
Q1
DQ
Q’
DQ
Q’
y
Q1
Q0
D1
D0
Clk
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Netlist State Table State Diagram Input Output Relation
xQ0
Q1
DQ
Q’
DQ
Q’
y
Q1
Q0
D1
D0
y(t) = Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)Q1(t)Q1(t+1) = D1(t) = x(t) + Q0(t)
Clk
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State table
0 0 0 11 01 1
PSinput
x=0 x=1
00, 0 10, 010, 0 10, 000, 0 11, 010, 1 11, 1
Q1(t) Q0(t) Q1(t+1) Q0(t+1), y(t)
S0
S1
S2
S3
PSinput
x=0 x=1
S0, 0 S2, 0S2, 0 S2, 0S0, 0 S3, 0S2, 1 S3, 1
Let:S0 = 00S1 = 01S2 = 10S3 = 11
Remake the state table using symbols instead of binary code , e.g. ’00’
y(t) = Q1(t) Q0(t)Q0(t+1) = D0(t) = x(t) Q1(t)Q1(t+1) = D1(t) = x(t) + Q0(t)
Logic Diagram => State Table
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State Table => State Diagram
Example: Output sequence
S0
S1
S2
S3
PSinput
x=0 x=1
S0, 0 S2, 0S2, 0 S2, 0S0, 0 S3, 0S2, 1 S3, 1
x/y
S1 S2 S3S0
0,1/0 1/0
0/11/0
0/00/0
1/1
Time 0 1 2 3 4 5
Input 0 1 1 0 1 -
State S0 S0 S2 S3 S2 S3
Output 0 0 0 1 0 1
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y(t) = Q1(t)Q0(t)Q0(t+1) = T0(t) = x(t) Q1(t)Q1(t+1) = T1(t) = x(t) + Q0(t)
X
TQ
Q’
TQ
Q’
y
Q0
Q1
T0
T1
Example with T Flip-Flops
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Logic Diagram => Excitation Table => State Table
y(t) = Q1(t)Q0(t)T0(t) = x(t) Q1(t)T1(t) = x(t) + Q0(t)Q0(t+1) = T0(t) Q’0(t)+T’0(t)Q0(t)Q1(t+1) = T1(t) Q’1(t)+T’1(t)Q1(t)
id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y
0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0 0
2 0 1 0 1 0 1 1 0
3 0 1 1 1 0 1 1 0
4 1 0 0 0 0 1 0 0
5 1 0 1 1 1 0 1 0
6 1 1 0 1 0 0 1 1
7 1 1 1 1 1 0 0 1
Excitation Table
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id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y
0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0 0
2 0 1 0 1 0 1 1 0
3 0 1 1 1 0 1 1 0
4 1 0 0 0 0 1 0 0
5 1 0 1 1 1 0 1 0
6 1 1 0 1 0 0 1 1
7 1 1 1 1 1 0 0 1
Excitation Table =>State Table => State Diagram
0/0
S0 S1 S3
S2
0/0
1/1
0/1
0, 1/01/0
1/0
PS\Input X=0 X=1
S0 S0,0 S2,0
S1 S3,0 S3,0
S2 S2,0 S1,0
S3 S1,1 S0,1
State AssignmentS0 00S1 01S2 10S3 11
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Excitation Table =>State Table => State Diagram
0/0
S0 S1 S3
S2
0/0
1/1
0/1
0, 1/01/0
1/0
PS\Input X=0 X=1
S0 S0,0 S2,0
S1 S3,0 S3,0
S2 S2,0 S1,0
S3 S1,0 S0,1
Time 0 1 2 3 4 5
Input 0 1 1 0 1 -
State S0 S0 S2 S1 S3 S0
Output 0 0 0 0 1 0
Example: Output sequence
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Implementation: State Diagram => State Table => Netlist
Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.
S1S0a/0
b/0
a/0
b/1
S2a/0
b/0
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State Diagram => State Table with State Assignment
State AssignmentS0: 00S1: 01S2: 10
PS\x a b
S0 S1,0 S0,0
S1 S2,0 S0,0
S2 S2,0 S0,1
PS\x 0 1
00 01,0 00,0
01 10,0 00,0
10 10,0 00,1
Q1(t+1)Q0(t+1), ya 0b 1
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State Table => Excitation Table
PS\x 0 1
00 01,0 00,0
01 10,0 00,0
10 10,0 00,1
id Q1Q0x D1D0 y
0 000 01 0
1 001 00 0
2 010 10 0
3 011 00 0
4 100 10 0
5 101 00 1
6 110 -- -
7 111 -- -
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0 2 6 4
1 3 7 5
x(t)
Q1
0 1 - 1
0 0 - 0
Q0D1(t):
D1(t) = x’Q0 + x’Q1
D0 (t)= Q’1Q’0 x’y= Q1x
id Q1Q0x D1D0 y
0 000 01 0
1 001 00 0
2 010 10 0
3 011 00 0
4 100 10 0
5 101 00 1
6 110 -- -
7 111 -- -
Excitation Table => Boolean Expression
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DQ
Q’
DQ
Q’
Q1
Q0
D1
D0
Q0
Q1
x’
D1(t) = x’Q0 + x’Q1
D0 (t)= Q’1Q’0 x’y= Q1x
x
y
Q’1
Q’0x’
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Canonical Form: Mealy and Moore Machines
Combinational Logic
x(t) y(t)
CLK
C2
C1
y(t)
CLK
x(t)
C1 C2
CLK
x(t)
y(t)
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Moore Machine: yi(t) = fi(X(t), S(t))Mealy Machine: yi(t) = fi(S(t))
si(t+1) = gi(X(t), S(t))
C1 C2
CLK
x(t)
y(t)
Mealy Machine
C1 C2
CLK
x(t) y(t)
Moore Machine
s(t) s(t)
Canonical Form: Mealy and Moore Machines
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Finite State Machine Example
• Traffic light controller– Traffic sensors: TA, TB (TRUE when there’s traffic)
– Lights: LA, LB
TA
LA
TA
LB
TB
TB
LA
LB
Academic Ave.B
rava
do
Blv
d.
Dorms
Fields
DiningHall
Labs
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FSM Black Box
• Inputs: CLK, Reset, TA, TB
• Outputs: LA, LB
TA
TB
LA
LB
CLK
Reset
TrafficLight
Controller
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FSM State Transition Diagram
• Moore FSM: outputs labeled in each state• States: Circles• Transitions: Arcs
S0LA: greenLB: red
Reset
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FSM State Transition Diagram
• Moore FSM: outputs labeled in each state• States: Circles• Transitions: Arcs
S0LA: greenLB: red
S1LA: yellowLB: red
S3LA: redLB: yellow
S2LA: redLB: green
TATA
TB
TB
Reset
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FSM State Transition Table
PS Inputs NS
TA TB
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S2 X 1 S2
S3 X X S0
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State Transition TablePS Inputs NS
Q1(t) Q0(t) TA TB Q1(t +1) Q0(t +1)
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
1 0 X 1 1 0
1 1 X X 0 0
State Encoding
S0 00
S1 01
S2 10
S3 11
Q1(t+1)= Q1(t) Q0(t)
Q0(t+1)= Q’1(t)Q’0(t)T’A + Q1(t)Q’0(t)T’B
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FSM Output TablePS Outputs
Q1 Q0 LA1 LA0 LB1 LB0
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0
1 1 1 0 0 1
Output Encoding
green 00
yellow 01
red 10
LA1 = Q1
LA0 = Q’1Q0
LB1 = Q’1
LB0 = Q1Q0
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FSM Schematic: State Register
S1
S0
S'1
S'0
CLK
state register
Reset
r
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Logic Diagram
S1
S0
S'1
S'0
CLK
next state logic state register
Reset
TA
TB
inputs
S1 S0
r
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FSM Schematic: Output Logic
S1
S0
S'1
S'0
CLK
next state logic output logicstate register
Reset
LA1
LB1
LB0
LA0
TA
TB
inputs outputs
S1 S0
r