crossbar architecture for nvm last - politecnico di milanocorsi.dei.polimi.it/ess/nvm/nvm_5a.pdf ·...

Crossbar architecture for Non-Volatile Memories

Andrea Redaelli

Copyright © 2008 Numonyx B.V.

Outline

• Why 3D approaches (literature review) ?

• The crossbar concept

– The “self-selected” resistive cross bar array– The diode selected array: the PCM example– Other biasing schemes

• System issues

– Possible applications for cross-bar– The cross-bar architecture (e. g., NiO storage)

• Conclusions


Market trends

$0

$10.000

$20.000

$30.000

$40.000

$50.000

$60.000

$70.000

$80.000

2007 2008 2009 2010 2011 2012

DRAM

NAND

NOREEPROM

$0

$10.000

$20.000

$30.000

$40.000

$50.000

$60.000

$70.000

$80.000

2007 2008 2009 2010 2011 2012

DRAM

NAND

NOREEPROM

� Non volatile Memory market is fast increasing market with largeexpected revenues.

� Scaling of conventional approaches are featuring fundamentallimitations


Why 3D stacking?

� 3D stacking allows cost reduction without cell geometrical scaling


Crossbar early works: the OTP

S.B. Herner, Matrix Semicon., IEEE Electr. Dev. Lett.,

2004

Polysilicon diodes – process temperatures: 540°C-750°C

S.B. Herner, Matrix Semicon., IEEE Electr. Dev. Lett.,

2004

Polysilicon diodes – process temperatures: 540°C-750°C

M. Johnson et al., Matrix Semicon., IEEE

J. of Solid-State Circuits, 2003

M. Johnson et al., Matrix Semicon., IEEE

J. of Solid-State Circuits, 2003

S. Moller et al, Princeton

Univ., Nature 2003

S. Moller et al, Princeton

Univ., Nature 2003

� Simple scheme employing ananti-fuse as storage element.

� A diode required to select thestorage element.


Crossbar for Oxide-Based RRAM

M-J Lee et al, Samsung, IEDM 2007M-J Lee et al, Samsung, IEDM 2007

M-J Lee et al, Samsung, Adv. Funct. Mat. 2009M-J Lee et al, Samsung, Adv. Funct. Mat. 2009

Ion~2·104 A/cm2

Ion/Ioff ~103

η=2

Ion~2·104 A/cm2

Ion/Ioff ~103

η=2


Latest results: Crossbar with PCM

�Selection through a threshold chalcogenide-based not rectifying element: OTS

�Sensing biasing above the OTS threshold but below the OUM one

�Programming above the OTS+OUM thresholds

Y. Sasago et al., Hitachi,

Symposium on VLSI

Technology, 2009

Y. Sasago et al., Hitachi,

Symposium on VLSI

Technology, 2009

K. DerChang et al.,

Intel-Numonyx,

IEDM, 2009

K. DerChang et al.,

Intel-Numonyx,

IEDM, 2009

�Selection through a polysilicon diode

�PCM till created after diode fabrication

�Good diode driving current capability


Outline




• Feasibility issues


• Conclusions


The memory array

Memory cell

� Main array: storage� Circuitry: read and write/erase operation� Read current to the sense amplifier trough the column


Cross-point array (CPA)

Bottom electrode

Top electrode

Selecting and storage layers

� Each cell is located between two metal lines. Very small cell size 4F2 for layer

� If the right material is found only 2 mask steps are required, resulting in a very simple process. Usual processes employ more masks (3/4)


Cross section view

�2/3 metal levels to manage circuitry�W contact to connect silicon with

metals and circuitry metals with array metal

� CMOS on STD silicon

Dielectric material cover the CMOS

Stacked memory layers2 metals for each layer

Cells are fully integrated in the BEOL �No silicon contamination issues

DielectricsW contacts

Cu Metals for Circuitry

Cu Metals Bottom

Cu Metals Top

Sto

rage


Array architecture

Diode

Storageelement

V

1

Vd

d

V

1

V

20

V

2

� To ensure a reasonable yield, the maximum number of critical masks should be minimized (r P=rSL

N). Interconnection complexity exponentiallyrises with number of stacked layers (loss of array efficiency). Two stacked layers are considered feasible. Three-f our layers areconsidered challenging

2048 rows

2048 columns

N layers

1D/1R scheme


Advantages of the crossbar scheme

� Minimum device area can be achieved: 4F2

� Very simple process flow with reduced mask number

� No issues for silicon contamination

� Maximum array efficiency can be achieved: η=Aarray/ (Aarray U Acircuitry)=1

� More memory device can be stacked in a 3D array, further reducing the effective cell size: 4/nF2


Outline




• System issues


• Conclusions


Resistive cross-point V/2 readout scheme

N row

s

M columns

0 V

0 V0 V-V/20 V0 V0 V

0 V 0 V V/2 0 V0 V

(N-1) x I(V/2) << I(V)

The ideal following condition should be verified:

Strongly non-linearcharacteristic needed !!!

(N-1) x I(V/2) < 0.1I(V)

The practical condition is:

Trade off between sensing and technology

-V/2

V/2

GND

GND


Resistive cross-point programming scheme

N r

ows

M columns

0 V

0 V0 V

-Vp/20 V0 V0 V

0V Vp/2 0V 0V 0V

SETthreshold

RESETthreshold

-Vp/2 Vp/2 Vp-Vp

Program/erase mustbe a threshold mechanism

0V


Sensed current � Isense=I(V)+(N-1)I(V/2)=Ion+(N-1)x0 if “1”=Ioff+(N-1)x0 if “0

Assumptions: 1) Symmetric characteristic

2) |Vp| “0”�”1” and “1”� “0” almost equal (bipolar switching)

N r

ows

M columns

0 V

0 V0 V

-Vp/20 V0 V0 V

0 V Vp/2 0 V0 V

Program � Vprog=Vp & Vdisturb=±Vp/2

I

V

VpVp/2

VreadVread/2 Program region

Ion

Ioff=0

Iprog

Vth0

Vth1

Ideal Crossbar array


0.0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 1.4V0nA

30nA

60nA

90nA

120nA

150nA

180nA

210nA

240nA

270nA

300nA

330nA

360nA

I(on)

I(off)

E. Lortscher, J. W. Ciszek, J. Tour, H. Riel: Reversible and Controllable Switching of a Single-Molecule Junction, Small 2, No. 8-9, 973 (2006)

Sense current of n x n crossbar

I

V0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

(µA)

10x10 OFF

50x50 ON

50x50 OFF

10x10 ON

100x100 ON

100x100 OFF

(Volts)

19

Sensed current � Isense=I(V)+(N-1)I(V/2)=Ion(V)+(N-1)/2xIon(V/2) if “1”

=Ioff(V)+(N-1)/2xIon(V/2) if “0

Ioff != 0

Absolute window: W=Ion(V)-Ioff(V) but design margins not acceptable

Read crossbar array: an example

Simulation from Prof. Paolo Lugli, TUM, EU funded VERSATILE Project


� The storage element itself displays strongly non linear characteristics suitable to selection purpose

nowadays no working storage materials

� 1D/1R scheme must be adopted. A selecting element is required:

• A rectifying element as a diode (A)

• A symmetric element (B)

Voltage

Current

Voltage

Current

(A) (B)

Solution: the selecting element


1T/1R Proposed Alternatives� Chalcogenide

� GST and other phase-change alloys� AgGeSe, AgGeS, WO 3 and SiO 2 solid electrolyte

� Binary oxide

� Nb2O5, Al 2O3, Ta2O5, TiO2, ZrOx , CuxO and NiO

� Oxides with perovskite structure

� SrZrO3, doped- SrTiO 3, Pb(Zr xTi1-x)O3 and Pr0.7Ca0.3 MnO3

� Conductive organics

� Bengala Rose, AlQ 3Ag, Cu-TCNQ A. Chen et al. , IEDM Tech. Dig. 2005

M. Kozicki, EPCOS 2006


Emerging memories swithing

Same or opposite polarity

Pt

Colossal Magneto-Resistive (CMR)

material as Pr0.7Ca0.3MnO3

(PCMO)

Resistive RAM (RRAM)


Noble metals (as Pt)

Transition Metal Oxides (NiO)

Oxide Resistive RAM (OxRRAM)

Opposite polarity

Ag or Cu/Ni, Cu/WAg33Ge20Se47, WO3

Programmable Metallization Cell (PMC)


TiN or TaNGe2Sb2Te5Phase Change Memory (PCM)

Opposite polarity

Cu/AlCuTCNQ, BengalaRose

Organic

Electrode Materials

Programming Voltage

TypicalMaterialMemory Type

Emerging memories must be compliant with a rectifying or symmetric decoding scheme


Outline




• System issues


• Conclusions


Resistive/PCM selection approaches

Stand alone, high density

Innovative

Smaller (~5-8F2)

Dedicated steps for the BJT integration

BJT/diode

Stand alone, very high densityEmbedded memoryApplication

Schematic Cell Structure Cross-section

Memory Array Organization

Cell Size

Process Complexity

BreakthroughConventional

Smaller (~4F2/n)Larger (~20 - 30F2)

Simpler processNo mask overhead for the selector

Diode BEOLMOSFET

n+n+p-substrate

STI

WL

BL

GND

n+n+p-substrate

STI

WL

BL

GND

p-substraten-wellp+

BL

WL

n+

p-substraten-wellp+

BL

WL

n+


PCM Array Layout and Section

• Cell is 104nm x 104nm: 0.0108 µm2

– 52nm x 52nm BJT selectors

– base contact shared by 4 Emitters

– effective cell area is 0.015 µm2

G. Servalli, IEDM 2009


• Dual crossed STI for BJT array definition– 270nm STI for wordlines (BJT bases)

– 140nm STI for BJT emitters and base contact region

– thin CoSi2 over BJT emitters junctions

BJT selector array


• Dual crossed STI for BJT array definition– 270nm STI for wordlines (BJT bases)

– 140nm STI for BJT emitters and base contact region

– thin CoSi2 over BJT emitters junctions

BJT selector array

p-implant

n-implant

base

emitters

emitters

Bases (WLs)

Common collector


x-WL equivalent electric circuit

M2 WL

M1 BL1 M1 BL2 M1 BL3 M1 BL4

n-array

p-collector common and grounded

base

emitters


x-BL equivalent electric circuit

M1 BL

M2 WL1 M2 WL2 M2 WL3 M2 WL4 M2 WL5 M2 WL6 M2 WL7 M2 WL8

AA AA AA AA AA AA AA AASTI STI STI STI STI STI STI

emitters

Bases (WLs)

Common collector


PNP-BJT Transistor

- BJT is not a field controlledtransistor but is mainly current controlled.As a results, some current flowingfrom the base to ground could exist.

- Properly biasing the base contact through the word line, the BJT can be used as aswitching selector

-The transistor gain is an important parameterto define WL voltage drop contributing toread and program performance

Base

Emitter

Collector


Selection through PNP-BJT

- Collector is alwaysgrounded while theemitter and base are used for selectionpurposes.

- The emitter is connected to the BLthrough the PCM cell, the base is connected to the WL through the base contacts

-We use the BJT almost as a diode but theBJT gain reduces voltage drops.

Base(WL)

Emitter

Collector

Storage

BL


Array stand-by: the leaker row

Leaker: 0V

+Vdd

+Vdd

+Vdd

FL FL FL FL

+Vdd

FL

When the array is switchedON, ready for programmingoperation, all the BJTs of thematrix are reverse biased athigh voltage, e.g. @ +Vddwith all the BLs let floatingfrom decoders

To manage the BLs voltage arow at the array edge (theleaker row) is carried @ 0 V

The BLs voltage stabilizes atan intermediate voltagebetween 0 and +Vdd. Whatvoltage?

IEB(+VBL)=(N-1)xIEB(-|Vdd-VBL|)

�VBL≈VTH of the emitter-base junction

�During stand-by there is consumptionVBL


Program biasing scheme: selected cell

+Vdd

0V

+Vdd

+Vdd

VBL

Vpulse<Vdd+VTH

VBL VBL

+Vdd

VBL

When the array isprogrammed the leaker isswitched off (WL leak. Vdd)

When the array is ready for programming, the selected WL is grounded and works asa leaker (there is aconsumption). The selectedBL is thus pulsed @ about Vddto program the cell.

During stand-by andprogram, the array leakagecould be severe, thus it mustbe minimized. How manyjunctions are leaking?

Stand-by: Ileak=(N)x(N-1)I EB(VBL-Vdd)

Program: Ileak=(N-1)x(N-1)I EB(VBL-Vdd)++(N-1)xIEB(Vpulse-Vdd)


Selected device during programming

- Programmed WL is biased to ground

- BL of the selected cell is carried at Vpulse(I(Prog)) � about 4 V

- EB junction is polarized in direct biasing

- Collector is grounded

- In the BJT (diode) flows the direct current at I(VEB))=I(Prog) � VEB about 2 V

Base(WL = 0 V)

Emitter

Collector = 0 V

Storage

BL� Vpulse


Standby/program biasing – unselected cell

+Vdd

0V

+Vdd

+Vdd

Vpulse

+Vdd

VBL VBL VBL VBL

Base(WL � +Vdd)

Emitter

Collector � 0 V

Storage

BL� VBL≈VTH

Two leakage:

• IBE � high contribution dueto BTB tunneling

• IBC � small contribution due to Impact ionization


Standby/program biasing – unselected row/column

+Vdd

0V

+Vdd

+Vdd

Vpulse

+Vdd

VBL

Unselected cells along theselected columns and rowsare biased at small voltages:

- Row � I(VBL) working asthe leaker

- Column � I(Vpulse-Vdd)

VBL VBL VBL


Base(WL = Vdd)

Emitter

Collector = 0 V

Storage

BL� Vpulse

Emitter

Collector = 0 V

Storage

BL� VBL

Base(WL = 0 V)

Unselected cells belonging from selected column

Unselected cells belonging from selected row works as leaker

Standby/program biasing – unselected row/column


BJT selector characteristics

�Active current as large as 300µA @ 2V

�Emitter leakage lower than 1pA / selector @3V even at hightemperature

0.0 0.5 1.0 1.5 2.0 2.50

100

200

300

400

500

30 C 85 C

VBE [V]0 1 2 3 4 5

1f

10f

100f

1p

10p

30 C 85 C

VBE [V]

Rev

erse

cu

rren

t [A

]


Isolation issues�Each active area (local WL) must be electrically isolated from theother ones.

�Each BE junction (belonging from different BLs) must be isolated from the adjacent ones

Emitter P

Base WLN at 0V

Base WLN at 4V

Collector P at 0 V

Emitter P

Emitter P at 0 V Emitter P at 4 VBase n+

Base n

Collector p

WL cut

BL cutSTI STISTI

Rot. STI Rot. STI Rot. STI

npn-BJT par.

pnp-BJT par.


Trench isolation

� To manage WL to WL isolation we can play

� Moving up the BC junction (raised emitter or epitaxy)

� Increasing the trench deep (difficult for technology)

� Increasing the collector doping (but this increases the BC leakage..)

Emitter P

Base WLN at 0V

Base WLN at 4V

Collector P at 0 V

Emitter P

BL cut

npn-BJT par.


Shallow STI isolation

� To manage BL to BL isolation we can play

� Taking the base-emitter junction as shallow as possible

� Increasing the rotated trench deep (Not easy for junction position)

� Increasing the base doping (but this increases theBE leakage..)

Emitter P at 0 V Emitter P at 4 VBase n+

Base n

Collector p

WL cutRot. STI Rot. STI Rot. STI

pnp-BJT par.


Outline




• System issues


• Conclusions


Array contingency

For the crossbar architecture a biasing scheme must be developed, considering

� Leakage during reading operation: when a cell must be read, the overallleakage of unselected cells along the same selected column must be at least one order of magnitude lower than the sensed current

� When the array is in the programming condition, the overall leakage of thearray must be lower than programming current. If not, the array throughput is severely depressed.

Different biasing schemes can be employed depending on the properties of the chosen storage element and the selecting device. Two extreme cases can be however identified:

� The standard rectifying scheme� V/2 biasing scheme


Cross-point standard rectifying biasing

N rows

M columns

0 V

Vread

Vread

0 V 0 V 0 V

Vread

(N-1) x I(V=0) << 0.1x I(Vread)

The following condition must hold for reading:

Always verifiedVread

Vread

Vread

Vread

0 V 0 V


Cross-point standard rectifying biasing

N rows

M columns

0 V

Vp

Vp

0 V 0 V 0 V

Vp

Vp

Vp

Vp

Vp

(N2-2N+1) x I(-(Vp)) << I(Vp)

The following condition must hold for programming:

0 V 0 V

Rectifying characteristics needed !!!

(N-1) x I(V=0) << 0.1x I(Vread)


Always verified


Cross-point V/2 biasing

(N-1) x I(+Vread/2) << 0.1xI(Vread))

The following condition musthold for reading:

Strongly non-linearcharacteristic needed !!!N rows

M columns

0 V

Vread/2

Vread

Vread/2

Vread/2

Vread/2

Vread/2

Vread/2

Vread/2 Vread/2 Vread/2 Vread/2 Vread/2


Cross-point V/2 biasing

(N2-2N+1) x I(0) << I(Vp)


N rows

M columns

0 V

Vp/2

Vp

Vp/2

Vp/2

Vp/2

Vp/2

Vp/2

Vp/2 Vp/2 Vp/2 Vp/2 Vp/2

(N-1) x I(+Vp/2) << 0.1x I(Vp)

(N-1) x I(+Vread/2) << 0.1xI(Vread)


Strongly non-linearcharacteristic needed !!!

During the programming in N-1 cells along the selected column and in N-1 cells along the selected rows flow a current equal to I(+Vp/2) that can cause a program disturb


Biasing scheme following the storage requirements

(N2-2N+1) x I(-0.33Vp) << I(Vp)


N rows

M columns

0 V

0.66V

V

0.66V

0.66V

0.66V

0.66V

0.66V

0.33V 0.33V 0.33V 0.33V 0.33V

(N-1) x I(+0.33Vp) << 0.1x I(Vp)

(N-1) x I(+0.33Vread) << I(Vread)


The leakage is depressed from I(+0.5Vread) to I(+0.33Vread)

By playing on the bias voltage is possible to better match the storage element characteristics. A compromise between read and program is always to be found


Simplified equivalent circuit

0 V

Vp

Vp

0 V 0 V 0 V

Vp

Vp

Vp

Vp

Vp

0 V 0 V

0 0.5 1 1.5 2-2

-1.5

-1

-0.5

0

0.5

1

1.5

2x 10

-3

Cur

rent

[A]

Array size

Read bitRead wordUnaccessed bitUnaccessed word

410×

Accessed junction

readword dd / 2V V=

unaccessedword dd / 2V V= −

unaccessedbit dd 2V V= +

readbit dd 2V V= −

sensV

Non

-acc

esse

d O

FF

Non

-acc

esse

d O

N

Non

-acc

esse

d O

FF

Non

-acc

esse

d O

N2n ×

Non

-acc

esse

d O

FF

Non

-acc

esse

d O

N

Vp

GND

GND

Vpn x

n x

SelSel

Diode from EU VERSATILE Project

- No issue during reading

- Leakage issue during program

-2 -1 0 1 210-610-510-410-310-210-1100101102103104

cure

nt d

ensi

ty (

A/c

m2 )

voltage (V)

Ion/Ioff ratio ~ 108

Best result of Versatile diode : Ag / ZnO


Outline




• System issues


• Conclusions


Possible applications

The high density/mass storage application market is continuouslyincreasing due to the increase of multi-media port able systems

Multi-layer stacked memories could be interesting f or

�High density applications (NAND-replacement): rewritable, high system embeddability, easy portabi lity, lowpower consumption

�Consumable applications: one time programmable, hig hsystem embeddability, easy portability, low powerconsumption


Specification for NAND replacement application

Specification for the junction in the case on NAND replacement application.

The storage element used for extracting the junction specification is the PCM.

104Do not care107 A/cm 2

106 A/cm 21.5-3 V

Direct1.5-3 V

ReverseDo not care

V/2 scheme

From -40 °CTo 55 °C

Do not care106107 A/cm 2

106 A/cm 21.5-3 V

Direct1.5-3 V

Reverse5-7 V

StandardrectifyingScheme

TemperatureRange

I (V)/I(V/2)

I(Vdd)/I (-Vdd)

Tile: 1k x1k

Max current density [A/cm 2]VreadVmax

Only diodeBiasing scheme


Consumable applications

Matrix semiconductor

Consumable Digital MediaTgt mkt: pc optional & non-pc

mainstreamUse mdl: store on card foreverChannel: mass merchant, food & drugAvg. price: low absolute out–of-pocket (3-5X cheape r)

Consumable memory cards

Videogame software storing

Can consumable device also play a role in portable s ystem fast growing market in future?


Specification for consumable application

The storage element actually chosen as an anti-fuse is the NiO developed in the EMMA project that can be programmed with 1.5 V and 1000 A/cm2..Alternatively Alumina was also considered.

Latest result from Versatile and Emma project fulf ill with these specifications!

104Do not care103 A/cm2102 A/cm21.5 V

Direct+2 V

ReverseDo not care

V/2 scheme

From -40 °CTo 55 °C

Do not care106103 A/cm2102 A/cm21.5 V

Direct+2 V

Reverse-3.5 V

StandardrectifyingScheme

TemperatureRange

I (Vdd)/I (Vdd/2)

I(Vdd)/I (-Vdd)

Max current density [A/cm2]VreadVmax

on diodeBiasing scheme


0 2 4 6 8 1010-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

Switch from OFF to ON state

Switch from ON to OFF state

curr

ent (

A)

voltage (V)

ZnO results

• Each cross point = selector + storage element

• Storage element : binary oxide (EMMA project)

• 4 steps of UV lithography

Ag

Metal Ti/AuZnO

Metal Binary oxide

Schottky Diode

Storage element

EU funded Versatile and Emma projects


Application scenario

Application scenario for stacked memory:

�NAND-replacement application if its cost is comparable to the costof ML-NAND technology (this implies at least 2 stacked levels witha 1D1R scheme and it looks feasible)

�Consumable application if its cost is at least 5 times lowerthan the NAND one (this implies a large number of levels, e. g. 5.High risk due to high number of critical masks that can impactthe yield)


Outline




• System issues


• Conclusions


Design flowSingle layer view:

�Programming current of memory element, Iprog

�Iprog must be delivered by decoders� W of MOS� overall dec. area �tile size

�Iprog defines the maximum direct voltage required taking into account the

voltage drop on the selector and parasitics (WLs BLs additional drops)

�Reverse voltage to deselect rows Vunsel should be closed to maximum direct voltage

�Assuming a rectifying or V/2 scheme, the leakage determine the overall array consumption

System view:

�Tile size at least equal to decoder size

�Partitioning of tiles can help in managing the overall leakage


Selecting element performances

-2 -1 0 1 210-610-510-410-310-210-1100101102103104

cure

nt d

ensi

ty (

A/c

m2 )

voltage (V)

Ion/Ioff ratio ~ 108

Best result of Versatile diode : Ag / ZnO

> 600 uA< 300 uAMax direct current @ 45nm tech node

~ 0.8 - 0.9 V~ 1 - 2 VThreshold voltage ( 1uA @ 45 nm tech node)

>1011< 108Max Ion (+2V) / Ioff ratio (-2V)

> 30 MA / cm 2< 8 -10 MA / cm 2Max density current before breakdown (direct )

Front end (typical)Back end (best results)DIODE Parameter

Best result for leakage: EU Versatile project Best result for direct current


NiO-based RRAM as storage

45 nmTech node (F)

< 4VNiO forming voltage

250 uANiO reset current

2.5 VNiO reset voltage

3 VNiO set voltage

< 100 nsNiO set/reset time

500uA /umn-MOS driving current capability [1/ W]

1-10 [MB/s]Write throughput

200uA /ump-MOS driving current capability [1/ W]

Mean valueParameter


Array sizing @ 45nm

• The cell programming current drives the decoders size• The minimum tile size is dictated by space required to allocate decoders (array efficiency >

90%)• Tile size define the parasitics, thus the required voltages and consumption. 4Mbit array

seems a good starting point (to be verified):� Array area = 43200 um2

� Decoder area = 42600 um2

Array area

Silicon Area

Array sizing

Decoders area

n

Programming current


Programming path voltages (parasitics)Process parameters:

�F = 45 nm (technology node)�Cell size: 4F2 = 0.0108um2�Rwl @ Cu / bit 0.5 ohm/bit�Rbl @ Cu / bit 0.5 ohm/bit�CCELL ~ 0.05fF (negligible)

Cu damascene process available today

~ 5 Maximum required voltage

0.25 BL resistance (1kOhm)

0.25 WL resistance (1kOhm)

2 Back end diode

2.5Storage (NiO )

Voltage drop [V]

(worst case)Programming path

80-100 A CMOS oxide


Vp = 5VVunsel = 4.5VV (leaker) = 1V (~Vth diode) IDIODE(Vp)= 250uA

Rectifying scheme

IDIODE (Vleak-Vunsel) x (N-1)2 << IPROG (<IPROG / 10)

� IDIODE (- 3.5V) < 6pA /bit � I(Vp)/I(Vleak-Vunsel) > 4x107

Total array leakage:

N row

s

N columns

0 V

Vunsel

Vunsel

Vleak Vleak Vleak

Vp

Vunsel

Vunsel

Vunsel

Vunsel

Vleak Vleak

Courtesy of Tortorelli, EU funded EMMA Project


Vp = 5VVunsel = 3.3 VVBL = 1.7V IDIODE(Vp)= 250uA

V/3, 2/3V polarization scheme

Pro and Cons:•Leakage: IDIODO(VBL-Vunsel) x (N-1)2 < IPROG/10 � IDIODO (-1.7 V) < 6 pA /bit•Disturb: I (Vp-Vunsel)< Idisturb � I (+1.7 V) •Sensing: I (0.33xVread)x (N-1) < 0.1xI(Vread) �I (0.33xVread) < 0.5 nA•Further consumption: I (+1.7V) x N < 0.1 x Iprog � I (+1.7V) <20 nA/bit•Ratio: I(Vp)/I(-1.7 V)=4x107 ~ I(Vp)/I(-3.5 V)=2.5x105

N row

s

N columns

0 V

Vunsel

Vunsel

VBL VBL VBL

Vp

Vunsel

Vunsel

Vunsel

Vunsel

VBL VBL


Polarization schemes comparison

2.5x1054x107I(Vp)/I(-3.5 V)

250 uA @ 2V250 uA @ 2VDirect current

~ 60mV / dec> 60 mV / decDirect slope

(ideal : 60mV/dec)

> 1.7No matterThreshold voltage

~ 3 pA/bit~ 1 nA /bitReverse leakage

(< 6pA/bit)

< - 1.7V< - 3.5Break down

V/3, 2/3VRectifying

� Leakage issue: exacerbated by scaling because of periphery defects� VTH > 1.8V � needed other kind of switch selector!!


Conclusions

• The 3D approach is an effective way to reduce cost per bit of a NVM

• Self selected crossbar array are today not available. No resistive memory satisfy the requested non-linearity IV constraints.

• Strong efforts to find a suitable selector able to drive the current requested by the storage element till maintaining good leakage performances

• A careful optimization of array design is mandatory to exploit the diode and storage element characteristics

• The NAND replacement application (data storage) still remain thedriving force of this activity

crossbar architecture for nvm last - politecnico di milanocorsi.dei.polimi.it/ess/nvm/nvm_5a.pdf ·...

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