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TRANSCRIPT
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Creation of Nanometre-Scale
Islands, Wires and Holes on Silicon Surfaces
for Microelectronics
Ph.D. Thesis
V. Palermo
University of Bologna
March 2003
© All Rights Reserved
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2 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
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Università degli studi di Bologna
Creazione di isole, fili e fori nanoscopici su superfici di silicio per microelettronica
Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
Tesi di Dottorato di Ricerca Scienze Chimiche
XV ciclo
Presentata da: Vincenzo Palermo
Relatore:Prof. Alberto Ripamonti
Co-Relatore: Dott. Derek Jones
Coordinatore di Dottorato: Prof. Goffredo Rosini
Marzo 2003
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4 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
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OMNIA IN MENSURA, ET NUMERO ET PONDERE.
Sapientiae Salomonis, 11:20
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6 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
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1. Introduction: nanotechnology and the future of computers The motivations of nanotechnology research
In 1965 an electronic engineer named Gordon Moore, one of the future founders of Intel,
noted that the performance of computers and their complexity doubled every 18 months
and foresaw that computer power would continue to grow exponentially over the following
years.
This prevision, quite provocative for its time, actually came about and gained the name of
“Moore’s Law”, and continues to hold for the trends of today’s computer industry. Since
1965, the number of transistors present in an integrated circuit (IC) has increased from
several hundred to more than ten million, and the minimum size of transistor elements has
shrunk from several millimetres to ≈130 nanometres (fig. 1.1).
Devices of such tiny dimensions are actually fabricated using lithographic techniques,
where light is passed through an optical mask to react with a photo-sensitive layer (resist)
Fig.1.1. Evolution of the number of transistors present on commercial computers [1].
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8 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
on the silicon wafer. This resist is then selectively removed and used as a mask for
processing the silicon surface (fig. 1.2, left). The maximum resolution attainable depends
upon the wavelength used, and current technology is near to its intrinsic resolution limit.
On the other hand, there is strong scientific and economic demand for further development
in IC miniaturization, to obtain more powerful and complex computers. Besides every-day
life applications, more powerful computers are fundamental for much scientific research,
such as climate change tracking, genome sequencing, and fluid dynamics. Increased
miniaturization is also fundamental for reducing power which has to be dissipated by the
chips which run at progressively higher frequencies. Energy consumption by
microelectronic devices is already an issue, and represents one of the main obstacles for
the continuing growth in wireless communication (cell phones, portable computers, CD
and DVD players, digital cameras, etc.).
Thus, it is expected that new production methods, different from current lithographic ones,
will be developed, methods which allow modification of a surface well below the 100 nm
limit, and even down to single atom manipulation. Techniques such as Scanning
Tunnelling Microscopy and Atomic Force Microscopy are already capable of moving
single atoms (see fig. 1.2, right) but, unfortunately, building a working nanodevice in this
way would take a very long time, and these techniques are difficult to apply to large scale
production.
Nowadays, thousands of researchers are working in the nanotechnology field towards a
new generation of microelectronic devices. Several possible solutions are competing for
tomorrow’s computer architecture, and there is still no clear winner. It is likely that the
final solution will be the combined use of different techniques and components (including
molecules, nanowires and nanodots) as they become available together with conventional
Fig. 1.2. Left: conventional litographic process [2]. Right: atomic manipulation of iron atoms on copper [3].
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silicon technology.
Below is a brief summary of the most recent developments in nanotechnology and
nanoscience.
Actual trends in nanotechnology
Perhaps, the most fascinating idea for nanodevice construction is to use one single
molecule, working as a complete device. The first molecular diodes (i.e. molecules
conducting current only in one direction) were created in 1997; in 1999, a molecular fuse
and a molecular transistor were demonstrated, although there was no possibility of wiring
these devices to external contacts. In April 2001, James Heath and his group at UCLA
fabricated an array of overlapping crossbars, and placed a small molecule of rotaxane
between each crossbar (fig. 1.3, left). This composite molecule is made up of two
component parts, the main rod-like molecular axis and a mobile ring “threaded” on it like a
bead on a necklace, and can function as a molecular switch. A working 16-bit memory
circuit was constructed using these molecules. For a brief review of these works, see [4]. In
June 2002, a single molecule transistor was built by connecting an organic molecule to two
metal contacts; the molecule contained one or two atoms of a transition metal (cobalt or
vanadium) forming the active region of the device, supported by an organic backbone [5].
Fig.1.3. Working nanodevices. Left: schematic representation of rotaxane molecules between crossed nanowires [4]. Right: SEM image of semiconductor nanowires forming a small circuit [9].
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10 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
Another approach to nanodevice fabrication has become possible through the discovery of
carbon nanotubes, which were observed for the first time in 1991 by a Japanese electron
microscopist studying the material deposited during arc-evaporation synthesis of fullerenes
[6]. They consist of a graphite-like carbon seamless cylinder, with a diameter of several
nanometers and lengths of up to a millimetre. Carbon nanotubes are very stable, can
behave as metals or semiconductors, and can host other molecular or ionic species thus
modifying their electrical behaviour. In 2001, Avouris and his group reported the first
circuit made with a single nanotube [7]. A few months later, Cees Dekker presented a
nanotube-based transistor able to amplify an input signal by a factor of ten, and built
several logic circuits using these nanotube transistors [8].
One problem with carbon nanotubes is that it is very difficult to control their electronic
properties, i.e., their metallic or semiconducting behaviour. An alternative to carbon
nanotubes are semiconductor nanowires. Silicon nanowires can be made using a laser to
vaporize the silicon together with a metal catalyst, like iron or gold. The vapour condenses
in nanosized drops of silicon and metal, from which the wires slowly grow out as more
silicon is adsorbed. In 2001, a group at Harvard University [9] created a transistor by
crossing two different nanowires. After this, the same group arranged four nanowires in a
noughts and crosses grid, creating something like a 4-bit memory (fig. 1.3, right). Even
metallic nanowires, made of platinum and silver, can be used in a crossed configuration to
store information [10].
There are some issues common to all these new technologies, though. First, it is difficult to
imagine these methods applied to large-scale production. Up to now, the insertion of a
molecule between two electrodes is an occasional, lucky event, while nanotubes and wires
have to be positioned on the surface, creating the appropriate contacts on them manually.
The large-scale production of integrated circuits using these building blocks will not be
straightforward and does not seem imminent.
Another issue is of an economic and not a scientific or technological nature. Since 1965,
the cost of IC manufacturing plants has sky-rocketed. If the cost of semiconductor
production plants continues to rise exponentially, in a few years such plants will cost up to
$20 billion. This is a sizeable investment, even for large companies such as IBM or Intel.
For this reason, it is likely that IC companies will resist changing to completely new
technologies, closing down their existing plants. As it is clear that silicon will remain the
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fundamental raw material of the IC industry for the foreseeable future, nanotechnology
developments for microelectronics will need to be silicon-compatible. In these early days
of nanotechnology, the most valid approach would seem to be the addition of molecular
functions to existing silicon technology – using the latter as a foundation on which to build.
Fabrication of self-organised structures on silicon
The possibility of using the phenomenon of atomic or molecular self-organization to create
nanostructures on silicon has already been demonstrated. The clean silicon surface shows
in some cases a high degree of order and complex surface reconstruction, as will be
described later. Several different ordered structures form spontaneously on this surface,
such as series of monatomic steps or boundaries between reconstructed areas. It has been
demonstrated that it is possible to use these structures to fabricate ordered nanodots and
nanolines on the surface [11]. More recently, well-defined nanometric patterns have been
obtained with selective etching of silicon using nitric oxide [12].
In this study the possibility of creating different types of nanostructures on the silicon
surface is explored. Methods had to be developed which were:
- Simple. They must not need complex masks or lithographic steps to create the
structure, but rather exploit self-organisation phenomena;.
- High resolution: the silicon surface modifications should be on a scalelength of below
100 nm;
- Fast: billions of nanostructures have to form over the whole surface simultaneously, to
be compatible with large-scale production requirements;
- Cheap: they must not require expensive equipment (such as e-beam lithography), but
exploit simple chemical and/or physical treatments to produce nanostructures on the
silicon surface.
In Chapter 2, the main characteristics of silicon are described. Chapter 3 provides a
summary of the techniques used for this research. Chapter 4 examines the chemical etching
of silicon in different liquid environments, and the effects of this etching on the surface at a
nanoscopic level, with the creation of nanoholes.
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12 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
Chapter 5 describes the growth in ultra-high vacuum (UHV) of nanoscopic voids and
islands on the silicon surface, and the effect of surface oxide on this growth.
Chapter 6 discusses the modification of silicon surfaces in UHV, following the adsorption
of molecules and thermal heating, to produce nanoislands and nanolines on silicon.
The overall conclusions of our work are summarised in Chapter 7.
Finally we will give some conclusions based on the results obtained, and discuss possible
applications of the methods developed.
Bibliography
[1] From www.intel.com
[2] From www.sematech.org
[3] Confinement Of Electrons In Quantum Corrals On A Metal Surface, Crommie MF,
Lutz CP, Eigler DM, Science 262 (5131): 218-220 Oct 8 1993.
[4] Molecules Get Wired, Service RF, Science 294 (5551): 2442-2443 Dec 21 2001.
[5] Coulomb Blockade And The Kondo Effect In Single-Atom Transistors, Park J,
Pasupathy AN, Goldsmith JI, Chang C, Yaish Y, Petta JR, Rinkoski M, Sethna JP,
Abruna HD, Mceuen PL, Ralph DC, Nature 417 (6890): 722-725 Jun 13 2002 ; Kondo
Resonance In A Single-Molecule Transistor, Liang WJ, Shores MP, Bockrath M, Long
JR, Park H, Nature 417 (6890): 725-729 Jun 13 2002 ; Nanotechnology - Electronics
And The Single Atom, De Franceschi S, Kouwenhoven L, Nature 417 (6890): 701-702
Jun 13 2002.
[6] Smallest Carbon Nanotube, Ajayan PM, Ijima S, Nature 358 (6381): 23-23 Jul 2 1992.
[7] Carbon Nanotube Inter- And Intramolecular Logic Gates, Derycke V, Martel R,
Appenzeller J, Nano Letters 1 (9): 453-456 Sep 2001.
[8] Logic Circuits With Carbon Nanotube Transistors, Bachtold A, Hadley P, Nakanishi T,
Dekker C, Science 294 (5545): 1317-1320 Nov 2001.
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[9] Logic Gates And Computation From Assembled Nanowire Building Blocks, Huang Y,
Duan XF, Cui Y, Lauhon LJ, Kim Kh, Lieber CM, Science 294 (5545): 1313-1317
Nov 9 2001.
[10] Formation And Disappearance Of A Nanoscale Silver Cluster Realized By Solid
Electrochemical Reaction, Terabe K, Nakayama T, Hasegawa T, Aono M, Journal Of
Applied Physics 91 (12): 10110-10114 Jun 15 2002.
[11] Fabrication And Integration Of Nanostructures On Si Surfaces, Ogino T, Hibino H,
Homma Y, Kobayashi Y, Prabhakaran K, Sumitomo K, Omi H, Accounts Of Chemical
Research 32 (5): 447-454 May 1999.
[12] Ultrafine And Well-Defined Patterns On Silicon Through Reaction Selectivity,
Prabhakaran K, Hibino H, Ogino T, Advanced Materials 14 (19): 1418-1421 Oct 2
2002.
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14 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
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2. Silicon surfaces
The name silicon (silicio in Italian) comes from the latin word silex. Amorphous silicon
was first isolated by Berzelius, in 1824, by reaction of potassium with silicon tetrafluoride.
Thirty years later, the first crystalline silicon was prepared. Silicon makes up 25% of
earth’s crust, and is the second most abundant element after oxygen. Elemental silicon is
not found in nature, occurring as silicon oxide (sand, quartz, amethyst, flint, etc.) or
silicates (asbestos, clay, mica, etc.). Perhaps no other element and its compounds has such
a wide range of uses. Silicon compounds such as sand and clay are used in the building
industry, as refractory materials for high-temperature applications and for enamels and
pottery. Silica is the main component of glass, silicon carbide is an important abrasive, and
silicones are commonly used polymers and lubricants.
Here, the most interesting use of silicon, of course, is for the production of
microelectronics devices. For this application, silicon of high purity (99.9999%) and of
high crystallinity is needed. Table 2.1 lists some of the physical characteristics of silicon.
High purity polycrystalline silicon is produced by the reaction of gaseous trichlorosilane
with hydrogen in a furnace. Then, to prepare a single-crystal of silicon, the so-called
Czochralski method is commonly used.
Polycrystalline silicon is melted in a quartz furnace at 1415°C in an argon atmosphere.
Then, a seed of single-crystal silicon is lowered into contact with the melt, and slowly
pulled out . In this way, the crystal grows and a crystalline cylindrical ingot several metres
long is created from the initial seed.
After cooling down, the ingot is sliced into thin silicon wafers. The wafer surfaces are
polished using a counter-rotating lapping machine in an Al2O3 slurry until the surface is
very flat and shiny, ready for the lithographic processes.
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16 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
Another way to obtain single crystal silicon is the Floating Zone (FZ) method, in which a
silicon cylinder is slowly passed through a heating ring. The area inside the ring melts, and
solidifies smoothly, crystallising as it comes out of the ring yielding a single silicon crystal.
Microelectronic devices are built on the silicon surface, which is the surface of interest
here. Unfortunately, silicon surfaces are normally quite dirty and uneven at the atomic
scale. Atmospheric oxygen and humidity react with silicon surfaces creating a thin layer of
oxide (called “native oxide”), which is usually irregular and full of defects. Different kinds
of contaminants also adsorb onto the surface. These are usually small organic molecules
and microscopic dust particles. A clean surface, on exposure to the atmosphere, is
completely covered with gas molecules, in less than 10-9 seconds. If the pressure is
reduced, let’s say to 10-6 mbar, this time increases to 1 second. This is the reason why to
study a clean surface we have to work in UHV, at pressures below 10-10 mbar.
The atoms in the silicon crystal have a diamond-like structure, each atom having 4 bonds
in a tetrahedral sp3 arrangement, with bond angles of 109.47 degrees. At the crystal
surface, some atoms will have non-bonding orbitals “dangling” in the vacuum, i.e. sp3
orbitals with a lone electron which are highly reactive. These orbitals are known as
dangling bonds. To minimize surface energy, the surface will reorganize, by decreasing
the number of dangling bonds.
Table 2.1 Physical data of silicon [1].
Atomic Weight 28.09 Lattice constant (A) 5.43095 Crystal structure Face-centered cubic
(diamond) Melting point 1415 °C
Density (g/cm3) 2.328 Boiling point 2355°C Atoms/cm3 5.0E22 Minority carrier
lifetime (s) 2.5E-3
Dielectric Constant 11.9 Specific heat (J/g °C)
0.7
Breakdown field (V/cm)
~3E5 Thermal conductivity (W/cm °C)
1.5
Electron affinity, x(V)
4.05 Vapour pressure (Pa) 1 at 1650°C, 1E-6 at 900° C
Energy gap (eV) at 300K
1.12 Reactivity Inert to acids. Attacked by halogens and alkaline
solutions Intrinsic carrier
conc. (cm-3) 1.45E10 Oxidation states +4, -4
Intrinsic Debye Length (µm)
24 Energy of a Si-Si bond (eV)
2.32
Intrinsic resistivity (Ω-cm)
2.3E5
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Dangling bond densities and positions, and thus the type of surface reconstruction, will
depend upon crystal orientation as well as the temperature and kinetics of the system.
Fig. 2.1 shows a drawing of the main faces of a silicon crystal. The angle α between any
(11n) face and the (100) face can be calculated from: 2/cos 2 += nnα . The angle
between any (11n) face and the (111) face can be calculated from:
)2(3/)2(cos 2 ++= nnα .
The chemistry and physics of the faces are very different; a brief description will be given
for the most important orientations.
Si (100)
On the (100) surface, each atom has two Si-Si bonds connecting it to the bulk and two
dangling bonds pointing outward. Surface energy is reduced by the dimerisation of the
surface atoms through overlap interaction of one dangling bond per atom, forming rows of
dimers aligned along the (110) direction. This is the well-known “2x1” reconstruction of
this silicon surface. The symmetric dimers would make the silicon surface metallic, but to
reduce surface stress the dimers tend to buckle, and the surface is thus semiconductive. It
took several years to understand that the dimers are buckled, because at room temperature
Fig. 2.1. Schematic view of the principal orientations of a silicon surface. Surface atoms are white, bulk atoms are black, dangling bonds are gray [2].
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18 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
they shift easily from one buckling direction to the other, thus appearing symmetric under
STM observation. Fig. 2.2 shows an STM image of the 2x1 reconstructed surface.
Even almost perfect (100) surfaces have a certain number of monoatomic steps and the
dimer rows on atomic layers are aligned at 90° to those on adjacent layers. Dimer rows are
thus perpendicular or parallel to the step. When the dimers on the upper side of the step
are parallel to the step, the step is called SA; if they are perpendicular, the step is called SB
Because of this symmetry, SA step edges will be smoother compared to the more broken,
fragmented edges of the SB steps
A common defect on the Si(100) surface is the presence of nickel contamination, which
appear as missing dimers in STM images. This type of contamination is so critical that
even if the silicon sample is only briefly brought into contact with stainless steel tools
(tweezers, for example), the 2x1 reconstruction of the surface can be blocked.
Silicon atoms can diffuse easily over the silicon surface as monomers and dimers
especially at elevated temperatures. The anisotropy due to the 2x1 reconstruction causes a
difference in the diffusion energies of adsorbates over the surface. Diffusion of these
silicon species along dimer rows, for example, will be much easier. A list of diffusion
energies for monomers and dimers is given below [2]:
Diffusion on Si(100) 2x1 Ed (eV) Monomers along dimer rows 0.6 Monomers across dimer rows 0.85 Monomer formation energy 1.8 Dimer along dimer rows 1.1 Dimer across dimer rows 1.5 Dimer formation energy 2.6 Dimer binding energy 0.76 Vacancies along dimer rows 1.7 Vacancies across dimer rows 1.9
SA
SB
Fig. 2.2. STM image of a 2x1reconstructed silicon surface,showing the dimer rows and steps,40x35 nm. Nickel-induced defectsare visible as dark spots. SA and SBsteps are indicated
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So, the diffusion energy for both monomers and dimers is nearly 40% greater if they have
to cross a dimer row. This difference reduces to ∼10% for vacancy diffusion.
Si(113)
The (113) surface can be imaged as a sequence of alternating (100) and (111)-like
structures, with two and one dangling bonds on alternate atoms, respectively. Interest in the
(113) surface is scientific, as it has been used to study the energetics of the (100) and (111)
surfaces, as well as for surface adsorption experiments.
Si(100) surfaces can easily develop (113) facets.
Si(111)
This surface, besides being the first one imaged with STM with atomic resolution, is one of
the most studied, because it is the best cleavage face of silicon, and because it shows one
of the most complex and elegant reconstructions in surface science.
All Si-Si bonds in the silicon crystal are perpendicular to a (111) plane, so this face will
have the lowest number of dangling bonds created per unit area. In fact, each Si atom on a
(111) surface shows a single dangling bond oriented perpendicular to the surface, and
bonded to three back atoms. These three bonds for each surface atom account for the great
chemical and physical stability of the Si(111) surface. Surface energy is 0.09 eV Å-2,
compared to 0.15 eV Å-2 for Si(100).
For energy minimization, this surface reconstructs, forming a huge 7x7 lattice cell
containing 102 atoms, described by the Dimer-Adatom-Stacking fault model (DAS). For a
detailed description of cell structure, see fig. 2.3.
The cell described by this model is very complex, being composed of three kinds of atoms:
adatoms, rest atoms and corner hole atoms. Furthermore, a subsurface stacking fault is
present in one half of the cell, making the two halves of the unit cell look different under
STM (Fig. 2.4). It took 26 years of research to completely understand the exact structure of
the 7x7 reconstruction.
Cleaving a silicon crystal along a (111) plane produces a metastable 2x1 reconstruction;
the 7x7 reconstruction is easily obtained by flashing at high temperature in UHV. At T >
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20 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
830°C, a disordered 1x1 phase covers the surface. Cooling down to 800°C leads to the
formation of the 7x7 phase. If the cooling process is too rapid, small 7x7 domains nucleate,
and a disordered 1x1 phase is preserved between domain boundaries.
Si(110)
Even though, as mentioned before, the (111) plane is the favoured cleaving plane of
silicon, thin (100) commercial wafers will not break along this plane, because the angle
between (100) and (111) is too far from 90° (see table 2.2). Instead, they will break along
the (110) plane because it is perpendicular to the (100) surface. Each surface atom on
Si(110) has a Si-Si bond pointing downward, one dangling bond pointing outward, and two
Si-Si bonds parallel to the surface, in a zig-zag pattern (see fig. 2.1). Cleaved (110)
surfaces are disordered but, upon annealing at high temperatures an ordered, complex 16x2
Fig.2.3 Scheme of the 7x7 DAS model [2]. In each unit cell there are 9 dimers, 12 adatoms, and a stacking layer fault. The force driving this complex reconstruction is the minimization of dangling bonddensity. The DAS model shows the lowest number of dangling bonds (19) of all possiblereconstructions. 12 dangling bonds are at the adatoms, 6 at the rest atoms and 1 at the corner hole atom. This surface is metallic.
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reconstruction takes place. The surface appears as a series of long ridges and valleys
parallel to each other. Eventually, tilted facets of orientation (17 15 1) can form on this
surface. The adsorption of Ge atoms on this surface leads to the formation of self-
assembled nanowires [3].
Table 2.2. Angles in degrees between different silicon faces [2].
Orientation
113
110
111
100
100
25.24
90.00
54.74
0
111
29.50
35.26
0
110
64.76
0
113
0
Fig. 2.4. STM image of a Si(111)surface, with 7x7 reconstruction. A unitcell with its adatoms is highlighted.Image size 13x13 nm.
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22 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
Bibliography
[1] Weast RC, Handbook Of Chemistry And Physics (Chemical Rubber Co., Cleveland,
1972)
[2] Dabrowski J, Mussig H, Silicon Surfaces And Formation Of Interfaces (World
Scientific Publishing, Singapore, 2000).
[3] The Structure Of Clean And SiGe-Covered Si(110) Surfaces, Butz R, Luth H, Surface
Science 365 (3): 807-816 Oct 1 1996
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3. STM and other surface analysis
techniques
Scanning Tunneling Microscopy
Since the invention of the optical microscope at the end of the 16th century, the possibility
of examining surfaces at higher and higher magnification has fascinated mankind.
Development of the technique continued and towards the end of the 19th century optical
microscopes were as good as today's standard instruments. The physical limits of the
wavelength of visible light (350-800nm) had been reached.
In the 1920s de Broglie showed that electrons can behave like waves and the use of these
particles for imaging with much higher resolution soon followed. Atomic resolution using
this technique is only possible in the transmission mode with extremely carefully prepared
samples.
In 1982, using the peculiar properties of piezoelectric materials, Binnig and Rohrer brought
a metallic tip very, very close to a silicon surface and scanned it across an extremly small
area (fig.3.1). The tunneling of electrons from the tip into the sample or vice versa allowed
them to obtain a local density of electronic states (LDOS) map of that surface. Although
theory (which treated the extreme point of the tip as a sphere) then excluded the possibility
of atomic resolution, following a tip "crash" into the surface, Binnig and Rohrer began to
observe the LDOS with atomic resolution. For this discovery and their following work,
they were awarded the Nobel Prize in Physics in 1986.
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24 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
The basic principle of STM is very simple. A metallic tip is scanned over a surface without
making ohmic contact, and a tunneling current passes between the tip and the surface. An
electronic circuit keeps this current constant by raising and lowering the tip during the
scan. In this way, recording the tip height at each point a three-dimensional image of local
density of electronic states (LDOS) of the surface can be obtained. To explain the
extremely high resolution attainable by this simple technique, quantum theory is needed.
According to classical physics, the current will flow between sample and tip only if they
are in physical contact. If there is a vacuum gap between the two, the electrons will simply
remain confined, for example, within the surface, without the possibility of passing into the
tip.
In quantum physics, however, the electrons have a certain probability of passing
(tunneling) across the gap, appearing on the other side of the gap, in this way reaching the
tip. It can be shown that the probability of an electron tunneling through a gap of thickness
z is:
kzep 22)0( −∝ ψ ; h
φmk
2= (1)
where ψ(0) is the electron wavefunction at the surface-gap border, m is the electron
mass=9.1x10-28 g, and φ is the work function of the metal (i.e. the energy required to
remove an electron from that material. For silicon it is 4.8 eV). The tunneling current thus
decays exponentially with z, and is extremely sensitive to topographical imperfections
present on the scanned surface. A rough formula giving the current as a function of z is [1]:
zFS eEVI
φρ 025.1)( −∝
Fig. 3.1. Binnig and Rohrer with the first STM. Image from IBM [2].
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V.Palermo 25
where ρs(EF) is the local density of states at the Fermi level on the given surface. For
example, the formula predicts that, for silicon, an increase in tip-surface distance of 1 Å
will give a 95% decrease in tunneling current.
This huge dependence of tunneling current upon the distance allows detection even of the
sub-nanometre changes in height given by the single atoms of which the surface is
composed, and thus to resolve them in the LDOS images. Of course this description of the
tunneling process is oversimplified and, for a more accurate one, the electronic states of
the tip, of the sample and their interaction have to be taken into account. Fig. 3.2 shows a
schematic representation of the interaction between tip and sample orbitals.
The exponential decay of current with distance also yields high lateral resolution. If the tip
is approximated as a sphere of radius R and the current passing at the minimum tip-sample
distance is I0, then the current passing at a lateral distance x from this point will be:
Rxk
eII 22
0
2−
=
Assuming a tip radius of 100 nm, the current is concentrated in an area ∼1.5 nm wide at tip
apex.
Very sharp tips with even smaller curvature radii can be produced in several ways. Simple
Fig.3.2. Schematic view of tip-sampleorbitals interaction. a) no interaction. b)equilibrium. c) sample positive. d) tippositive [1].
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26 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
tungsten wires mechanically cut are capable of obtaining atomic resolution on graphite in
air, but for more disordered and rougher samples sharper and more reproducible tips are
needed.
STM tips are mostly made by electrochemically etching a W or Pt-Ir wire. The tips we
used were prepared using methods based on the work of Fotino [3].
A tungsten wire, 0.38 nm diameter, is immersed in a KOH solution(0.6M) with a thicker
tungsten wire used as a counterelectrode. The cathodic and anodic reactions involved in the
etching are:
Cathode: 6H2O + 6 e- → 3H2(g) + 6 OH-
Anode: W(s) + 8 OH- → WO42- + 4H2O + 6 e-
A potential of 3V a.c. is applied to the tungsten, and the wire is immersed in the solution
until a constant current of ∼100 mA is established. The etching rapidly removes metal,
shaping the wire end as a sharp tip. When the potential reaches 11 V, the coarse tip etching
is finished. The wire is then removed from the solution, carefully inserted into an
insulating plastic tube leaving only the tip exposed, and re-immersed in the solution with
the tip pointing upwards. A more gentle etching is thus made to reduce tip radius. Usually
5 minutes etching at 0.7 V a.c. is used. In this configuration, very small hydrogen bubbles
formed on the tip sides sliding upwards with a “honing” effect on the tip.
This procedure yields extremely sharp and reproducible tips at the microscopic level.
After the etching, the tip is thoroughly rinsed in ultrapure water, then dipped into
concentrated HF to remove surface oxides and hydroxides [4]. The tip is dried with
nitrogen, inserted into the UHV system and degassed overnight at ∼150°C.
The possibility of measuring sub-nanometric distances would be useless without being able
to control tip movement over such a minute scale. To scan the tip over the surface, a
piezoelectric scanner is used. Piezos are usually made of an alloy of PbZrO3 and PbTiO3, a
material which contracts or expands when a voltage is applied to it. The Omicron
instrument used in our laboratory has three such piezo scanners for x,y, and z tip motion,
allowing one to scan the tip over the surface with sub-Ångstrom precision (fig. 3.3).
To isolate the instrument from ambient vibrations, the whole STM stage is suspended upon
four springs, which eliminate all frequencies above 1 Hz, and surrounded by a crown of
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V.Palermo 27
copper wings and fixed magnets. Parasitic currents generated by the magnets into the
copper wings contrast every movement of the stage, and efficiently block stage vibrations.
The STM can be used not only to explore surface topography, but to measure the I/V
characteristics of single atoms or molecules on the surface (Scanning Tunneling
Spectroscopy or STS). Furthermore, it can be used to modify the surface with voltage
bursts, digging into it or delicately moving single molecules or atoms over a surface [5]. It
can be used in vacuum, in air and, with proper lateral isolation of the tip, even in liquids.
A major drawback of STM is that it works only on conducting and semiconducting
surfaces, and thus cannot be used on many surfaces of biological and chemical interest.
Another instrument more suitable for these and other applications is the Atomic Force
Microscope (AFM).
Atomic Force Microscopy
AFM was invented in 1986 by Binnig, Quate and Gerber after calculating the possibility of
building a cantilever with a force constant of the same order of magnitude as that of a
chemical bond.
In AFM, a tip mounted on a microscopic cantilever (usually made of Si3N4, fabricated with
optical lithography) is brought close to a surface. When the tip touches the surface, the
cantilever is very slightly deflected upwards. The movement is measured by observing the
Y-PIEZO
SILICON SAMPLE
Fig. 3.3. A picture of theSTM used for theexperiments. The tripodpiezo scanner is shown.
Z-PIEZO
X-PIEZO
TIP
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28 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
deviation of a laser beam hitting the upper face of the cantilever. Fig. 3.4 provides a
schematic view of the principle of AFM.
The typical force constant of the cantilever varies from 0.0006 to 2 N/m, the typical
resonance frequency is 3 to 120 kHz. The AFM tip can apply a force on the sample of up
to 10-9 N. The AFM can be used on conductive or insulating surfaces, in vacuum, air or
liquids. Furthermore, the tip can be modified to sense electrostatic potentials (electric force
microscopy) or magnetic fields (magnetic force microscopy); it can even be functionalized
with complex molecules such as proteins, to interact with biological surfaces.
A drawback of the AFM is that the force it exerts can damage the surface under
observation, especially if the sample is soft (as in the case of cell membranes, for
example). This problem can be overcome using the instrument in tapping mode (where the
tip does not move laterally during its brief contact with the surface) or in non-contact mode
in which the tip oscillates above the surface during the scan and the changes in its
frequency due to interaction with surface are monitored. The shifts in the oscillating
frequency of the cantilever due to tip-sample interaction are then used for imaging the
surface. In this mode, interaction of the tip with the surface is minimal, and soft samples
can be imaged.
STM and AFM are the main techniques used for this work. A brief description of other
techniques used occasionally is given below.
Fig. 3.4. Scheme of an atomic force microscope.
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V.Palermo 29
Low Energy Electron Diffraction (LEED)
Electrons with energies in the 20-500 eV range are diffracted by a crystalline surface; the
diffraction peaks are visualized on a fluorescent screen. This technique probes the long
range order of the surface, up to a depth of several nanometres.
X-Ray Photoelectron Spectroscopy (XPS)
XPS allows both qualitative and quantitative chemical analysis of the elements present on
or near the sample surface.
An X-ray source is used to photoionize the atoms on a surface and produce photoelectrons.
By measuring the kinetic energy of the photoelectrons, the binding energy of the electronic
levels can be calculated. This energy will depend on the chemical environment of the
surface atoms.
Although the soft X-rays used penetrate to a depth of ~2000Å, the sampling depth of the
technique is determined by the mean free path of the photoelectrons which allows their
escape from only the first 10-100Å.
Secondary Ion Mass Spectroscopy (SIMS)
High and low energy ions (primary ions) are used to bombard a sample and remove surface
atoms and ions. The ionic fragments removed (secondary ions) are then analysed by a mass
spectrometer. The surface can be consumed during the measurement and profiles obtained,
giving concentrations of the materials composing the sample at different depths (depth
profiles).
A popular variant of SIMS is TOF-SIMS. In this technique, the secondary ion masses are
measured by a time-of-flight (TOF) measurement. The secondary ions generated by the
bombarding primary ions are accelerated to a constant kinetic energy, and then move
through a field-free space before they reach the detector, where their intensity is measured
as a function of flight time. Since ions with different masses have different velocities at a
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30 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
given kinetic energy, the measured flight times of the ions can easily be converted to their
masses. The static nature of this latter technique allows mass spectroscopy surface analysis
with minimal damage to the surface.
Bibliography
[1] Chen CJ, Introduction To Scanning Tunneling Microscopy (Oxford University Press,
Oxford, 1993)
[2] From www.ibm.com
[3] Tip Sharpening By Normal And Reverse Electrochemical Etching, Fotino M, Review
Of Scientific Instruments 64 (1): 159-167 Jan 1993
[4] A Convenient Method For Removing Surface Oxides From Tungsten STM Tips,
Hockett LA, Creager SE, Review Of Scientific Instruments 64 (1): 263-264 Jan 1993
[5] Confinement Of Electrons In Quantum Corrals On A Metal Surface, Crommie MF,
Lutz CP, Eigler DM, Science 262 (5131): 218-220 Oct 8 1993
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V.Palermo 31
4. Surface modification of silicon in liquid.
Nano-hole creation.
Liquid treatments of silicon wafers are very common in the integrated circuit (IC)
manufacturing industry. They are used to clean and improve surface uniformity, to create
and etch protective oxide layers and to remove photo-resist layers.
Crystalline silicon with its native oxide layer is very stable, and is resistant to many acids.
It is easily attacked by hydrofluoric acid (HF) and alkaline solutions.
The thin (~2 nm), passivating layer of native oxide (SiO2) is formed on exposure to the
atmosphere. This surface layer contains many defects and contaminants, so it is usually
chemically stripped and substituted with a better, chemically-formed protective oxide.
The most common silicon cleaning procedure is the RCA method, named after the Radio
Corporation of America [1]. It consists of two steps: in the first one, the surface is treated
with a hot, alkaline solution (H2O:H2O2:NH4OH, 4:1:1), to remove particles from the
surface; following this, a hot, acidic solution (H2O:H2O2:HCl, 4:1:1) is used to remove
metal contamination. Other well-known cleaning methods are IMEC (a sequence of
cleaning steps in H2O:O3 and dilute HF) or the Pirana etch (a hot 4:1 mixture of H2SO4 :
H2O2).
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32 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
The standard RCA clean removes surface contaminants, etches the native oxide and
oxidizes the silicon surface, leaving a uniform layer of silicon oxide which better protects
the surface from further contamination.
Etching with fluorine-based solutions
Hydrofluoric acid is one of the most common reagents used in the treatment of silicon
wafers, both in the research field and in industrial processes. A rapid dip in dilute HF is the
simplest way to remove the native oxide from Si(100), and leaves the surface passivated by
a layer of Si-H bonds. Because of the low polarization of Si-H bonds, the Si-H layer is
stable even for several days, protecting the surface from contamination. It has often been
assumed that this short etch does not significantly change the surface morphology of the
silicon substrate[2], even though a prolonged dip in dilute HF leads to surface roughening
[3].
Although dilute HF roughens the Si(100) surface at the atomic scale [4,5], immersion in
concentrated HF (49%) etches the surface oxide without attacking the Si surface,
uncovering in this way the buried Si/SiO2 interface. The final, counter-intuitive result is
that dilute HF etches the silicon while concentrated HF leaves the crystalline silicon
untouched. [3]
Etching Si with fluorine-containing solutions at different concentrations and pH can
produce different morphologies, from rough surfaces to flat, nearly ideal Si-H terminated
surfaces.
Hessel et al. and Higashi et al. demonstrated in 1991 that very flat Si(111) surfaces can be
obtained using 40% NH4F, while etching with HF always yields rough surfaces. The
surface becomes smoother because the etchant rapidly attacks Si atoms at step borders,
thus removing surface kinks and irregularities in a step-flow mechanism [6, 7]. Later on,
even smoother and more perfect surfaces were obtained by removing oxygen from the
solution, after it was discovered that oxygen dissolved in 40% NH4F initiates the formation
of triangular etch pits. It was not possible to obtain flat surfaces by etching Si(100) with
ammonium fluoride solutions, which leads to the formation of small 2x1 dimer-row
reconstructed (100) terraces, together with (111) facets [8].
This difference is caused by the different hydride terminations prevailing on the (100) and
(111) faces. While the ideal Si(111)-H surface is monohydride terminated, the more
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V.Palermo 33
reactive dihydrides predominate on the Si(100)-H surface, making it more vulnerable to
etching. The etching reaction is thus strongly anisotropic, etching (100) facets faster than
(111), thus producing (111) microfaceting on Si(100) crystals.
A more uniform Si(100) surface can, however, be prepared by etching at low pH with an
HF/HCl mixture [9], or by using very dilute HF solutions and ultrapure water with low
dissolved oxygen and carbon contents [10].
Electrochemical etching can also be used, applying anodic or cathodic bias to the silicon,
to obtain different morphologies [11]; by varying the potential, isotropic or anisotropic
etching is observed. The aforementioned results show that, despite the simplicity of the
reactants, fluoride etching of silicon is quite a complex reaction.
Fig. 4.1. Chemical etching of silicon
HO+H
H HO
H
H
H
FSi
Si
SiSi
+H2O
-OH-+F-
H2O H H
Si H
F OH
H Si
Si Si
-H2
+H2O
H
H
H
FSi
Si
SiSi
H
H
H
OHSi
Si
SiSi
H
H
H
H Si
Si
Si Si
Etching mechanism of silicon
HF rapidly dissolves the SiO2 passivating layer on silicon, leaving the surface almost
completely hydrogenated [12]. After this, two different types of reactions etch the silicon
simultaneously, one chemical and the other electrochemical [13]. The overall etching
mechanism can be schematized in two stages (see Figure 4.1):
i) Si-H bonds are substituted by Si-F or Si-OH bonds, creating a partial charge on the
surface silicon atom and polarizing its Si-Si backbonds;
ii) these polarised backbonds are then more easily attacked by HF or H2O. After
rupture of the Si-Si bond, the atom is removed leaving behind new Si-H
terminations, and the reaction can start again.
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34 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
These reactions take place, although at different rates, on both Si(100) and Si(111).
Stage i) is usually the rate-determining step of the reaction, and the stability of the Si-H
bonds depends upon the pH, the concentration of nucleophilic species in solution, and an
eventual potential applied to the crystal.
For pH >5, as in the case of concentrated NH4F solutions, reaction begins with attack by
water to give Si-OH (step A→C). The -OH group is rapidly substituted by fluorine, with
polarization of the underlying Si-Si bonds. These bonds are then easily attacked by water,
the silicon atom being released into solution as HSiF(OH)2. The Si-OH → Si-F substitution
is not fundamental for the reaction, and etching can proceed even for Si-OH terminated
atoms, but XPS measurements showed the presence of a certain number of Si-F bonds
remaining. Furthermore, fluorine seems to have a catalytic effect on Si-H substitution, as
indicated by the dependence of the etch rate upon the F- concentration at least for pH
values between 4 and 8.
Si-F bonds can be easily removed by a water rinse. In the case of strongly alkaline
solutions (pH=14), OH- groups act directly as nucleophiles, and no fluorine is needed to
catalyze Si-H bond rupture.
At pH
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V.Palermo 35
electrostatic interactions, by lowering the energy of the interaction step. After the
formation of the Si-OH group, the reaction proceeds as shown in the scheme of fig. 4.1.
Matsumura et al [4] proposed that not only water but HF2- molecules also play a major role
in electrochemical etching of silicon, leaving on the surface Si-F terminated bonds which
can be immediately attacked in an autocatalytic process (fig. 4.3).
In the electrochemical reactions described above, an external potential is applied to the
silicon crystal. The chemical and electrochemical reactions, in any case, take place
simultaneously most of the time, with the chemical path predominating at high pH. Even
when no external potential is applied to the silicon, partial electrochemical reactions can
take place at different “cathodic” and “anodic” sites on the surface with an internal charge
exchange which ensures neutrality [11]. This macroscopic silicon etching and hydrogen
bubble formation can lead to visually observable patterns on the surface when Si(100) is
immersed in ammonium fluoride, even without applying a potential.
Si Si
Si Si
H
H
H
F Si
Si
Si SiH
F F-H+ -2e
+HF2-
H
HF
SiSi
SiSi + F
F F
FH
H
H
F -H+ -2e
+HF2-
Fig.. 4.3. Autocatalytic electrochemical etching of silicon by HF2- .
Inhomogeneities on silicon surfaces caused by electrochemical reactions and charge
transfer have been studied extensively, because they are of fundamental importance in the
formation of porous silicon.
Pore formation on silicon
When Si(100) or Si(111) are etched under anodic bias in fluorine-based solutions,
microscopic pores form on their surface. Several different morphologies of pores have
been observed, with pore diameters ranging from 10 nm to several microns, with depths of
several microns [14]. Pore shape is very variable too, ranging from ordered, straight pores
to chaotic networks of branched pores (fig. 4.4). Porous silicon has been known since the
fifties, but it was only in 1990 that interest in this material increased, following the
discovery that porous silicon layers were able to emit bright, red light. This led to a large
amount of research and now different classes of micropores can be reproducibly created,
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36 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
Fig. 4.4 Different types of Silicon micropores. From ref. [14].
mostly for optical and micromachining applications. However, there is still no unified
theory able to explain the nucleation and growth mechanism of all the different kinds of
pores.
We will give a short description of some of these theories; for more detail, see Parkhutik et
al. [15].
One model explains pore nucleation on the basis of physical processes such as hole
positive charge migration, ion transport to the surface, and small perturbations on the
silicon surface, modelled as Fourier components. The system is shown to be unstable, and
some spatial frequencies that lead to pore nucleation evolve from the etching process.
A second model focusses on stationary pore growth, without explaining the nucleation
stage. According to this model, silicon dissolves preferentially at pore edges because h+
charges are attracted by the stronger electric field present at these edges.
A third class of models explains pore growth as a Diffusion Limited Aggregation (DLA)
process, where the random walk of h+ charge carriers through the depleted layer present at
the silicon-liquid interface controls pore shape.
Finally, the model by Carstensen, Cristophersen and Foll [16], proposes that areas of the
surface of some characteristic size LCO are etched by synchronized “current bursts” in the
flow of h+ charges. These bursts dissolve silicon through cyclic stages of surface oxidation,
oxide removal and hydrogen passivation. Areas where a burst has recently taken place are
less passivated, and thus more likely to be etched again; in this way, the pore bottom
continues to dissolve, while the pore walls are passivated and are thus less favourable areas
towards current bursts.
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V.Palermo 37
EXPERIMENTAL RESULTS
In the following sections, we will show some experimental results obtained from STM and
AFM measurements of fluorine-treated Si(100) surfaces. In the first part, the results of
mild etching, using concentrated and dilute HF solutions at low pH, are presented. In the
second part, the results of etching at high pH using ammonium fluoride are presented, and
the mechanism of pore formation discussed.
Etching of Si(100) in dilute and concentrated HF
Samples were cut from different areas of an 8-inch diameter p-doped silicon(100) wafer
(10 Ω-cm) supplied by MEMC Electronic Materials. Each series of STM measurements
was carried out over at least six different areas on at least two identical samples. Low
Electron Energy Diffraction (LEED) was used to check the surface cleanliness of the
samples before STM measurements.
Table 4.1 summarizes the different treatments of each sample. After etching with
electronic grade HF, each sample underwent a final rinse in Ultra-Pure Water (UPW,
resistivity >18 MΩ-cm). Both the HF and the UPW were allowed to flow continuously
over the sample surface. Some samples were not etched with HF at all but just washed with
UPW to observe the morphology of the native oxide layer (~2 nm thick) covering the
surface. All of these processes were carried out under nitrogen to limit reoxidation and the
samples were then introduced from the nitrogen atmosphere directly into the vacuum
chamber, and degassed overnight at ∼150°C before LEED and STM measurements.
STM images were obtained from each sample using the same measurement parameters
(sample bias 4 V, feedback current 1 nA, scan speed 800 nm s-1). These parameters
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38 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
provided a satisfactory level of reproducibility for all the samples. Measurements were
made over an area of 500x500 nm (image size 500x500 pixel). Slope correction was
carried out by subtracting row-wise and column-wise fitted slopes from the entire image,
which gave better results than the simple subtraction of a fitted plane, especially for the
rougher samples. Following slope correction, the rms roughness:
∑ −=xy
hyxhN
22 )),((
1σ
and the 2-D Fourier transform:
)(22
2
),(4
),( vyuxixy
eyxhvuF +∑∆= ππ
were calculated for each image, where N2 is the number of pixels composing the image,
h(x,y) is the surface height at each point, ∆ is the distance between points, h is the mean
height and u, v are the spatial frequencies. The radial power spectrum PS(f) of the STM image data is obtained from the angular
average of the squared Fourier transform with f 2 = u2 + v2.
Fig. 4.5 shows the STM images obtained from the various samples. Sample A, still covered
with its native oxide layer, shows an irregular surface, with RMS roughness of ~0.5 nm
(see Table 4.1). Observing the sample with LEED gave no diffraction pattern, even at
relatively high incident electron energies, because of the surface oxide coverage. After 1
min etching in dilute HF (sample B), the morphology is similar to the original one, though
Table 4.1. Sample treatments, average RMS roughness and integrated area of power spectra.
Sample Treatment RMS roughness (nm)
PS area (f < 0.1 nm-1)
PS area (f > 0.1 nm-1)
A Rapid dip in water 0.53 ± 0.13 3.66 0.32
B 1 min. in HF 5% + 10 min. in water 0.51 ± 0.08 2.72 0.34
C 30 min. in HF 5% + 10 min. in water 0.62 ± 0.08 10.64 0.38
D 5 sec. in HF 49% + 10 min. in water 0.42 ± 0.04 1.83 0.22
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V.Palermo 39
Fig. 4.5 STM images of each group of samples, showing the topography of the silicon surface. A) noetching, original oxide surface. B) after 1 min etching in dilute HF. C) after 30 min etching in diluteHF. D) after dipping in concentrated HF. Grey scale indicates height of the surface, from lower (black) to higher (white). The images are 250x250 nm, i.e. representative portions of the images usedfor the roughness measurement and PSD analysis.
some of the larger features have disappeared, and the image quality is better, maybe due to
improved tunnelling due to the cleaner surface. The RMS roughness is comparable to that
of the original surface. Clear diffraction patterns are visible using LEED, though at quite
high energies (200 eV). After prolonged etching (sample C), the RMS roughness increases
to 0.62 nm and a long-range corrugation is visible on the surface, even if the LEED pattern
is good.
The samples dipped in concentrated HF (D) reveal the bare Si/SiO2 interface, which has a
disordered aspect and protrusions over a wide range of dimensions. The quality of the
STM images of sample D is very good, probably due to the cleanliness of the surface,
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40 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
1 .E -0 2
1 .E -0 1
1 .E + 0 0
1 .E + 0 1
1 .E + 0 2
1 .E + 0 3
0 .0 0 0 .0 1 0 .1 0 1 .0 0f (1 /nm )
nm^4
A , a s re c e iv e d
B , e tc h e d 1 min
C, e tc h e d 3 0 min
D, e tc h e d HF 4 9 %
Fig. 4.6. Log-Log plot of the averaged power spectra of the STM images for all the samples.
which gives a more stable tunnelling junction. The LEED pattern is excellent, showing
clear diffraction peaks at energies as low as 37 eV, comparable to that obtained after high
temperature cleaning in UHV.
Fig. 4.6 shows the power spectra of the samples. The high frequency and low frequency
areas of the power specturm are considered separately. Table 4.1 shows for each sample,
together with the roughness, the integrated area of the power spectrum for the high and low
frequency part.
We first examine the differences between the samples in the low frequency part of the
spectrum ( 0.15 nm-1. This effect could be due to the
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V.Palermo 41
improved surface cleanliness after etching with concentrated HF, which would give a more
stable STM junction thus reducing the high frequency noise in the image.
Fig. 4.5 and the analysis of the power spectrum of each sample shows that a rapid dip in
HF removes the native oxide but does not lead to major changes in the morphology of the
Si surface, its only effect being the removal of some of the larger features present on the
original surface. Prolonged etching, on the other hand, increases the RMS roughness of the
surface.
Etching of Si(100) in concentrated ammonium fluoride and nano-hole creation
Two different types of commercial p-doped Si(100) wafers (2Ω-cm and 10Ω-cm) from
MEMC were used. Several different samples of 10x5 mm were immersed for 10 minutes
in 40% electronic grade NH4F solution under agitation. Previous works used low
temperatures or anodic potentials applied to the silicon to avoid gaseous hydrogen
production and to obtain a uniform surface, but in our experiment we worked at room
temperature to check the influence of hydrogen bubbles on surface morphology. During
the etching, the stirring was sufficient to provide a uniform concentration of reagents over
the whole sample surface, but not to mechanically remove the hydrogen bubbles from the
silicon surface.
After the etching, each sample was rinsed in ultra-pure water to remove any etching
residues, and observed with STM, AFM and optical microscopy. The AFM measurements
were made in air, while for STM measurements the samples were rapidly dried with
nitrogen and inserted into the vacuum system to avoid surface reoxidation. After insertion
into the vacuum, surface cleanliness was checked with LEED, and the surface morphology
observed by STM. Parameters for STM measurements were sample bias +4 V, 1 nA
current, 1.6 Hz scan rate. The images obtained were stable and reproducible over several
days. Scan parameters for AFM were 20 nN force and 1 Hz scan rate.
Some of the samples were cleaned with an RCA standard clean [1] before NH4F etching, to
check the influence of possible surface contaminants on the final results. Eight different
samples were prepared and more than sixty STM images of the samples were taken at
different points of the various samples.
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42 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
(110)
(110)
Fig.4.7. a,b,c) STMtopographic images of differentetching morphologies. Eachimage is 500x500 nm. Z-ranges are 10, 10 and 18 nmrespectively. d) STM image of a bridgecreated by etching of the lowerlayers of silicon (black arrow).Image is 250x250x6 nm.
After ~2 min of immersion in the solution, hydrogen bubbles become visible on the sample
surface. The production is slow and the bubbles are quite stable on the sample without
detaching. Thus, some areas of the surface are masked from the liquid etching action.
STM observations (fig. 4.7) show that, at the nanometer scale, the surface is unevenly
covered with holes of radii ranging from 10 to 200 nm, with depths of 2-4 nm. These holes
have a wide range of different shapes and distributions. In most cases the surface was
covered with a uniform distribution of round-shaped holes (fig.4.7a), indicating isotropic
etching. The dimension and the density of the holes changed greatly from sample to
sample and even over the surface of a single sample. In some cases the etching was
anisotropic, yielding nearly square holes and layered structures, as shown in fig. 4.7b.
Square holes have been previously observed in cases where the etching speed in the (110)
direction is significantly smaller than in the (100) direction [17].
Over these areas (fig 4.7b and especially 4.7c) it is clearly visible how, once the surface
had been attacked, the reaction continued to preferentially remove atoms at step
irregularities (kink atoms), straightening step edges. Eventually, the exposed underlying
silicon was also attacked, and further holes created inside the previously etched larger
ones. It was not possible to detect monatomic steps on this kind of surface. The smallest
step height observed was ~1.5 nm, corresponding to several atomic layers. In the image
shown in Figure 4.7a the etching was not strong and created only anisotropic holes on the
surface. In fig. 4.7b and c the stronger etch proceeded laterally for several tens of
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V.Palermo 43
nanometres, leaving straight steps several tens of nanometers long, and roughly rectangular
holes, as expected, given the structure of the (100) crystal face. In some cases, a
significative underetch is observed, and the formation of suspended bridges and tunnels
can be deduced from the STM images (fig. 4.7d)
The formation of branched pores and suspended structures has been attributed, during pore
formation, to diffusion limited aggregation effects, where the h+ charge carriers necessary
for silicon etching have a higher probability of reacting at pore bottoms than reaching the
upper part of the silicon surface. In the case of very deep pores, quantum wire effects have
been invoked to explain the pore growth mechanism [15]. In our case, though, the pores
formed were very shallow, the underetch depth being only a few nanometres on pores of
∼100 nm width. Thus, more than diffusion effects, the main contribution to the
underetching process must come from anisotropic etching and some kind of autocatalytic
reaction path, analogous to the one described by Matsumura et al. [4], with some areas of
the silicon surface hydrogenated and thus less vulnerable to etching.
Pre-treatment with RCA cleaning has no effect on the final morphology, and this seems to
exclude pore nucleation being caused by presence of metallic or organic surface
contaminants.
The morphology and the distribution density of the pits was quite uniform over
microscopic areas of the sample but changes were observed over the millimetre scale. This
suggests that etching intensity is influenced by some large-scale parameter.
Large-area measurements made with AFM or with an optical microscope (fig. 4.8),
showed that the inhomogeneity of surface etching can be correlated with the masking
action of the bubbles. While the fluoride dissolved the silicon, hydrogen bubbles formed
by the reaction covered some areas of the surface thus blocking the etching over that area,
generating macroscopic steps at the bubble-liquid border. As the reaction proceeded, more
hydrogen accumulated and the bubble diameter increased, producing in this way a circular
pattern of steps. The increase in bubble diameter was not continuous with time, otherwise a
uniform surface slope gradient would have been obtained. The formation of this circular
“etching staircase” indicates that the bubble growth was stepwise, the bubble accumulating
more and more hydrogen without enlarging across the surface, until it relaxed, increasing
its diameter stepwise and covering more silicon. The circular structures in fig. 4.8a are not
co-axial and their asymmetry could derive from physical processes due to stirring or
irregularities on the surface.
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44 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
a b Fig. 4.8. a) optical micrograph of etching patterns on Si(100) created by NH4F, 1.2x0.9 mm. b) AFM image of the circles border. xy range is 40x24 µm. z-range is 30 nm.
The step structure was not destroyed by the etching even after the bubble detached from
the surface but, on the contrary, the etching process seemed to be influenced by the
presence of the step.
Observing in detail a series of steps (fig. 4.8b), a quite deep trench is visible at the base of
each step. A close-up image of a step and the corresponding line profile of the trench is
shown in fig. 4.9. The trench is ∼5 nm deep with respect to the lower surface, compared to
a step height of 2.2 nm.
A similar structure has been recently obtained with electrochemical etching of p-type
Si(100) in 4% HF, [18] in which a “current burst” etching model, previously described,
was assumed for silicon dissolution. In that experiment, the trench was created at the
border of silicon nitride masks, and began to grow after a nucleation stage. Preferential
trench etching was along the (110) direction, and the trench growth was explained as an
effect of mechanical stress induced by the nitride mask and of electric field enhanced
dissolution which depended upon an external applied potential.
While it is clear that in our system the gas bubbles have a masking effect similar to a
classical, solid nitride mask, it is unlikely that hydrogen present on the surface can induce a
significant stress in the silicon lattice as in the case of a nitride mask. Furthermore, no
external field was applied to drive preferential etching at the trench site.
It has been proposed [19] that the cathodic and anodic part of the etching reaction
(hydrogen production and silicon oxidative etching, respectively) take place at different
points on the surface, with a net charge transfer between the different areas. In this case,
the highest reaction rates will correspond to the silicon area surrounding the bubble border,
where a high number of positive charges will be available for the reaction. Furthermore, a
sharp trench extending into the silicon crystal will be a preferential electrostatic attractor
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V.Palermo 45
Fig. 4.9. AFM image of the etched surface, showing a step created on the surface by bubblemasking. A stronger etching action is visible on the right side of the step, as well as theprotected area on the upper side of the step (indicated by the arrows). Image is 10x10 µm,z-range is 30 nm. The profile on the right is taken from the central area of the image.
for the h+ charge carriers coming from other “cathodic areas” of the sample, either from
other regions on the surface or from the back of the silicon chip [18].
In the areas where the hydrogen bubble had detached and the surface was exposed to the
etching, the reaction was not uniform in the neighbourhood of the steps. It is possible to
observe (fig. 4.8b and 4.9) an area on the upper side of the step where less or even no
etching at all seems to have taken place, as if the step was able to protect the surface from
etching. While etching on the lower side with trench formation can be attributed to the
presence of the bubble, the surface on the upper step side can be etched only after bubble
detachment, so no masking effect can account for this result. However, a further
preferential attraction of h+ charge carriers from the already formed trench can be
hypothised, electrochemically shielding the surrounding area from further etching. If this is
true, the shielding effect would be very strong, with a relatively shallow 5 nm-deep trench
protecting an area of ∼1 µm parallel to the step.
To summarise, the etching of Si(100) in NH4F is a complex process, in which different
reaction paths, both chemical and electrochemical, co-exist. Hydrogen bubbles formed by
the reaction act as a mask on the surface, and create etching paths and inhomogeneous
etching of the surface. Different kinds of pores are observed on the surface, and in some
cases the anisotropy of the process is so strong as to give square-shaped holes and
underetching.
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46 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
The diffusion of h+ charge carriers in the crystal is one of the main rate-determining steps
of the reaction, and leads to the formation of a deep trench immediately outside the bubble
perimeter. These trenches act as charge collectors, and reduce the etching of the upper step
surface in the proximity of the steps.
Bibliography
[1] The Evolution Of Silicon-Wafer Cleaning Technology, Kern W, Journal Of The
Electrochemical Society 137 (6): 1887-1892 Jun 1990.
[2] Spectroscopic Ellipsometry Studies Of HF Treated Si (100) Surfaces, Yao H, Woollam
Ja, Alterovitz SA, Applied Physics Letters 62 (25): 3324-3326 Jun 21 1993; Influence
Of HF-H2O2 Treatment On Si(100) And Si(111) Surfaces, Graf D, Bauermayer S,
Schnegg A, Journal Of Applied Physics 74 (3): 1679-1683 Aug 1 1993; Kinetics Of
Oxidation On Hydrogen-Terminated Si(100) And (111) Surfaces Stored In Air, Miura
T, Niwano M, Shoji D, Miyamoto N, Journal Of Applied Physics 79 (8): 4373-4380
Part 1 Apr 15 1996.
[3] Hydrogen On Si - Ubiquitous Surface Termination After Wet-Chemical Processing,
Pietsch GJ Applied Physics A-Materials Science & Processing 60 (4): 347-363 Apr
1995; Structure Of The Stepped Si/SiO2 Interface After Thermal-Oxidation -
Investigations With Scanning Tunneling Microscopy And Spot-Profile Analysis Of
Low-Energy Electron-Diffraction, Pietsch GJ, Kohler U, Jusko O, Henzler M, Hahn
PO, Applied Physics Letters 60 (11): 1321-1323 Mar 16 1992
[4] Enhanced Etching Rate Of Silicon In Fluoride Containing Solutions At pH 6.4,
Matsumura M, Fukidome H, Journal Of The Electrochemical Society 143 (8): 2683-
2686 Aug 1996.
[5] A Study Comparing Measurements Of Roughness Of Silicon And SiO2 Surfaces And
Interfaces Using Scanning Probe Microscopy And Neutron Reflectivity, Crossley A,
Sofield CJ, Goff JP, Lake ACI, Hutchings MT, Menelle A, Journal Of Non-Crystalline
Solids 187: 221-226 Jul 1995.
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V.Palermo 47
[6] Step-Flow Mechanism Versus Pit Corrosion - Scanning-Tunneling Microscopy
Observations On Wet Etching Of Si(111) By Hf Solutions, Hessel HE, Feltz A, Reiter
M, Memmert U, Behm RJ, Chemical Physics Letters 186 (2-3): 275-280 Nov 8 1991
[7] Comparison Of Si(111) Surfaces Prepared Using Aqueous-Solutions Of NH4F Versus
HF, Higashi GS, Becker RS, Chabal YJ, Becker AJ, Applied Physics Letters 58 (15):
1656-1658 Apr 15 1991
[8] Wet Chemical Etching Of Si(100) Surfaces In Concentrated NH4F Solution -
Formation Of (2x1)H Reconstructed Si(100) Terraces Versus (111) Faceting, Neuwald
U, Hessel HE, Feltz A, Memmert U, Behm RJ, Surface Science 296 (1): L8-L14 Oct
10 1993
[9] Ideal Hydrogen Termination Of Si(001) Surface By Wet-Chemical Preparation, Morita
Y, Tokumoto H, Applied Physics Letters 67 (18): 2654-2656 Oct 30 1995.
[10] Atomic Structures Of Hydrogen-Terminated Si(001) Surfaces After Wet Cleaning
By Scanning Tunneling Microscopy, Endo K, Arima K, Kataoka T, Oshikane Y, Inoue
H, Mori Y, Applied Physics Letters 73 (13): 1853-1855 Sep 28 1998.
[11] On The Potential-Dependent Etching Of Si(111) In Aqueous NH4F Solution
Houbertz R, Memmert U, Behm RJ, Surface Science 396 (1-3): 198-211 Jan 20 1998
[12] Etching Process Of SiO2 By HF Molecules, Hoshino T, Nishioka Y Journal Of
Chemical Physics 111 (5): 2109-2114 Aug 1 1999.
[13] Etching Mechanism And Atomic-Structure Of H-Si(111) Surfaces Prepared In
NH4F, Allongue P, Kieling V, Gerischer H, Electrochimica Acta 40 (10): 1353-1360
Jul 1995.
[14] Pore Formation Mechanisms For The Si-HF System, Carstensen J, Christophersen
M, Foll H, Materials Science And Engineering B-Solid State Materials For Advanced
Technology 69: 23-28 Sp. Iss. Si Jan 19 2000
[15] Porous Silicon - Mechanisms Of Growth And Applications, Parkhutik V, Solid-
State Electronics 43 (6): 1121-1141 Jun 1999
[16] Formation And Application Of Porous Silicon, Foll H, Christophersen M,
Carstensen J, Hasse G, Materials Science & Engineering R-Reports 39 (4): 93-141 Nov
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[17] Pore Morphology And The Mechanism Of Pore Formation In N-Type Silicon,
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48 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
[18] Deep Electrochemical Trench Etching With Organic Hydrofluoric Electrolytes,
Christophersen M, Merz P, Quenzer J, Carstensen J, Foll H, Sensors And Actuators A-
Physical 88 (3): 241-246 Mar 5 2001.
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V.Palermo 49
5. Surface modification of silicon in vacuum; void creation and oxide desorption
The main reason for the huge success of silicon in the microelectronics industry is not due
to its superior properties as a semiconductor. Other materials, for example germanium,
have better qualities, such as higher mobility of charge carriers and lower noise levels,
which would allow the construction of faster and higher performance devices.
The widespread use of silicon, however, is mainly due to the outstanding characteristics of
its oxide. Silicon dioxide (SiO2) is a very good electrical insulator, easy to form,
chemically and thermally stable and is compatible with lithographic and metal deposition
processes. Germanium oxide, on the contrary, is too reactive to be used.
Even the use of Si(100) substrates for nearly all microelectronic devices is dictated by
oxide quality. The (111) face of silicon crystal can be easily cleaved and flattened, and
almost atomically perfect surfaces can be obtained with simple chemical procedures (as
described above). But the density of interfacial defects is highest for Si(111)-SiO2
interfaces, and lowest for Si(100)-SiO2 ones, so microchips will continue to be fabricated
on Si(100) wafers.
SiO2 (silica) is present in 95% of the earth’s minerals, in different allotropic forms such as
quartz, tridymite, and cristobalite. In the bulk, each silicon atom is bonded to four oxygens,
in a Si-O-Si tri-dimensional network. Si-O bonds are 0.16 nm long and form an angle
ranging from 120° to 150°.
Three typical intrinsic defects are present in SiO2. The so-called E’ centres are oxygen
vacancies, with a hole localised on a silicon atom with only three Si-O bonds,
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50 Creation of Nanometre-Scale Islands, Wires and Holes on Silicon Surfaces for Microelectronics
O3Si· +SiO3, Whereas the PR (peroxy radical) defects are holes trapped by a charged
peroxy moiety, with a O3Si-O-O+ ·SiO3 structure. The NBOHC (non-bridging oxygen hole
centres) derive from water or hydrogen contamination, and are schematized as O3Si- O- H-
O-SiO3 .
The atomic structure of the Si-SiO2 interface varies enormously. Local domains resembling
the tridymite and the cristobalite structure of silica are present, but it seems that only 10%
of the interface is ordered [1]. Far from the interface, the SiO2 bulk is completely
disordered. The passage from bulk Si to stoichiometric SiO2 passes through a non-
stoichiometric SiOx layer 0.7 nm thick.
When a clean silicon surface is exposed to atmospheric oxygen, a thin, ∼2 nm thick layer
of native oxide forms spontaneously which is usually removed and substituted with
thicker, better quality oxide layers before further processing.
Silicon is usually oxidised by thermal annealing, at temperatures between 800° and 1100°,
in an atmosphere of pure O2 with some water eventually added to increase oxidation speed.
Thermal oxides made in pure oxygen (dry oxides) grow more slowly than oxides produced
in an oxygen-water atmosphere (wet oxides), but are usually of better quality.
According to the Deal-Groove formula, the time t needed to grow an oxide of thickness X
is given by [1]:
1
212−
−−
+=
ABXBXt α
where the constant B and B/A decrease exponentially with temperature as
−
kTEexp ,
with activation energies for dry oxidation of EB =1.23 and EB/A =2.0 eV respectively.
EB is related to the diffusion of oxygen in silicon, while the value of EB/A is interpreted as
the energy required to break a Si-Si bond. The exponent α is 1 for wet oxidation, and 0 for
oxidation at high temperatures and low oxygen pressures. It has intermediate values for dry
oxidation. This formula does not work well for low values of X, at the initial stages of
oxidation, and usually empirical corrections are used.
An interesting characteristic of silicon is that, at high temperature and in vacuum, oxygen
can actually etch the silicon crystal giving gaseous products, and the oxidized layer present
on the crystal becomes unstable (fig. 5.1) [2].
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V.Palermo 51
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
0.60.70.80.911.11.2
1000/T (1/K)
P (T
orr)
SiO2 + Si → 2SiO(g) Oxide decomposition
Si+O2 → SiO2(s) oxide formation Fig.5.1. phase diagram of the oxygen-silicon system.
Silicon oxidation, apart from the initial nucleation stages at the monolayer level, proceeds
uniformly over the whole surface, with a planar reaction front moving from the surface
into the bulk.
If heated under low oxygen partial pressure (vacuum or inert atmosphere), SiO2 is known to
decompose following the reaction:
SiO2 + Si → 2SiO↑ (1)
The reaction begins with nucleation at defect points on the Si/SiO2 interface and proceeds
in a spatially inhomogeneous manner, with the formation of large voids on the oxide
surface [3].
Several studies have been made on the dynamics of void growth both on thick [4] and thin
[5] layers of SiO2 . The process has been used to decorate otherwise unobservable defects at
the Si/SiO2 interface [6], or to grow nanoislands of silicon on the void surface [7]. It has
been suggested that the defects acting as nucleation centres could be metallic contaminants
present on the native surface, which aggregate and catalyze SiO2 decomposition [8].
After oxide desorption, the silicon surface is very rough. In particular, on Si(100) square
islands are observed, several nanometres high, which act as ‘pinning sites’ on the motion of
monatomic steps