CPU-IOP Communication

In most cases the memory unit acts as a message center where each processor leaves information for the other.

The sequence of operations may be carried out as shown in the flow-chart.

Fig: CPU-IOP Communication. The CPU sends an instruction to test the IOP path. The IOP

responds by inserting a status word in memory for the CPU to check.

The bits of the status word indicate the condition of the IOP and I/O device, such as IOP overload, condition, device busy with another transfer, or device ready for I/O transfer.

The CPU refers to the status word in memory to decide what to do next.

CPU Operations IOP Operations

continue

Send instruction to test IOP path

If status OK, send start I/O instruction to IOP

CPU continues with another program

Request IOP status

Check status word for correct transfer

Transfer status word to memory location

Access memory for IOP program

Conduct I/O transfer using DMA; prepare status report

I/O transfer completed;Interrupt CPU

Transfer status word to memory location

PRIORITY INTERRUPTPriority

- Determines which interrupt is to be served first when two or more requests are made simultaneously

- Also determines which interrupts are permitted to interrupt the computer while another is being serviced

- Higher priority interrupts can make requests while servicing a lower priority interrupt

Priority Interrupt by Software(Polling) Priority is established by the order of polling the devices (interrupt sources)Flexible since it is established by softwareLow cost since it needs a very little hardware Very slow

Priority Interrupt by Hardware Require a priority interrupt manager which accepts all the interrupt requests to determine the highest priority request Fast since identification of the highest priority interrupt request is identified by the hardware Fast since each interrupt source has its own interrupt vector to access directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

The hardware priority function can be established by either a serial or a parallel connection of interrupt lines.The serial connection is also known as daisy chaining method.The CPU responds to an interrupt request by enabling the interrupt acknowledge line. This signal is received by device 1 at its PI(priority in) input. The acknowledge signal passes on to the next device through the PO(priority out) output only if device 1 in not requesting an interrupt.If the device 1 has a pending interrupt, it blocks the acknowledge signal from the next device by placing a 0 in the PO output.It then proceeds to insert its own interrupt vector address(VAD) into the data bus for the CPU to use during the interrupt cycle.

Priority Interrupt

Device 1PI PO

Device 2PI PO

Device 3PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To nextdevice

CPU

VAD 1 VAD 2 VAD 3Processor data bus

* Serial hardware priority function* Interrupt Request Line

- Single common line* Interrupt Acknowledge Line

- Daisy-Chain

A device with a 0 in its PI input register generates a 0 in its PO output to inform the next-lower priority device that the acknowledge signal has been blocked.

A device that is requesting an interrupt and has a 1 in its PI input will interrupt the acknowledge signal by placing a 0 in its PO output.

If the device does not have pending interrupts, it transmits the acknowledge signal to the next device by placing a 1 in its PO output.

Thus the device with PI=1 and PO=0 is the one with the highest priority that is requesting an interrupt, and this device places its VAD on the data bus.

PARALLEL PRIORITY INTERRUPT

IEN: Set or Clear by instructions ION or IOFIST: Represents an unmasked interrupt has occurred. INTACK enables

tristate Bus Buffer to load VAD generated by the Priority Logic

Interrupt Register: - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instructionMask Register: - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

Priority Interrupt

Maskregister

INTACKfrom CPU

Priorityencoder

I 0

I 1

I 2

I 3

0

1

2

3

y

x

ISTIEN0

1

2

3

0

0

0

0

0

0

Disk

Printer

Reader

Keyboard

Interrupt register

Enable

Interruptto CPU

VADto CPU

BusBuffer