cpu design. cs252/culler lec 1.2 1/22/02 levels of representation (61c review) high level language...
TRANSCRIPT
CPU Design
CS252/CullerLec 1.2
1/22/02
Levels of Representation (61C Review)
High Level Language Program
Assembly Language Program
Machine Language Program
Control Signal Specification
Compiler
Assembler
Machine Interpretation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw $15,0($2)
lw $16,4($2)
sw $16,0($2)
sw $15,4($2)
0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
°°
ALUOP[0:3] <= InstReg[9:11] & MASK
CS252/CullerLec 1.3
1/22/02
Execution Cycle
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
Obtain instruction from program storage
Determine required actions and instruction size
Locate and obtain operand data
Compute result value or status
Deposit results in storage for later use
Determine successor instruction
4
Edge triggered D Flip-Flop
Clk
D
Q
Q
QSET
CLR
D
Clk
Output changes only on the rising edge of the clock
CS252/CullerLec 1.5
1/22/02
What’s a Clock Cycle?
• Old days: 10 levels of gates• Today: determined by numerous time-
of-flight issues + gate delays– clock propagation, wire lengths, drivers
Latchor
register
combinationallogic
In-Out control
Q
QSET
CLR
DDout
Din
• Instruction 00
??
???
00
IR
???
ALU
Ctrl
+1
PC
Out In
Beginning, Program & Data in MemoryReset counter, the Machine in a random state ….
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 00011 000
00
901
00
???
???
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 00011 000
Instruction Fetch (1) ...
PC MAR, Read
IR
00
901
01
901
???
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 00011 000
Instruction Fetch (2) ...
MDR IR, PC1
IR
A B
00
901
01
901
102
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 00011 000
Instruction Execute ...
In Accu
IR
A B
102
12
Next instruction: 01
13
01
310
01
901
102
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 00011 000
Instruction Fetch (1) ...
PC MAR, Read
IR
14
01
310
02
310
102
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 00011 000
Instruction Fetch (2) ...
MDR IR, PC1
IR
A B
15
10
102
02
310
102
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 000
Instruction Execute ...
IR[adr] MAR, Accu MDR,Write
IR
A B
ACCU
16
Next instruction: 02
17
02
901
02
310
102
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 000
Instruction Fetch (1) ...
PC MAR, Read
IR
18
02
901
03
901
102
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 000
Instruction Fetch (2) ...
MDR IR, PC1
IR
A B
19
02
901
03
901
304
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 00011 000
Instruction Execute ...
In Accu
IR
A B
304
20
Next instruction: 03
21
03
311
03
901
304
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 000
Instruction Fetch (1) ...
PC MAR, Read
IR
22
03
311
04
311
304
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 000
Instruction Fetch (2) ...
MDR IR, PC1
IR
A B
23
11
304
04
311
304
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
IR
A B
ACCU
Instruction Execute ...
IR[adr] MAR, Accu MDR,Write
24
Next instruction: 04
25
04
210
04
311
304
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Fetch (1) ...
PC MAR, Read
IR
26
04
210
05
210
304
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Fetch (2) ...
MDR IR, PC1
IR
A B
27
10
102
05
210
304
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Execute (1) ...IR[adress] MAR , Read
IR
A B
ACCU
28
10
102
05
210
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Execute (2) ...ACCU - MDR ACCU
IR
A B
ACCU
304
29
Next instruction: 05
30
05
808
05
210
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Fetch (1) ...
PC MAR, Read
IR
31
05
808
06
808
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Fetch (2) ...
MDR IR, PC1
IR
A B
32
05
808
08
808
102
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Execute ...(acc ≥ 0 IR[adress] PC)
IR
A B
ACCU
33
Next instruction: 08
34
08
902
08
808
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Fetch (1) ...PC MAR, Read
IR
35
08
902
09
902
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Fetch (2) ...MDR IR, PC1
IR
A B
36
08
902
09
902
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Execute ...ACCU OUT
IR
A B
ACCU
202
37
Next instruction: 09
38
09
000
09
902
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Fetch (1) ...PC MAR, Read
IR
39
09
000
10
000
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Fetch (2) ...MDR IR, PC1
IR
A B
40
09
000
10
000
202
ALU
Ctrl
+1
PC
Out In
MAR
MDR
00 90101 31002 90103 31104 21005 80806 51007 21108 90209 00010 10211 304
Instruction Execute ...HLT
IR
A B
ACCU