cpsc 121: models of computation 2012 summer term 2

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CPSC 121: Models of Computation 2012 Summer Term 2. Building & Designing Sequential Circuits Steve Wolfman, based on notes by Patrice Belleville and others. Outline. Prereqs, Learning Goals, and Quiz Notes Problems and Discussion A Pushbutton Light Switch - PowerPoint PPT Presentation

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Page 1: CPSC 121: Models of Computation 2012 Summer Term 2

snick

snack

CPSC 121: Models of Computation2012 Summer Term 2

Building & Designing Sequential Circuits

Steve Wolfman, based on notes by Patrice Belleville and others

1

Page 2: CPSC 121: Models of Computation 2012 Summer Term 2

Outline

• Prereqs, Learning Goals, and Quiz Notes

• Problems and Discussion– A Pushbutton Light Switch– Memory and Events: D Latches & Flip-Flops– General Implementation of DFAs

(with a more complex DFA as an example)– How Powerful are DFAs?

• Next Lecture Notes

2

Page 3: CPSC 121: Models of Computation 2012 Summer Term 2

Learning Goals: Pre-Class

We are mostly departing from the readings to talk about a new kind of circuit on our way to a full computer: sequential circuits.

The pre-class goals are to be able to:– Trace the operation of a deterministic finite-

state automaton (represented as a diagram) on an input, including indicating whether the DFA accepts or rejects the input.

– Deduce the language accepted by a simple DFA after working through multiple example inputs.

3

Page 4: CPSC 121: Models of Computation 2012 Summer Term 2

Learning Goals: In-Class

By the end of this unit, you should be able to:– Translate a DFA to a corresponding sequential

circuit, but with a “hole” in it for the circuitry describing the DFA’s transitions.

– Describe the contents of that “hole” as a combinational circuitry problem (and therefore solve it, just like you do other combinational circuitry problems!).

– Explain how and why each part of the resulting circuit works.

4

Page 5: CPSC 121: Models of Computation 2012 Summer Term 2

Where We Are inThe Big Stories

Theory

How do we model computational systems?

Now: With our powerful modelling language (pred logic), we can prove things like universality of NOR gates for combinational circuits.

Our new model (DFAs) are sort of full computers.

Hardware

How do we build devices to compute?

Now: Learning to build a new kind of circuit with

memory that will be the key new feature we need to build full-blown computers!

(Something you’ve seen in lab from a new angle.)

5

Page 6: CPSC 121: Models of Computation 2012 Summer Term 2

Outline

• Prereqs, Learning Goals, and Quiz Notes

• Problems and Discussion– A Pushbutton Light Switch– Memory and Events: D Latches & Flip-Flops– General Implementation of DFAs

(with a more complex DFA as an example)– How Powerful are DFAs?

• Next Lecture Notes

6

Page 7: CPSC 121: Models of Computation 2012 Summer Term 2

Problem: Push-Button Light Switch

Problem: Design a circuit to control a light so that the light changes state any time its “push-button” switch is pressed.

(Like the light switches in Dempster: Press and release, and the light changes state. Press and release again, and it changes again.)

??

7

Page 8: CPSC 121: Models of Computation 2012 Summer Term 2

A Light Switch “DFA”

light off

light on

pressed

pressed

This Deterministic Finite Automaton (DFA) isn’t really about accepting/rejecting; its current state is the state of the light.

??

8

Page 9: CPSC 121: Models of Computation 2012 Summer Term 2

Problem: Light Switch

Problem: Design a circuit to control a light so that the light changes state any time its “push-button” switch is pressed.

Identifying inputs/outputs: consider these possible inputs and outputs:

Input1: the button was pressedInput2: the button is downOutput1: the light is onOutput2: the light changed states

Which are most useful for this problem?

a.Input1 and Output1

b.Input1 and Output2

c.Input2 and Output1

d.Input2 and Output2

e.None of these9

??

Page 10: CPSC 121: Models of Computation 2012 Summer Term 2

COMPARE TO: Lecture 2’s Light Switch

Problem: Design a circuit to control a light so that the light changes state any time its switch is flipped.

??

Identifying inputs/outputs: consider these possible inputs and outputs:

Input1: the switch flippedInput2: the switch is onOutput1: the light is onOutput2: the light changed states

Which are most useful for this problem?

a.Input1 and Output1

b.Input1 and Output2

c.Input2 and Output1

d.Input2 and Output2

e.None of these10

Page 11: CPSC 121: Models of Computation 2012 Summer Term 2

Outline

• Prereqs, Learning Goals, and !Quiz Notes

• Problems and Discussion– A Pushbutton Light Switch– Memory and Events: D Latches & Flip-Flops– General Implementation of DFAs

(with a more complex DFA as an example)– How Powerful are DFAs?

• Next Lecture Notes

11

Page 12: CPSC 121: Models of Computation 2012 Summer Term 2

Departures from Combinational Circuits

MEMORY:We need to “remember” the light’s state.

EVENTS:We need to act on a button push rather than in response to an input value.

12

Page 13: CPSC 121: Models of Computation 2012 Summer Term 2

Problem: How Do We Remember?

We want a circuit that:• Sometimes… remembers its current state.• Other times… loads a new state to remember.

13Sounds like a choice.

What circuit element do we have for modelling choices?

Page 14: CPSC 121: Models of Computation 2012 Summer Term 2

Worked Problem: “Muxy Memory”

How do we use a mux to store a bit of memory? We choose to remember on a control value of 0 and to load a new state on a 1.

0

1output

???

new data

control14

We use “0” and “1” because that’s how MUXes are usually labelled.

Page 15: CPSC 121: Models of Computation 2012 Summer Term 2

Worked Problem: Muxy Memory

How do we use a mux to store a bit of memory? We choose to remember on a control value of 0 and to load a new state on a 1.

0

1output (Q)

old output (Q’)

new data (D)

control (G)

This violates our basic combinational constraint: no cycles.15

Page 16: CPSC 121: Models of Computation 2012 Summer Term 2

Truth Table for “Muxy Memory”

Fill in the MM’s truth table:

G D Q'

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

a. b. c. d. e.Q

0

1

0

1

0

1

0

1

Q

0

1

0

1

0

0

1

1

Q

0

1

0

1

0

X

X

1

Q

0

0

0

1

1

1

0

1

None of

these

16

Page 17: CPSC 121: Models of Computation 2012 Summer Term 2

Worked Problem: Truth Table for “Muxy Memory”

Worked Problem: Write a truth table for the MM: G D Q' Q

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

Like a “normal” mux table, but what happens when Q' Q?17

Page 18: CPSC 121: Models of Computation 2012 Summer Term 2

Worked Problem: Truth Table for “Muxy Memory”

Worked Problem: Write a truth table for the MM: G D Q' Q

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

Q' “takes on” Q’s value at the “next step”.18

Page 19: CPSC 121: Models of Computation 2012 Summer Term 2

“D Latch” Symbol + Semantics

We call a “muxy memory” a “D latch”.

When G is 0, the latch maintains its memory.

When G is 1, the latch loads a new value from D.

0

1output (Q)

old output (Q’)

new data (D)

control (G) 19

Page 20: CPSC 121: Models of Computation 2012 Summer Term 2

D Latch Symbol + Semantics

When G is 0, the latch maintains its memory.

When G is 1, the latch loads a new value from D.

0

1output (Q)

old output (Q’)

new data (D)

control (G) 20

Page 21: CPSC 121: Models of Computation 2012 Summer Term 2

D Latch Symbol + Semantics

When G is 0, the latch maintains its memory.

When G is 1, the latch loads a new value from D.

output (Q)

new data (D)

control (G)

D

G

Q

21

Page 22: CPSC 121: Models of Computation 2012 Summer Term 2

Hold On!!

Why does the D Latch have two inputs and one output when the mux inside has THREE inputs and one output?

a. The D Latch is broken as is; it should have three inputs.

b. A circuit can always ignore one of its inputs.

c. One of the inputs is always true.

d. One of the inputs is always false.

e. None of these (but the D Latch is not broken as is).

22

Page 23: CPSC 121: Models of Computation 2012 Summer Term 2

Using the D Latch for Circuits with Memory

Problem: What goes in the cloud? What do we send into G?

D

GQ Combinational

Circuit to calculatenext state

input

??

23

We assume we just want Q as the output.

Page 24: CPSC 121: Models of Computation 2012 Summer Term 2

Using the D Latch for Our Light Switch

Problem: What do we send into G?

D

GQ

no (0 bit) input output

??

current light state

a. T if the button is down, F if it’s up.b. T if the button is up, F if it’s down.c. Neither of these. 24

Page 25: CPSC 121: Models of Computation 2012 Summer Term 2

A Timing Problem:We Need EVENTS!

Problem: What do we send into G?

D

GQ

output

“pulse” when

button is pressed

current light state

button pressed

As long as the button is down, D flows to Q flows through the NOT gate and back to D...

which is bad!25

Page 26: CPSC 121: Models of Computation 2012 Summer Term 2

A Timing Problem, Metaphor(from MIT 6.004, Fall 2002)

What’s wrong with this tollbooth?

P.S. Call this a “bar”, not a “gate”, or we’ll tie ourselves in (k)nots.

26

Page 27: CPSC 121: Models of Computation 2012 Summer Term 2

A Timing Solution, Metaphor(from MIT 6.004, Fall 2002)

Is this one OK?

27

Page 28: CPSC 121: Models of Computation 2012 Summer Term 2

A Timing Problem

Problem: What do we send into G?

D

GQ

output

“pulse” when

button is pressed

current light state

button pressed

As long as the button is down, D flows to Q flows through the NOT gate and back to D...

which is bad!28

Page 29: CPSC 121: Models of Computation 2012 Summer Term 2

A Timing Solution (Almost)

D

GQ

output

button pressed

D

GQ

Never raise both “bars” at the same time.

29

Page 30: CPSC 121: Models of Computation 2012 Summer Term 2

A Timing Solution

D

GQ

output

D

GQ

??

The two latches are never enabled at the same time (except for the moment needed for the NOT gate on the left to compute, which is so short that no “cars” get through).

30

Page 31: CPSC 121: Models of Computation 2012 Summer Term 2

A Timing Solution

D

GQ

output

D

GQ

button pressed

button press signal

31

Page 32: CPSC 121: Models of Computation 2012 Summer Term 2

Button/Clock is LO (unpressed)

D

GQ

output

D

GQ

LO

32

1

1

0

0

1

We’re assuming the circuit has been set up and is “running normally”. Right now, the light is off (i.e., the output of the right latch is 0).

Page 33: CPSC 121: Models of Computation 2012 Summer Term 2

Button goes HI (is pressed)

D

GQ

output

D

GQ

HI

33

1

1

0

1

1

This stuff is processing a new signal.

Page 34: CPSC 121: Models of Computation 2012 Summer Term 2

Propagating signal.. left NOT, right latch

D

GQ

output

D

GQ

HI

34

1

1

1

1

0

This stuff is processing a new signal.

Page 35: CPSC 121: Models of Computation 2012 Summer Term 2

Propagating signal.. right NOT (steady state)

D

GQ

output

D

GQ

HI

35

0

1

1

1

0

Why doesn’t the left latch update?a.Its D input is 0.b.Its G input is 0.c.Its Q output is 1.d.It should update!

Page 36: CPSC 121: Models of Computation 2012 Summer Term 2

Button goes LO (released)

D

GQ

outputLO

36

0

1

1

0

0

D

GQ

This stuff is processing a new signal.

Page 37: CPSC 121: Models of Computation 2012 Summer Term 2

Propagating signal..left NOT

D

GQ

output

D

GQ

LO

37

0

1

1

0

1

This stuff is processing a new signal.

Page 38: CPSC 121: Models of Computation 2012 Summer Term 2

Propagating signal..left latch (steady state)

D

GQ

output

D

GQ

LO

38

0

0

1

0

1

And, we’re done with one cycle.How does this compare to our initial state?

Page 39: CPSC 121: Models of Computation 2012 Summer Term 2

Master/Slave D Flip-Flop Symbol + Semantics

When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D.

Otherwise, it maintains its current value.

output (Q)

new data (D)

control or

“clock” signal (CLK)

D

G

Q

D

G

Q

39

Page 40: CPSC 121: Models of Computation 2012 Summer Term 2

Master/Slave D Flip-Flop Symbol + Semantics

When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D.

Otherwise, it maintains its current value.

output (Q)

new data (D)

control or

“clock” signal (CLK)

D

G

Q

D

G

Q

40

Page 41: CPSC 121: Models of Computation 2012 Summer Term 2

Master/Slave D Flip-Flop Symbol + Semantics

When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D.

Otherwise, it maintains its current value.

output (Q)

new data (D)

control or

“clock” signal (CLK)

D

G

Q

D

G

Q

41

Page 42: CPSC 121: Models of Computation 2012 Summer Term 2

Master/Slave D Flip-Flop Symbol + Semantics

When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D.

Otherwise, it maintains its current value.

new data

clock signal

D

Q output

42We rearranged the clock and D inputs and the output to match Logisim.

Below we use a slightly different looking flip-flop.

Page 43: CPSC 121: Models of Computation 2012 Summer Term 2

Why Abstract?

Logisim (and real circuits) have lots of flip-flops that all behave very similarly:– D flip-flops, – T flip-flops, – J-K flip-flops, – and S-R flip-flops.

They have slightly different implementations… and one could imagine brilliant new designs that are radically different inside.

Abstraction allows us to build a good design at a high-level without worrying about the details.

43Plus… it means you only need to learn about D flip-flops’ guts.

The others are similar enough so we can just take the abstraction for granted.

Page 44: CPSC 121: Models of Computation 2012 Summer Term 2

Outline

• Prereqs, Learning Goals, and !Quiz Notes

• Problems and Discussion– A Pushbutton Light Switch– Memory and Events: D Latches & Flip-Flops– General Implementation of DFAs

(with a more complex DFA as an example)– How Powerful are DFAs?

• Next Lecture Notes

44

Page 45: CPSC 121: Models of Computation 2012 Summer Term 2

How Do Computers Execute Programs?

• High-level languages (Java/Racket) are translated into low-level machine language

• A machine language program is a list of instructions in a representation scheme close to “plain” binary (e.g., 4 bits for the type of instruction, 4 bits for what part of the computer the result goes to, etc.)

• Each instruction has a (barely) human-readable version

• After it’s done with an instruction, the computer (usually) executes the next instruction in the list

45

Page 46: CPSC 121: Models of Computation 2012 Summer Term 2

Simplified Example(sum of 1..n)

(1) sum 0

(2) is n = 0?

(3) if the answer was yes, go to (7)

(4) sum sum + n

(5) n n - 1

(6) go to (2)

(7) halt

46

If the computer executed all instructions in order, there’d be no loops or recursion!

Fortunately, “branch” instructions (like (3)) tell the computer to go elsewhere.

Page 47: CPSC 121: Models of Computation 2012 Summer Term 2

Simplified Example, Complicated Execution

(1) sum 0

(2) is n = 0?

(3) if the answer was yes, go to (7)

(4) sum sum + n

(5) n n - 1

(6) go to (2)

(7) halt

47

To run faster, the computer starts executing one instruction even before it finishes the last.

But then what does it do with (3)?Does it execute (4) or (7)?

Page 48: CPSC 121: Models of Computation 2012 Summer Term 2

Branch Prediction Machine

To pre-execute a “branch”, the computer guesses which instruction comes next.

Here’s one reasonable guess: If the last branch was “taken” (like going to (7) from (3)), take the next. If it was “not taken” (like going to (4) from (3)), don’t take the next.

48Why? In recursion, how often do we hit

the base case vs. the recursive case?

Page 49: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Branch Predictor (First Pass)

Here’s the corresponding DFA. (Instead of accept/reject, we care about the current state.)

yes no

taken

nottaken

taken

49

nottaken

Experiments show it generally works well to add “inertia”so that it takes two “wrong guesses” to change the prediction…

taken the last branchwas taken

not taken the last branchwas not taken

yes we predict thenext branch will be taken

no we predict thenext branch will be not taken

Page 50: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Branch Predictor (Final Version)

Here’s a version that takes two wrong guesses in a row to admit it’s wrong:

Can we build a branch prediction circuit?

YES!

yes?

no?

NO!

nottaken

taken

nottaken

taken

nottaken

takentaken

not taken

50

Page 51: CPSC 121: Models of Computation 2012 Summer Term 2

Abstract Template for a DFA Circuit

input

clock

51

compute next state

store current

state

Each time the clock “ticks” move from one state to the next.

Page 52: CPSC 121: Models of Computation 2012 Summer Term 2

Template for a DFA Circuit

Each time the clock “ticks” move from one state to the next.

D

Q Combinationalcircuit to calculatenext state/output

input

CLK

Each of these lines (except the clock) may carry multiple bits; the D flip-flop may be several flip-flops to store several bits.

52

Page 53: CPSC 121: Models of Computation 2012 Summer Term 2

How to Implement a DFA: Slightly Harder

(1) Number the states and figure out b: the number of bits needed to store the state number.

(2) Lay out b D flip-flops. Together, their memory is the state as a binary number.

(3) Build a combinational circuit that determines the next state given the input and the current state.

(4) Use the next state as the new state of the flip-flops.

53

Page 54: CPSC 121: Models of Computation 2012 Summer Term 2

How to Implement a DFA: Slightly Easier MUX Solution

(1) Number the states and figure out b: the number of bits needed to store the state number.

(2) Lay out b D flip-flops. Together, their memory is the state as a binary number.

(3) For each state, build a combinational circuit that determines the next state given the input.

(4) Send the next states into a MUX with the current state as the control signal: only the appropriate next state gets used!

(5) Use the MUX’s output as the new state of the flip-flops.

54With a separate circuit for each state, they’re often very simple!

Page 55: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the PredictorStep 1

YES!3

yes?2

no?1

NO!0

nottaken

taken

nottaken

taken

nottaken

takentaken

not takenWhat is b (the number of 1-bit flip-flops

needed to represent the state)?a.0, no memory neededb.1c.2d.3e.None of these

As always, we use numbers to represent the inputs:

taken = 1not taken = 0

55

Page 56: CPSC 121: Models of Computation 2012 Summer Term 2

Just Truth Tables...

Current State input New state

0 0 0 0 0

0 0 1 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

YES!3

yes?2

no?1

NO!0

nottaken

taken

nottaken

taken

nottaken

takentaken

not taken

What’s in this row?a.0 0b.0 1c.1 0d.1 1e.None of these.

56

Reminder: not taken = 0 taken = 1

Page 57: CPSC 121: Models of Computation 2012 Summer Term 2

Just Truth Tables...

Current State input New state

0 0 0 0 0

0 0 1 0 1

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 1 1

1 1 0 1 0

1 1 1 1 1

YES!3

yes?2

no?1

NO!0

nottaken

taken

nottaken

taken

nottaken

takentaken

not taken

57

Reminder: not taken = 0 taken = 1

Page 58: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor:Step 3

We always use this pattern.

In this case, we need two flip-flops.

D

Q Combinationalcircuit to calculatenext state/output

input

CLK

D

Q

Let’s switch to Logisim schematics...58

Page 59: CPSC 121: Models of Computation 2012 Summer Term 2

???

Implementing the Predictor:Step 3

D

Q ??

input

CLK

D

Q

59

sleft

sright

Page 60: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor:Step 3

60

???

sleft

sright

input

Page 61: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor: Step 5 (easier than 4!)

61

The MUX “trick” here is much like in the ALU from lab!

sleft

sright

input

Page 62: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor: Step 4

62

input

sleft

srightIn state number 0, what should be the new value of sleft?Hint: look at the DFA, not at the circuit!a.inputb.~inputc.1d.0e.None of these.

Page 63: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor: Step 4

63

input

In state number 1, what’s the new value of sleft?a.inputb.~inputc.1d.0e.None of these.

sleft

sright

Page 64: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor: Step 4

input

In state number 2, what’s the new value of sleft?a.inputb.~inputc.1d.0e.None of these.

64

sleft

sright

Page 65: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor: Step 4

input

In state number 3, what’s the new value of sleft?a.inputb.~inputc.1d.0e.None of these.

65

sleft

sright

Page 66: CPSC 121: Models of Computation 2012 Summer Term 2

Just Truth Tables...

sleft sright input sleft' sright'

0 0 0 0 0

0 0 1 0 1

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 1 1

1 1 0 1 0

1 1 1 1 1

66

input

Page 67: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor: Step 4

67

input

sleft

sright

Page 68: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor: Step 4

In state number 0, what’s the new value of sright?a.inputb.~inputc.1d.0e.None of these.

68

input

sright

Page 69: CPSC 121: Models of Computation 2012 Summer Term 2

Implementing the Predictor: Step 4

TADA!! 69

input

sleft

sright

Page 70: CPSC 121: Models of Computation 2012 Summer Term 2

You can often simplify, but that’s not the point.

70

input

sleft

sright

Page 71: CPSC 121: Models of Computation 2012 Summer Term 2

Just for Fun: Renaming to Make a Pattern Clearer...

pred last input pred' last'

0 0 0 0 0

0 0 1 0 1

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 1 1

1 1 0 1 0

1 1 1 1 1

YES!3

yes?2

no?1

NO!0

nottaken

taken

nottaken

taken

nottaken

takentaken

not taken

71

Page 72: CPSC 121: Models of Computation 2012 Summer Term 2

Outline

• Prereqs, Learning Goals, and !Quiz Notes

• Problems and Discussion– A Pushbutton Light Switch– Memory and Events: D Latches & Flip-Flops– General Implementation of DFAs

(with a more complex DFA as an example)– How Powerful are DFAs?

• Next Lecture Notes

72

Page 73: CPSC 121: Models of Computation 2012 Summer Term 2

Steps to Build a Powerful Machine

(1) Number the states and figure out b: the number of bits needed to store the state number.

(2) Lay out b D flip-flops. Together, their memory is the state as a binary number.

(3) For each state, build a combinational circuit that determines the next state given the input.

(4) Send the next states into a MUX with the current state as the control signal: only the appropriate next state gets used!

(5) Use the MUX’s output as the new state of the flip-flops.

73With a separate circuit for each state, they’re often very simple!

Page 74: CPSC 121: Models of Computation 2012 Summer Term 2

How Powerful Is a DFA?

DFAs can model situations with a finite amount of memory, finite set of possible inputs, and particular pattern to update the memory given the inputs.

How does a DFA compare to a modern computer?

a.Modern computer is more powerful.

b.DFA is more powerful.

c.They’re the same.74

Page 75: CPSC 121: Models of Computation 2012 Summer Term 2

Where We’ll Go From Here...

We’ll come back to DFAs again later in lecture.

In lab you have been and will continue to explore what you can do once you have memory and events.

And, before long, how you combine these into a working computer!

Also in lab, you’ll work with a widely used representation equivalent to DFAs: regular expressions.

75

Page 76: CPSC 121: Models of Computation 2012 Summer Term 2

Outline

• Prereqs, Learning Goals, and !Quiz Notes

• Problems and Discussion– A Pushbutton Light Switch– Memory and Events: D Latches & Flip-Flops– General Implementation of DFAs

(with a more complex DFA as an example)– How Powerful are DFAs?

• Next Lecture Notes

76

Page 77: CPSC 121: Models of Computation 2012 Summer Term 2

Learning Goals: In-Class

By the end of this unit, you should be able to:– Translate a DFA to a corresponding sequential

circuit, but with a “hole” in it for the circuitry describing the DFA’s transitions.

– Describe the contents of that “hole” as a combinational circuitry problem (and therefore solve it, just like you do other combinational circuitry problems!).

– Explain how and why each part of the resulting circuit works.

77

Page 78: CPSC 121: Models of Computation 2012 Summer Term 2

Next Lecture Learning Goals: Pre-Class

By the start of class, you should be able to:– Convert sequences to and from explicit formulas

that describe the sequence.– Convert sums to and from summation/”sigma”

notation.– Convert products to and from product/”pi”

notation.– Manipulate formulas in summation/product

notation by adjusting their bounds, merging or splitting summations/products, and factoring out values.

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Next Lecture Prerequisites

See the Mathematical Induction Textbook Sections at the bottom of the “Readings and Equipment” page.

Complete the open-book, untimed quiz on Vista that’s due before the next class.

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Page 80: CPSC 121: Models of Computation 2012 Summer Term 2

snick

snack

More problems to solve...

(on your own or if we have time)

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Page 81: CPSC 121: Models of Computation 2012 Summer Term 2

Problem: Traffic Light

Problem: Design a DFA with outputs to control a set of traffic lights.

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Page 82: CPSC 121: Models of Computation 2012 Summer Term 2

Problem: Traffic Light

Problem: Design a DFA with outputs to control a set of traffic lights.

Thought: try allowing an output that sets a timer which in turn causes an input like our “button press” when it goes off.

Variants to try:- Pedestrian cross-walks- Turn signals- Inductive sensors to indicate presence of cars- Left-turn signals

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1 2 3a a

a,b,cb

b,cc

PROBLEM: Does this accept the empty string?

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“Moore Machines” DFAs whose state matters

A “Moore Machine” is a DFA that’s not about accepting or rejecting but about what state it’s in at a particular time.

Let’s work with a specific example...

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