cpen 315 - digital system design chapter 9 – computer design c. gerousis © logic and computer...
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CPEN 315 - Digital System Design
Chapter 9 – Computer Design
C. Gerousis© Logic and Computer Design Fundamentals, 4rd Ed., Mano
Prentice Hall
Charles Kime & Thomas Kaminski
© 2008 Pearson Education, Inc.
Overview Part 1 – Datapaths
– Introduction
– Datapath Example
– Arithmetic Logic Unit (ALU)
– Shifter
– Datapath Representation and Control Word
Part 2 – A Simple Computer– Instruction Set Architecture (ISA)
– Single-Cycle Hardwired Control
Part 3 – Multiple Cycle Hardwired Control– Single Cycle Computer Issues
– Modifications to Datapath
– Modifications to Control
– Sequential Control Design
Introduction
Computer Specification– Instruction Set Architecture (ISA) - The parts of a
processor's design that need to be understood in order to write a machine language instructions and registers – A low-level description.
– Computer Architecture - A high-level description of the hardware implementing the computer derived from the ISA.
– The architecture usually includes additional specifications such as speed, cost, and reliability.
Introduction (continued)
Simple computer architecture decomposed into:– Datapath for performing operations– Control unit for controlling datapath operations
A datapath is specified by:– A set of registers– The microoperations performed on the data
stored in the registers– A control interface
Datapaths Guiding principles for basic datapaths:
– The set of registers Collection of individual registers A set of registers with common access resources called a
register file A combination of the above
– Microoperation implementation One or more shared resources for implementing
microoperations Buses - shared transfer paths Arithmetic-Logic Unit (ALU) - shared resource for
implementing arithmetic and logic microoperations Shifter - shared resource for implementing shift
microoperations
Four parallel-loadregisters
Two mux-based register selectors
Register destination decoder
Mux B for external constant input
Buses A and B with externaladdress and data outputs
ALU and Shifter withMux F for output select
Mux D for external data input Logic for generating status bits
V, C, N, Z
MD select 0 1MUX D
V
C
NZ
n
n
n
n
n
n
n
nn n
n
2 2
n
n
A data B data
Register file
1 0
MUX B AddressOutDataOut
Bus ABus B
nn
Function unit
A B nG select
4
Zero Detect
MF select
nn
nF
MUX F
H select2
n
A BS2:0 || Cin
Arithmetic/logicunit (ALU)
G
BS
Shifter
H
MUX
01
23
MUX
0123
0 1 2 3
Decoder
Load
Load
Load
Load
Load enable
WriteD data
D address2
Destination select
Constant in
MB select
A select
A address
B select
B address
R3
R2
R1
R0
Bus Dn
Data In
ILIR0 0
0 1
Datapath Example
Microoperation: R0 ← R1 + R2
MD select 0 1MUX D
V
C
NZ
n
n
n
n
n
n
n
nn n
n
2 2
n
n
A data B data
Register file
1 0
MUX B AddressOutDataOut
Bus ABus B
nn
Function unit
A B nG select
4
Zero Detect
MF select
nn
nF
MUX F
H select2
n
A BS2:0 || Cin
Arithmetic/logicunit (ALU)
G
BS
Shifter
H
MUX
01
23
MUX
0123
0 1 2 3
Decoder
Load
Load
Load
Load
Load enable
WriteD data
D address2
Destination select
Constant in
MB select
A select
A address
B select
B address
R3
R2
R1
R0
Bus Dn
Data In
ILIR0 0
0 1
Datapath Example: Performing a Microoperation
Apply 01 to A select to place contents of R1 onto Bus A
Apply 10 to B select to place contents of R2 onto B data and apply 0 to MB select to place B data on Bus B
Apply 0010 to G select to perform addition G = Bus A + Bus B
Apply 0 to MF select and 0 to MDselect to place the value of G onto BUS D
Apply 00 to Destination select to enable the Load input to R0
Apply 1 to Load Enable to force the Load input to R0 to 1 so that R0 is loaded on the clock pulse (not shown)
The overall microoperation requires1 clock cycle
Arithmetic Logic Unit (ALU) In this and the next section, we deal with design of
typical ALUs and shifters Decompose the ALU into:
– An arithmetic circuit– A logic circuit– A selector to pick between the two circuits
Arithmetic circuit design– Decompose the arithmetic circuit into:
An n-bit parallel adder A block of logic that selects four choices for the B input to the
adder
Arithmetic Circuit Design (continued) There are only four functions of B to select as Y in G = A + Y + Cin:
B inputlogicMUX
n
n
X
Cin
Y
n
Cout
n-bitparalleladder
S1
S0
An
S1
S0
Bn
A inputlogicCombinational
Logic Circuit
* Simplification could yield less complex logic.
*
C i C i + 1
One stage ofarithmetic
circuit
One stage oflogic circuit
2-to-1MUX0
1S
A i
B i
S0
S1
S2
C i
G i
A i
B i
S0
S1
A i
B i
S0
S1
C in
Arithmetic Logic Unit (ALU)
For n-bit ALU the one stage circuit must be repeated n times.
ALU (continued)
S2 = 0 Arithmetic operationsS2 = 1 logic operations
Arithmetic Circuit Example Inputs Xi and Yi of each full adder in an arithmetic circuit have digital logic specified by the Boolean functions:
iniii
ii
CBSBY
AX
Where S is a selection variable, Cin is the input carry, and Ai and Bi are input data for stage i.
(a) Draw the logic diagram for the 4-bit circuit using full-adders and multiplexers.
(b) Determine the arithmetic operation performed for each of the four combinations of S and Cin : 00, 01, 10 and 11.
4-Bit Basic Left/Right Shifter
Right shift fills position on left with value on input IR
Serial outputs are available from serial output R.
B3
IR IL
S
Serialoutput L
Serialoutput R
2
B2 B1 B0
H0H1H2H3
SMUX
0 1 2S
MUX
0 1 2S
MUX
0 1 2S
MUX
0 1 2
Shift Functions:(S1, S0) = 00 Pass B unchanged 01 Right shift 10 Left shift 11 Unused
Datapath Representation Earlier we looked at detailed
design of ALU and shifter in the datapath
Here we move up one level in the hierarchy from that datapath
The registers, and the multiplexer, decoder, and enable hardware for accessing them become a register file
The ALU, shifter, Mux F and status hardware become a function unit
The remaining muxes and buses which handle data transfers are at the new level of the hierarchy
Address outData out
Constant in
MB select
Bus ABus B
FSVCNZ
MD select
n
D dataWriteD address
A address B address
A data B data
2mx n
Register file
m
m m
n nn
nn
A B
Functionunit
F
4
MUX B1 0
MUX D0 1
n nData in
Datapath Representation (continued)
In the register file:– Multiplexer select inputs become
A address and B address – Decoder input becomes D
address– Multiplexer outputs become A
data and B data– Input data to the registers
becomes D data– Load enable becomes write
The register file now appears like a memory based on clocked flip-flops (the clock is not shown)
The function unit labeling is quite straightforward except for FS
Address outData out
Constant in
MB select
Bus ABus B
FSVCNZ
MD select
n
D dataWriteD address
A address B address
A data B data
2mx nRegister file
m
m m
n nn
nn
A B
Functionunit
F
4
MUX B1 0
MUX D0 1
n nData in
MD select 0 1MUX D
V
C
NZ
n
n
n
n
n
n
n
nn n
n
2 2
n
n
A data B data
Register file
1 0
MUX B AddressOutDataOut
Bus ABus B
nn
Function unit
A B nG select
4
Zero Detect
MF select
nn
nF
MUX F
H select2
n
A BS2:0 || Cin
Arithmetic/logicunit (ALU)
G
BS
Shifter
H
MUX
01
23
MUX
0123
0 1 2 3
Decoder
Load
Load
Load
Load
Load enable
WriteD data
D address2
Destination select
Constant in
MB select
A select
A address
B select
B address
R3
R2
R1
R0
Bus Dn
Data In
ILIR0 0
0 1
Address outData out
Constant in
MB select
Bus ABus B
FSVCNZ
MD select
n
D dataWriteD address
A address B address
A data B data
2mx nRegister file
m
m m
n nn
nn
A B
Functionunit
F
4
MUX B1 0
MUX D0 1
n nData in
Datapath Representation (continued)
MF, G, and H must be defined in terms of the codes for FS
Status Bits
ALU Function Select (FS)
S2 = 0 Arithmetic operationsS2 = 1 logic operations
G Select,H Select, andMFin T ofFS Codes
FS(3:0)MFSelect
GSelect(3:0)
HSelect(3:0) Microoperation
0000 0 0000 XX0001 0 0001 XX0010 0 0010 XX0011 0 0011 XX0100 0 0100 XX0101 0 0101 XX0110 0 0110 XX0111 0 0111 XX1000 0 1X00 XX1001 0 1X01 XX1010 0 1X10 XX1011 0 1X11 XX1100 1 XXXX 001101 1 XXXX 011110 1 XXXX 10
F AF A 1
F A BF A B 1F A BF A B 1F A 1F AF A BF A BF A BF AF BF sr BF sl B
Definition of Function Unit Select (FS) Codes
The Control Word
The datapath has many control inputs The signals driving these inputs can be defined
and organized into a control word To execute a microinstruction, we apply
control word values for a clock cycle. For most microoperations, the positive edge of the clock cycle is needed to perform the register load
The datapath control word format and the field definitions are shown next
The Control Word Fields
Fields– DA – D Address– AA – A Address– BA – B Address– MB – Mux B– FS – Function Select – MD – Mux D– RW – Register Write
The connections to datapath are shown in the next slide
Control word
DA AA BA MB
FS MD
RW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Control Word Block Diagram
108
14
0
13
11
Bus D
Constant inn
n
MUX B1 0
D dataWrite
D address
A address B address
A data B data
8 x nRegister file
A B
Functionunit
n
n
n
MUX D
0 1
n nData in
Bus A
Bus B
RW
12AA
15DA
n
BA9
Address out
Data out
V
C
N
Z
7
MD 1
MB 6
4 FS
5
32
Control word
DA AA BA MB
FS MD
RW
1514 13 12 1110 9 8 7 6 5 4 3 2 1 0
Encoding of ControlWord for Datapath
F A
DA, AA, BA MB FS MD RW
Function Code Function Code Function Code Function Code Function Code
R0 000 Register 0 0000 Function 0 No write 0R1 001 Constant 1 0001 Data In 1 Write 1R2 010 0010R3 011 0011R4 100 0100R5 101 0101R6 110 0110R7 111 0111
1000100110101011110011011110
F AF A 1
BF A B 1F A BF A B 1F A 1F AF A BF A BF A BF AF BF sr BF sl B
Control Word Encoding
Microoperations for the Datapath - Symbolic Representation
Micro-operation DA AA BA MB FS MD RW
R1 R2 R3 Register Function WriteR4 —* R6* Register Function WriteR7 R7 — Register Function WriteR1 R0 — Constant Function Write—— R3 Register — — No WriteR4 —— — — Data in WriteR5 R0 R0 Register Function Write
R1 R2 R3– F A B 1+ +=R4 sl R6 F sl B=R7 R7 1+ F A 1+=R1 R0 2+ F A B+=
Data out R3R4 Data inR5 0 F A B=
*The shifter is driven by the B Bus source for the shift is specified in theBA field rather than the AA field.
Control Word Example
Given the sequence of 16-bit control words for the datapath and the initial ASCII character codes in 8-bit registers, simulate the datapath to determine the alphanumeric characters in the registers after the execution of the sequence.
011 011 001 0 0010 0 1 R0 00000000100 100 001 0 1001 0 1 R1 00100000101 101 001 0 1010 0 1 R2 01000100001 001 000 0 1011 0 1 R3 01000111001 001 000 0 0001 0 1 R4 01010100110 110 001 0 0101 0 1 R5 01001100111 111 001 0 0101 0 1 R6 01000001011 111 000 0 0000 0 1 R7 01001001
RW = 1 WriteMD = 0 FunctionMB = 0 Function
Control word
DA AA BA MB FS M
DRW
151413121110 9 8 7 6 5 4 3 2 1 0
Control Word Example (continued)
011 011 001 0 0010 0 1
Addition
108
14
0
13
11
Bus D
Constant inn
n
MUX B1 0
D dataWrite
D address
A address B address
A data B data
8 x nRegister file
A B
Functionunit
n
n
n
MUX D
0 1
n nData in
Bus A
Bus B
RW
12AA
15DA
n
BA9
Address out
Data out
VCNZ
7
MD 1
MB 6
4 FS
5
32
R3 R1
133 RRR
R3 01000111
R1 00100000
01100111133 RRR
01100111133 RRR
Control Word Example (continued)
100 100 001 0 1001 0 1
01110100144 RRR
R1 00100000R4 01010100
‘t’
101 101 001 0 1010 0 1
01101100155 RRR
R1 00100000R5 01001100
‘l’
001 001 000 0 1011 0 1
1101111111 RR
001 001 000 0 0001 0 1
11100000111 RR
110 110 001 0 0101 0 1
011000011166 RRR
R6 01000001
‘a’
111 111 001 0 0101 0 1
R7 01001001
011010011177 RRR ‘i’
011 111 000 0 0000 0 1
0110100171 RR ‘i’
D i g i t a l
Control Word Example (continued)