course overview 2016... · case statements • default case: –two ways to fully define case...

Course Overview

Chapter 5a Copyright 2014 G. Tumbush v1.2

• Review of combinational and sequential logic design • Modeling and verification with hardware description languages • Introduction to synthesis with HDLs • Programmable logic devices • State machines, datapath controllers, RISC CPU • Architectures and algorithms for computation and signal processing • Synchronization across clock domains • Timing analysis • Fault simulation and testing, JTAG, BIST

1

Behavioral Models


• Up to this point just created schematics textually • Behavioral models are abstract descriptions of functionality

• Easier to understand • More closely follow the algorithm • Much more productive

• Two way to create behavioral models • Continuous assignment • Procedural assignment

• Need behavioral operators

2

Operators – Bitwise/reduction are unary:

& 4’b1001 = 0

& 4’bx101 = x

| 4’b1001 = 1

| 4’bx101 = x

– Logical Operators: 2’b00 && 2’b11 = 2’b00

2’b00 || 2’b11 = 2’b11

– Shift 4’sb1001 >> 1 = 0100

4’sb1001 >>> 1 = 1100

4’b1001 >>> 1 = 0100

– Relational 4'b01x0 == 4'b01x0 produces an x

4'b01x0 === 4'b01x0 produces a 1

Behavioral Operators - Arithmetic


Operator Type Operator Symbol Operation # of Operands

Arithmetic * Multiply 2

/ Divide 2

+ Add 2

- Subtract 2

% Modulus 2

S. Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Sun Microsystems, 1996

A=4’b0011; B=4’b0100; A*B = 4’b1100 A+B=4’b0111 B-A=4’b0001

D=6; E=4; (D/E)=1 (D%E)=2 If an operand bit has a value of x or z, the result is x

A=4’b0011; B=4’b01x0; (A*B) = 4’bxxxx (A+B)=4’bxxxx (B-A)=4’bxxxx

4

Behavioral Operators - Logical



Logical ! Logical Negation 1

&& Logical and 2

|| Logical or 2


Always evaluate to a 1-bit value If an operand is not equal to 0 it is equivalent to logic 1

A=1’b1;B=1’b0; !A=1’b0 (A &&B) = 1’b0 (A || B) = 1’b1 A=3; B=0; !A= 1’b0 (A &&B) = 1’b0 (A || B) = 1’b1 A=2’bx0; B=2’b00; (A && B) = 1’b0 (A || B) = 1’bx A=2’b1x; B=2’b00; (A && B) = 1’b0 (A || B) = 1’b1 A=1’bx; !A=1’bx A=1’bz; !A=1’bx

5

Behavioral Operators - Relational



Relational > Greater than 2

< Less than 2

>= Greater than or equal

2

<= Less than or equal

2


Always evaluate to a 1-bit value

A=4;B=3; (A <= B) = 1’b0 (A>B) = 1’b1 If any operand bit has a value of x or z, the result is x

A=4’b0011; B=4’b01x0; (A>=B) = 1’bx

6

Behavioral Operators - Equality



Equality == Equality 2

!= Inequality 2

=== Case equality 2

!== Case inequality 2


7

Always evaluate to a 1-bit value

For logical equality if an operand bit has a value of x or z, the result is x.

A=3’b010; B=2’b10; (A==B)=1’b1 (A!=B)=1’b0 A=3’bx10; B=3’b010; (A==B)=1’bx

For case equality operators all bits must match exactly including x’s or z’s.

A=3’bx10; B=3’b010; (A===B) =1’b0 A=3’bx10; B=3’bx10; (A===B) =1’b1

Uses for Case Equality/Inequality

Chapter 5a Copyright 2014 G. Tumbush v1.2 8

Suppose we have a comparator in our testbench

comparatorexpected

error

actual

always @(expected or actual) begin if (expected != actual) error = 1’b1; else error = 1’b0; end

if expect = 4’b0011 and actual = 4’b001x error will be set to 0

if (expected !== actual)

if expect = 4’b0011 and actual = 4’b001x error will be set to 1

Behavioral Operators - Bitwise



Bitwise ~ Bitwise negation 1

& Bitwise and 2

| Bitwise or 2

^ Bitwise xor 2

^~ or ~^ Bitwise xnor 2


9

Performs a bit-by-bit operation on the operands. A=4’b1010; B=4’b1101 ~A =4’b0101 (A&B)=4’b1000 (A|B)=4’b1111 A=4’b10x0; B=4’b1x11; ~A=4’01x1 (A&B)=4’b10x0 (A|B)=4’b1x11

Behavioral Operators - Reduction



Reduction & Reduction and 1

~& Reduction nand 1

| Reduction or 1

~| Reduction nor 1

^ Reduction xor 1

~^ Reduction xnor 1

S. Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Sun Microsystems, 1996 10

Performs operation on all bits Always evaluates to a 1-bit value A=4’b1000; &A=1’b0 |A=1’b1 ^A=1’b1,

A=3’b101; &A=1’b0 ~&A=1’b1

A=4’b10x0; &A= 1’b0 |A = 1’b1 ^A=1’bx

Exercises


A=2’b01; B=2’b10; C=2’b00; D=2’bx0;

8. B==D 9. B===D 10. ~D 11. B&C 12. A ^C 13. &A 14. ~&B 15. ~|A

11

1. B*A 2. A+B 3. B%A 4. !A 5. A && C 6. B || A 7. B>A

Behavioral Operators – Shift/Concatenation



Shift >> Right Shift 2

<< Left Shift 2

Concatenation {} Concatenation Any number


When bits are shifted, vacant bit positions are filled with 0’s

A=4’b1100; (A >> 2)=4’b0011 (A<<1)=4’b1000

Concatenation is used to append multiple operands The operands must be sized

A=2’b01; B=3’b101; {A,B}=5’b01101

Verilog 2001 adds Arithmetic Shift Operators: Arithmetic Shift Right: >>> Arithmetic Shift Left: <<< Arithmetic Shift preserves sign bit. It works with signed operators, which were also introduced with Verilog 2001

12

Behavioral Operators – Replication/Conditional



Replication { { } } Replication 2

Conditional ? : Conditional Three


The replication operator is used to replicate a value

A=1’b1; B=2’b01; {4{A}}=4’b1111 {4{B}}= 8’b01010101 The conditional operator is used as a shorthand for a 2-1 mux Syntax: (condition) ? (value if true) : (value if false)

A=1’b1; (A== 1’b1) ? 1’b0 : 1’b1 evaluates to 1’b0 If “condition” is x the “value if true” expression is compared to the “value if false” expression bit-by-bit and return an x for bits that don’t match, the bit if they do.

13

Operator Precedence • Binary Operator Precedence

(A + B)/C is not the same as A + B/C

a & &b is not the same as a && b

correct syntax and required by LRM: a & (&b)

a | |b is not the same as a || b

correct syntax and required by LRM: a | (|b)

Exercises


A=4’b0110; B=4’b1001; C=1’b1; D=2’b00;

1. A>>1 2. A >>4 3. B << 1 4. {A,C,D} 5. {4{C}} 6. {2{B}} 7. C ? A : B 8. D ? A : B 9. 1’bx ? C:D

15

Continuous Assignment


Uses the keyword assign Used to drive a value onto a wire Continuous assignments create combinatorial logic only! Example:

module example(input wire a,b, output wire out1, out2, out3); assign out1=a; assign out2=a&&b; assign out3= a ? 1’b1 : b; endmodule

Exercise


Create a 2-1 mux using continuous assignments. Inputs are i0, i1, sel. Output is out.

Procedural assignments


You’ve already seen an example of a procedural block, initial

initial begin a = 1’b0; b = 1’b1; end

Another procedural block is always always blocks are entered when a signal in the sensitivity list changes (event occurs)

always @(a or b) begin // always @(a,b) c = a^b end

Continuous vs Procedural for Combinatorial Logic


module bool(input wire a, b,c, output wire out); assign out = c&&(a||b); endmodule

assign is never used in a procedural block Only signals declared as type reg can be driven in a procedural block Only signals declared as type wire can be driven by assign

module bool(input wire a, b,c, output reg out); always @(a or b or c) begin out = c&&(a||b); end endmodule

Equivalent

module bool(a, b,c, out); input a,b,c; output out wire a,b,c; reg out; always @(a or b or c) begin out = c&&(a||b); end endmodule

Equivalent

Exercise


Create a 2-1 mux using a procedural block Inputs are i0, i1, sel. Output is out.

Incomplete Sensitivity List


What happens if I don’t fully fill out a sensitivity list? The procedural block doesn’t get entered when it should

module mux2_1(input wire i0, i1,sel, output reg out); always @(i0 or sel) begin out = sel ? i1 : i0; end endmodule

Verilog 2001 added wildcard (*) to represent sensitivity list: always @*

Why bother with Procedural?


It looks like more typing?! If I add a term to my statement I have to add it to the sensitivity list

Wide range of conditional statements allowed in procedural blocks • If-else • Case • Loop

• while • for • repeat • forever

if-else


module encoder(input wire [3:0] code, output reg [2:0] out); always @(code) begin if (code== 4’b0001) out = 3’b000; else if (code== 4’b0010) out = 3’b001; else if (code== 4’b0100) out = 3’b010; else if (code== 4’b1000) out = 3’b011; else out = 3’b1xx; end endmodule

encodercode out34

Case


module encoder(input wire [3:0] code, output reg [2:0] out);

always @(code) begin case(code) 4’b0001: out = 3’b000; 4’b0010: out = 3’b001; 4’b0100: out = 3’b010; 4’b1000: out = 3’b011; default: out = 3’b1xx; endcase end

endmodule

encodercode out34

case statements

• default case: – An optional case to indicate what actions to perform if

none of the defined case items match the case expression

– Good coding style to place the default last, though not required by the Verilog LRM

– If a case statement does not include a case default and if it is not possible to find a binary case expression that matches any of the defined case items, the case statement is not "full." • Verilog does not require case statements to be “full” • If case statement not “full” and no default case, latch

inferred

case statements

• default case:

– Two ways to fully define case statement:

module encoder_def(input wire [3:0] code, output reg [2:0] out);

always @(code) begin case(code) 4’b0001: out = 3’b000; 4’b0010: out = 3’b001; 4’b0100: out = 3’b010; 4’b1000: out = 3’b011; default: out = 3’b1xx; endcase end

endmodule

module encoder2(input wire [3:0] code, output reg [2:0] out);

always @(code) begin out = 3’b1xx; case(code) 4’b0001: out = 3’b000; 4’b0010: out = 3’b001; 4’b0100: out = 3’b010; 4’b1000: out = 3’b011; endcase end

endmodule

Decision Trees Post synthesis implementation will differ based on coding style

Priority Decision Tree

Parallel Decision Tree

Exercise


Create a 2-1 mux using if/else and another using case statements. Inputs are i0, i1, sel. Output is out.

Example


Create the next state logic for the NRZ-to-Manchester encoder implemented as a Mealy machine in section 3.7.1

module manchester_next_state(input wire q1, q0, Bin, output reg q1_new, q0_new);

always @(q1 or q0 or Bin) begin case({q1,q0}) 2’b00: begin if (Bin) {q1_new,q0_new} = 2’b10; else {q1_new,q0_new} = 2’b01; end 2’b01: {q1_new,q0_new} = 2’b00; 2’b10: {q1_new,q0_new} = 2’b00; default: {q1_new,q0_new} = 2’b00; endcase end

endmodule

S_0 S_1S_2Bin==0/

Bout=0

Bin==1/

Bout=1

Bin==0/

Bout=1

Bin==x/

Bout=0

Bin==1/

Bout=0

Example


Create the next state logic for the NRZ-to-Manchester encoder implemented as a Mealy machine in section 3.7.1

module manchester_next_state(input wire [1:0] current_state, input wire Bin, output reg [1:0] next_state);

always @(current_state or Bin) begin case(current_state) 2’b00: begin if (Bin) next_state = 2’b10; else next_state = 2’b01; end 2’b01: next_state = 2’b00; 2’b10: next_state = 2’b00; default: next_state = 2’b00; endcase end

endmodule

S_0 S_1S_2Bin==0/

Bout=0

Bin==1/

Bout=1

Bin==0/

Bout=1

Bin==x/

Bout=0

Bin==1/

Bout=0

While Loop


• Loops until expression is false • Typically found inside initial procedural blocks

integer address; initial begin address = 0; while (address < 128) begin address = address+1; end end

For loop


integer bit_pos; reg [4:0] count; reg [15:0] my_reg; always @(my_reg) begin count = 0; for (bit_pos = 0; bit_pos < 16; bit_pos = bit_pos +1) begin if (my_reg[bit_pos]) count = count+1’b1; end end

The only synthesizable loop

Repeat loop


• Executes a loop a fixed number of times • Repeat value can be a constant, variable, or signal • Typically found inside initial procedural blocks

integer address; reg read_req; initial begin address = 0; repeat(5) begin read_req = 1'b0; #10; read_req = 1'b1; #10; address = address+1; end end

Forever


reg clk; initial begin clk = 1'b0; forever #100 clk = ~clk; end

• Loops until $finish is encountered • Typically found inside initial procedural blocks • Equivalent to while (1)

Alternate way to create free running clock: reg clk = 0; always #100 clk = ~clk;

Exercise


Using your favorite loop design a loop that for a 128-bit array will initialize the even locations to 0 and the odd locations to 1

1 0 1 0 1 0 1 0...01234127 126 125

If with no else


What would occur with this code? always @(a or c) begin if (a) b=c; end

D Q

ENa

bc

What is wrong with latches • Asynchronous • Outputs can glitch • Not testable with scan techniques

A latch!

Inferring latches in case statements


always @(sel or i0 or i1) begin case (sel) 1’b0: out = i0; endcase end

always @(sel or i0 or i1) begin case (sel) 1’b0: out = i0; 1’b1: out = i1; endcase end

always @(sel or i0 or i1) begin case (sel) 1’b0: out = i0; default: out = i1; endcase end

always @(sel or i0 or i1) begin case (sel) 1’b0: out = i0; 1’b1: out = i1; default: out = i1; endcase end

Latch No Latch

No Latch No Latch

The Correct Way to Create Storage


Create a flip-flop: module dff_examples (input D, Clk, output Q, Qb); reg DFF_async1, DFF_async2, DFF_sync; // D Flip Flop Asychronous Reset Example always @(posedge clk or posedge reset) begin if(reset == 1) DFF_async1 <= 1’b0; else DFF_async <= D; end // Another D Flip Flop Asychronous Reset Example always @(posedge clk, negedge reset) begin if(!reset ) DFF_async2 <= 1’b0; else DFF_async <= D; end // D Flip Flop Sychronous Reset Example always @(posedge clk ) begin if(reset) DFF_async <= 1’b0; else DFF_async <= D; end

course overview 2016... · case statements • default case: –two ways to fully define case...

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