Course Offering!

ECE 6775: VLSI Memory Design ECE 5960-5: VLSI Memory Design (Undergrad version)

The class covers all the knowledge required to succeed in the design of memories in state-of-the-art and near-future technologies.

• Design of Static Random Access Memories (SRAMs) • SRAM Design with Advanced MOS Technologies • Design of Dynamic Memory Arrays (DRAMs) • Specific memory arrays (ROMs, CAMs, SCMs…) • Non-volatile Memories (Flash) • Emerging Non-Volatile Memory Technologies (MRAM, RRAMs, PCM...) • Design with Non-Volatile Memory Technologies (FPGAs, Neuromorphic…)

The class relies intensively on two practical hands-on activities:

• VLSI memory design labs – including full-custom SRAM designs generation using industry-standard EDA tools at 180nm and 7nm FinFETs; and semi-custom design of a RISC-V processor using memory macros.

• The nanofabrication of emerging resistive RAM memories in the Utah’s Nanofab and its full electrical characterization.

We will also visit IMFlash Technologies and meet with memory engineers Instructor: Prof. Pierre-Emmanuel Gaillardon (MEB 2126)

High-density flash memory chip for SSD

65nm 6T SRAM

6T SRAM circuit

Memory integration in EDA tools

Advanced probing techniques

Utah’s Nanofab

Instructor:Pierre-Emmanuel Gaillardon: pierre-emmanuel.gaillardon@utah.edu

Office:MEB 2126

Office Hours:Pierre-Emmanuel Gaillardon: T 2:15pm-3:30pm -- H 11:15am-12:15pm

Class and Labs Hours:Class: T/H 12:25pm-1:45pm - WBB 820Labs (VLSI): W 10:10am-1:10pm - MEB 2555Labs (Nanofab): F 10:10am-1:10pm - Nanofab or MEB 1339

Recommended Textbook:CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edition, Neil Weste and David Harris, Pearsoneducation - Addison-Wesley.

Recommended knowledge:Some background in CMOS digital design and the physics of semiconductors is recommended but most ofthe basic concepts will be refreshed.

Prerequisites

ECE/CS 5710/6710: Digital VLSI Design or Instructor consentMust be enrolled as a ECE or CS graduate student for 6XXX level registrations

Units:4 credits

Course costThis course is associated with a lab fee of $155 (regular course and labs fees ($35) and an additional fee tocover the nanofabrication cost ($120).

Course DescriptionThe goal of this course is to introduce undergraduate and graduate students to the design of VLSI memories.The course will cover static, dynamic and non-volatile memories by carefully considering device technology,circuit design and system integration. The philosophy of this course is to first ensure that the basic knowledge of memory design in bulk technologyis mastered. Then, the specific challenges brought by state-of-the-art semiconductor (FinFET, FDSOI andmodern Flash processes) will be covered and practical solutions towards lowering the power consumptionimpact of memories in the context of modern system-on-chip design will be presented. Finally, the latestresearch advances in the domain of non-volatile memories will be discussed along with the opportunities theywill bring to the semiconductor industry in the coming years. In addition, the class will be augmented with several hands-on experiences: (1) the design of a full memorysystem, including full custom SRAM cells and peripheral circuits generation using industry-standard EDAtools, (2) the design of a state-of-the-art processor using compiler-generated memory cuts and (3) thenanofabrication of emerging resistive RAM memories in the Utah's Nanofab and its full electricalcharacterization. The students groups will be asked to answer scientific research questions and prepare ascientific paper by the end of the semester. Guest lectures will be offered by IMFlash Technologies.

With this course, the attendees will be equipped with all the background knowledge required to succeed inthe design of memories in state-of-the-art and near-future technologies.

Class schedule: The current tentative class schdule is available HERE

Lab groups: The class will be devided in section of 6 students who will separate nanofabrication session. However, all labgroups attend the VLSI labs together. Attendance to the scheduled lab slots is mandatory and will beenforced.

Policies

The college of Engineering guidelines.The University of Utah's Student Code covers cheating and other student conduct policies.Late submission:We follow a strict late submission rule based on the timestamp on your Canvas submission. Latesubmissions are at risk to not be graded and result in a 0% score. If graded, late homework/reportssubmissions will be handled as follow: Between due date and 1 week after the submission, themaximum achievable grade will be reduced to 75%. Further late submissions will have a maximumachievable grade of 50%. The instructor reserves the right to reject any late submissions. If you haveany concerns, start early or inform the instructor! Any changes in due date will affect the entire class atthe discretion of the lecturers.The instructor reserves the right to add/remove exams/graded assignments and/or chance deadlines athis discretion.

The University of Utah seeks to provide equal access to its programs, services and activities for peoplewith disabilities. If you will need accommodations in the class, reasonable prior notice needs to begiven to the Center for Disability Services, 162 Olpin Union Building, 801-581-5020. CDS will workwith you and the instructor to make arrangements for accommodations.

All written information in this course can be made available in alternative format with priornotification to the Center for Disability Services.

Planned Evaluation and Grading

ItemECE5960-005

ECE 6775 /CS 6961-001 Description

VLSI Labs 55% 40% 9 labs weighted equally; Attendance counting for 5%Project (RRAMNanofabrication) 20% 35% Lab reports: 10% (undergraduate) - 5% (graduate); Presentation:

10%; Final paper and results (graduate students only): 20%Exams 25% 25% Final exam

Advanced VLSI Memory Design ECE 5960-5/6 ECE 6775-1/2 CS6961-1/2

Tentative Schedule – Aug. 2nd, 2017 Class times – T/H – 12:25pm-1:45pm Lab times – W/F – 10:10am-01:10pm Week Date Topic

1

Aug. 22 (T) Class presentation and Reminder on full-custom VLSI design Aug. 23 (W) No lab – Use this time to get up to speed with VLSI design Aug. 24 (H) CMOS Gates Aug. 25 (F) No lab – Use this time to get up to speed with VLSI design

2

Aug. 29 (T) Logical effort Aug. 30 (W) VLSI Lab 1 Aug. 31 (H) SRAM bit cell Sept. 01 (F) Nanofab safety training

3

Sept. 05 (T) SRAM Periphery Sept. 06 (W) VLSI Lab 2 – session 1 Sept. 07 (H) Exercise Session (Logical Effort, …) Sept. 09 (F) Nanofab Lab

4

Sept. 12 (T) No class Sept. 13 (W) VLSI Lab 2 – session 2 Sept. 14 (H) No class Sept. 15 (F) Nanofab Lab

5

Sept. 19 (T) Scaling – Advanced CMOS Technologies - FDSOI Sept. 20 (W) VLSI Lab 3 Sept. 21 (H) Scaling – Advanced CMOS Technologies - FinFETs Sept. 22 (F) Nanofab Lab

6

Sept. 26 (T) No class Sept. 27 (W) VLSI Lab 4 – session 1 Sept. 28 (H) No class Sept. 29 (F) Nanofab Lab

7

Oct. 3 (T) SRAM design with advanced memory technologies Oct. 4 (W) VLSI Lab 4 – session 2 Oct. 5 (H) Non-volatile Memory Arrays Oct. 6 (F) Nanofab Lab

8

Oct. 10 (T) Fall break Oct. 11 (W) Fall break Oct. 12 (H) Fall break Oct. 13(F) Fall break

9

Oct. 17 (T) Non-volatile Memory Arrays Oct. 18 (W) VLSI Lab 5 Oct. 19 (H) Dynamic Memory Arrays Oct. 20 (F) Nanofab Lab

10

Oct. 24 (T) Other memory arrays Oct. 25 (W) VLSI Lab 6 Oct. 26 (H) Emerging Non-volatile Memory Arrays Oct. 27 (F) Nanofab Lab

11 Oct. 31 (T) Emerging Non-volatile Memory Arrays Nov. 1 (W) VLSI Lab 7 Nov. 2 (H) No class

Nov. 3 (F) Nanofab Lab

12

Nov. 7 (T) Design with Non-volatile Emerging Technologies Nov. 8 (W) VLSI Lab 8 Nov. 9 (H) Design with Non-volatile Emerging Technologies Nov. 10 (F) Nanofab Lab

13

Nov. 14 (T) IMFT guest lecture: Reliability in Flash Nov. 15 (W) VLSI Lab 9 Nov. 16 (H) IMFT guest lecture: Probing and characterization Nov. 17 (F) Nanofab Lab

14

Nov. 21 (T) IMFT guest lecture: integration Nov. 22 (W) VLSI Lab buffer Nov. 23(H) Thanksgiving Nov. 24 (F) Thanksgiving

15

Nov. 28 (T) Research Activity Nov. 29 (W) VLSI Lab buffer Nov. 30 (H) No class Dec. 1 (F) Nanofab lab

16

Dec. 5 (T) Research Activity Dec. 6 (W) Oral presentations – groups of 2 – 2p. IEDM paper for grads Dec. 7(H) Exercise session Dec. 8 (F) Reading day

17 Dec. 12 (T) Final exam - 10:30 am – 12:30 pm Legend:

Class Guest lectures Exams Labs Holidays / No Class