copyright agrawal, 2011lecture 1: introduction1 low-power design of digital vlsi circuits...

Copyright Agrawal, 2011Copyright Agrawal, 2011 Lecture 1: IntroductionLecture 1: Introduction 11

Low-Power Design of Digital VLSI CircuitsLow-Power Design of Digital VLSI Circuits

Introduction to Low Power DesignIntroduction to Low Power Design

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal


Course ObjectivesCourse Objectives

Low-power is a current need in VLSI Low-power is a current need in VLSI design.design.

Learn basic ideas, concepts, theory and Learn basic ideas, concepts, theory and methods.methods.

Gain experience with techniques and Gain experience with techniques and tools.tools.

Course DescriptionCourse Description


This course is designed for the MTech program in VLSI at IIT, Delhi. It is patterned after a one-semester graduate-level course offered at Auburn University. A set of 16 lectures that include classroom exercises provide understanding of theoretical and practical aspects of power and energy in digital VLSI systems. The course fulfills a basic need of today’s industrial design environment. Specific topics include power components of digital CMOS circuits, power analysis, glitch elimination for reducing dynamic power, dual-threshold design for reduced static power, voltage and frequency scaling*, power management in memories* and microprocessors*, parallelism for power saving, battery management*, test power*, and ultra-low voltage (subthreshold) logic circuits*, low power technologies (domino CMOS, pass transistor logic)*, adiabatic logic*.

________________* Not included in short course.

OutlineOutline Lecture 1:Lecture 1: Introduction (37)Introduction (37) * Number of slides* Number of slides Homework 1 (10 points)Homework 1 (10 points) Lecture 2:Lecture 2: Power dissipation of CMOS Circuits (46):Power dissipation of CMOS Circuits (46): Lecture 3:Lecture 3: Power of a transitionPower of a transition Lecture 4:Lecture 4: Dynamic (logic, glitch, short-circuit) power, static powerDynamic (logic, glitch, short-circuit) power, static power Homework 2 (10 points)Homework 2 (10 points) Lecture 5:Lecture 5: Gate-level power analysis (56):Gate-level power analysis (56): Lecture 6:Lecture 6: Logic simulation, delay estimationLogic simulation, delay estimation Lecture 7:Lecture 7: Transition density, Probabilistic methodsTransition density, Probabilistic methods Lecture 8:Lecture 8: Power calculationPower calculation Homework 3 (10 points)Homework 3 (10 points) Lecture 9:Lecture 9: Linear Programming – A Mathematical optimization technique (44):Linear Programming – A Mathematical optimization technique (44): Lecture 10:Lecture 10: Examples of LP and ILP optimizationExamples of LP and ILP optimization Homework 4 (10 points)Homework 4 (10 points) Lecture 11:Lecture 11: Gale-level power optimization (59):Gale-level power optimization (59): Lecture 12:Lecture 12: Glitch-free design for reduced dynamic powerGlitch-free design for reduced dynamic power Lecture 13:Lecture 13: Dual-threshold design for reduced leakageDual-threshold design for reduced leakage Lecture 14:Lecture 14: ExamplesExamples Lecture 15:Lecture 15: Multicore design for low power (23) Multicore design for low power (23) Homework 5 (10 points)Homework 5 (10 points) Lecture 16:Lecture 16: Test Power (52)Test Power (52) Lecture 17:Lecture 17: Test Power (continued)Test Power (continued) EXAM (50 points)EXAM (50 points)

Copyright Agrawal, 2011Copyright Agrawal, 2011Lecture 1: IntroductionLecture 1: Introduction 44

ScheduleSchedule July 26, 2011 – 4:00-5:30PM Lecture 1July 26, 2011 – 4:00-5:30PM Lecture 1 July 27, 2011 – 4:00-5:30PM Lectures 2 and 3July 27, 2011 – 4:00-5:30PM Lectures 2 and 3 July 28, 2011 – 4:00-5:30PM Lectures 4, 5 and 6July 28, 2011 – 4:00-5:30PM Lectures 4, 5 and 6 July 29, 2011 – 4:00-5:30PM Lectures 6 (cont.), 7 and 8July 29, 2011 – 4:00-5:30PM Lectures 6 (cont.), 7 and 8 July 30, 2011 – 4:00-5:30PM Lectures 9 and 10July 30, 2011 – 4:00-5:30PM Lectures 9 and 10 Aug 1, 2011 – 4:00-5:30PM Lectures 11 and 12Aug 1, 2011 – 4:00-5:30PM Lectures 11 and 12 Aug 2, 2011 – 4:00-5:30PM Lectures 13 and 14Aug 2, 2011 – 4:00-5:30PM Lectures 13 and 14 Aug 3, 2011 – 4:00-5:30PM Lecture 15Aug 3, 2011 – 4:00-5:30PM Lecture 15 Aug 4, 2011 – 4:00-5:30PM Lecture 16Aug 4, 2011 – 4:00-5:30PM Lecture 16 Aug 5, 2011 – 4:00-5:30PM Lecture 17Aug 5, 2011 – 4:00-5:30PM Lecture 17 Aug 6, 2011 – EXAMAug 6, 2011 – EXAM



Power Consumption of VLSI ChipsPower Consumption of VLSI Chips

Why is it a concern?


ISSCC, Feb. 2001, KeynoteISSCC, Feb. 2001, Keynote“Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now.

“Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .”

Patrick P. Gelsinger Senior Vice PresidentGeneral ManagerDigital Enterprise Group INTEL CORP.


VLSI Chip Power DensityVLSI Chip Power Density

40048008

80808085

8086

286386

486Pentium®

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Po

wer

Den

sity

(W

/cm

2 )

Hot Plate

NuclearReactor

RocketNozzle

Sun’sSurface

Source: Intel


SIA Roadmap for Processors (1999)SIA Roadmap for Processors (1999)YearYear 19991999 20022002 20052005 20082008 20112011 20142014

Feature size (nm)Feature size (nm) 180180 130130 100100 7070 5050 3535

Logic transistors/cmLogic transistors/cm22 6.2M6.2M 18M18M 39M39M 84M84M 180M180M 390M390M

Clock (GHz)Clock (GHz) 1.251.25 2.12.1 3.53.5 6.06.0 10.010.0 16.916.9

Chip size (mmChip size (mm22)) 340340 430430 520520 620620 750750 900900

Power supply (V)Power supply (V) 1.81.8 1.51.5 1.21.2 0.90.9 0.60.6 0.50.5

High-perf. Power (W)High-perf. Power (W) 9090 130130 160160 170170 175175 183183

Source: http://www.semichips.org


Recent DataRecent Data

Source: http://www.eetimes.com/story/OEG20040123S0041


Low-Power DesignLow-Power DesignDesign practices that reduce power Design practices that reduce power

consumption by at least one order of consumption by at least one order of magnitude; in practice 50% reduction magnitude; in practice 50% reduction is often acceptable.is often acceptable.

Low-power design methods:Low-power design methods:Algorithms and architecturesAlgorithms and architecturesHigh-level and software techniquesHigh-level and software techniquesGate and circuit-level methodsGate and circuit-level methodsTest powerTest power


VLSI Building BlocksVLSI Building BlocksFinite-state machine (FSM)Finite-state machine (FSM)BusBusFlip-flops and shift registersFlip-flops and shift registersMemoriesMemoriesDatapathDatapathProcessorsProcessorsAnalog circuitsAnalog circuitsRF componentsRF components


Specific Topics in Low-PowerSpecific Topics in Low-Power Power dissipation in CMOS circuitsPower dissipation in CMOS circuits Device technologyDevice technology

Low-power CMOS technologiesLow-power CMOS technologies Energy recovery methodsEnergy recovery methods

Circuit and gate level methodsCircuit and gate level methods Logic synthesisLogic synthesis Dynamic power reduction techniquesDynamic power reduction techniques Leakage power reductionLeakage power reduction

System level methodsSystem level methods MicroprocessorsMicroprocessors Arithmetic circuitsArithmetic circuits Low power memory technologyLow power memory technology

Test PowerTest Power Power estimationPower estimation


Some ExamplesSome Examples


State Encoding for a CounterState Encoding for a CounterTwo-bit binary counter:Two-bit binary counter:

State sequence, 00 → 01 → 10 → 11 → 00State sequence, 00 → 01 → 10 → 11 → 00Six bit transitions in four clock cyclesSix bit transitions in four clock cycles6/4 = 1.5 transitions per clock6/4 = 1.5 transitions per clock

Two-bit Gray-code counterTwo-bit Gray-code counterState sequence, 00 → 01 → 11 → 10 → 00State sequence, 00 → 01 → 11 → 10 → 00Four bit transitions in four clock cyclesFour bit transitions in four clock cycles4/4 = 1.0 transition per clock4/4 = 1.0 transition per clock

Gray-code counter is more power efficient.Gray-code counter is more power efficient.

G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Kluwer Academic Publishers (now Springer), 1998.


Binary Counter: Original Binary Counter: Original EncodingEncoding

Present Present statestate Next stateNext state

aa bb AA BB

00 00 00 11

00 11 11 00

11 00 11 11

11 11 00 00

A = a’b + ab’ = a xor bB = a’b’ + ab’ = b’

A

B

a

b

CKCLR


Binary Counter: Gray EncodingBinary Counter: Gray Encoding

Present Present statestate Next stateNext state

aa bb AA BB

00 00 00 11

00 11 11 11

11 00 00 00

11 11 11 00

A = a’b + ab = bB = a’b’ + a’b = a’

A

B

a

b

CKCLR


Three-Bit CountersThree-Bit CountersBinaryBinary Gray-codeGray-code

StateState No. of togglesNo. of toggles StateState No. of togglesNo. of toggles

000000 -- 000000 --

001001 11 001001 11

010010 22 011011 11

011011 11 010010 11

100100 33 110110 11

101101 11 111111 11

110110 22 101101 11

111111 11 100100 11

000000 33 000000 11

Av. Transitions/clock = 1.75Av. Transitions/clock = 1.75 Av. Transitions/clock = 1Av. Transitions/clock = 1


N-Bit Counter: Toggles in Counting CycleN-Bit Counter: Toggles in Counting Cycle Binary counter: T(binary) = 2(2Binary counter: T(binary) = 2(2NN – 1) – 1) Gray-code counter: T(gray) = 2Gray-code counter: T(gray) = 2NN

T(gray)/T(binary) = 2T(gray)/T(binary) = 2N-1N-1/(2/(2NN – 1) → 0.5 – 1) → 0.5

BitsBits T(binary)T(binary) T(gray)T(gray) T(gray)/T(binary)T(gray)/T(binary)

11 22 22 1.01.0

22 66 44 0.66670.6667

33 1414 88 0.57140.5714

44 3030 1616 0.53330.5333

55 6262 3232 0.51610.5161

66 126126 6464 0.50790.5079

∞∞ -- -- 0.50000.5000


FSM State EncodingFSM State Encoding

11

01000.1

0.10.4

0.3

0.6 0.9

0.6

01

11000.1

0.10.4

0.3

0.6 0.9

0.6

Expected number of state-bit transitions:

1(0.3+0.4+0.1) + 2(0.1) = 1.0

Transition probability based on

PI statistics

State encoding can be selected using a power-based cost function.

2(0.3+0.4) + 1(0.1+0.1) = 1.6


FSM: Clock-GatingFSM: Clock-GatingMoore machine: Outputs depend only on Moore machine: Outputs depend only on

the state variables.the state variables. If a state has a self-loop in the state transition If a state has a self-loop in the state transition

graph (STG), then clock can be stopped graph (STG), then clock can be stopped whenever a self-loop is to be executed.whenever a self-loop is to be executed.

Sj

SiSk

Xi/Zk

Xk/Zk

Xj/Zk

Clock can be stopped when (Xk, Sk) combination occurs.


Clock-Gating in Moore FSMClock-Gating in Moore FSM

Combinational logic

LatchClock

activation logic

Flip

-flo

ps

PI

CK

PO

L. Benini and G. De Micheli,Dynamic Power Management,Boston: Springer, 1998.


Bus Encoding for Reduced PowerBus Encoding for Reduced Power Example: Four bit busExample: Four bit bus

0000 → 1110 has three transitions.0000 → 1110 has three transitions. If bits of second pattern are inverted, then 0000 → If bits of second pattern are inverted, then 0000 →

0001 will have only one transition.0001 will have only one transition. Bit-inversion encoding for N-bit bus:Bit-inversion encoding for N-bit bus:

Number of bit transitions0 N/2 N

N

N/2

0Nu

mb

er

of b

it tr

an

sitio

ns

afte

r in

vers

ion

en

cod

ing


Bus-Inversion Encoding LogicBus-Inversion Encoding Logic

Polarity decision

logic

Se

nt d

ata

Re

ceiv

ed

da

ta

Bus register

Polarity bit

M. Stan and W. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 49-58, March 1995.


Clock-Gating in Low-Power Flip-FlopClock-Gating in Low-Power Flip-Flop

D QD

CK

Example: Benchmark S5378Example: Benchmark S5378 TSMC025 CMOS technologyTSMC025 CMOS technology 50ns clock50ns clock 1,000 random vectors1,000 random vectors Reference: J. D. Alexander, Reference: J. D. Alexander, Simulation Based Power Estimation Simulation Based Power Estimation

for Digital CMOS Technologiefor Digital CMOS Technologies, Master’s Thesis, Auburn s, Master’s Thesis, Auburn University, December 2008, Section 3.8.University, December 2008, Section 3.8.

ClockNumber of comb.

gates

Number of flip-flops

Power consumption in μW

Comb. gates

Flip-flops Total

Ungated 2,958 179 330 752 1,082

Gated 3,316 179 276 32 308



Example: Shift RegisterExample: Shift Register

D Q D Q D Q

D QD QD Q

D Q

D Q

D

CK

Output


Reduced-Power Shift RegisterReduced-Power Shift Register

D Q D Q D Q

D QD QD Q

D Q

D Q

D

CK(f/2)

mu

ltip

lexe

r

Output

Flip-flops are operated at full voltage and half the clock frequency.


Power Consumption of Shift RegisterPower Consumption of Shift Register

P = C’VDD2f/n

Degree of parallelism, n1 2 4

No

rma

lize

d p

ow

er

1.0

0.5

0.25

0.0

Deg. of Deg. of parallelismparallelism

Freq Freq (MHz)(MHz)

Power Power ((μμW)W)

11 33.033.0 15351535

22 16.516.5 887887

44 8.258.25 738738

16-bit shift register, 2μ CMOS

C. Piguet, “Circuit and Logic LevelDesign,” pages 103-133 in W. Nebeland J. Mermet (ed.), Low PowerDesign in Deep SubmicronElectronics, Springer, 1997.


Books on Low-Power Design (1) Books on Low-Power Design (1) L. Benini and G. De Micheli, L. Benini and G. De Micheli, Dynamic Power Management Design Dynamic Power Management Design

Techniques and CAD ToolsTechniques and CAD Tools, Boston: Springer, 1998., Boston: Springer, 1998. T. D. Burd and R. A. Brodersen, T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Energy Efficient Microprocessor

DesignDesign, Boston: Springer, 2002., Boston: Springer, 2002. A. Chandrakasan and R. Brodersen, A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Low-Power Digital CMOS

DesignDesign, Boston: Springer, 1995., Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, A. Chandrakasan and R. Brodersen, Low-Power CMOS DesignLow-Power CMOS Design, New , New

York: IEEE Press, 1998.York: IEEE Press, 1998. J.-M. Chang and M. Pedram, J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Power Optimization and Synthesis at

Behavioral and System Levels using Formal MethodsBehavioral and System Levels using Formal Methods, Boston: , Boston: Springer, 1999.Springer, 1999.

D. Chinnery and K. Keutzer, D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC & Closing the Power Gap Between ASIC & Custom: Tools and Techniques for Low Power Design, Custom: Tools and Techniques for Low Power Design, Springer, Springer, 2007, ISBN 0387257632, 97803872576312007, ISBN 0387257632, 9780387257631..

M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Advanced Low-Power Digital Circuit TechniquesPower Digital Circuit Techniques, Boston: Springer, 1997., Boston: Springer, 1997.


Books on Low-Power Design (2)Books on Low-Power Design (2) P. Girard, N. Nicolici and X. Wen, P. Girard, N. Nicolici and X. Wen, Power-Aware Testing and Test Power-Aware Testing and Test

Strategies for Low Power DevicesStrategies for Low Power Devices, Springer, 2010., Springer, 2010. R. Graybill and R. Melhem, R. Graybill and R. Melhem, Power Aware ComputingPower Aware Computing, New York: , New York:

Plenum Publishers, 2002.Plenum Publishers, 2002. S. Iman and M. Pedram, S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Logic Synthesis for Low Power VLSI

DesignsDesigns, Boston: Springer, 1998., Boston: Springer, 1998. M. Keating, D. Flynn, R. Aitken, A. Gibbons and K. Shi, M. Keating, D. Flynn, R. Aitken, A. Gibbons and K. Shi, Low Power Low Power

Methodology Manual For System-on-Chip Design, Methodology Manual For System-on-Chip Design, 1st ed. 2007. 1st ed. 2007. Corr. 2nd printing, 2007, XVI, 304 p., Hardcover, ISBN: 978-0-387-Corr. 2nd printing, 2007, XVI, 304 p., Hardcover, ISBN: 978-0-387-71818-7.71818-7.

J. B. Kuo and J.-H. Lou, J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI CircuitsLow-Voltage CMOS VLSI Circuits, New , New York: Wiley-Interscience, 1999.York: Wiley-Interscience, 1999.

J. Monteiro and S. Devadas, J. Monteiro and S. Devadas, Computer-Aided Design Techniques Computer-Aided Design Techniques for Low Power Sequential Logic Circuitsfor Low Power Sequential Logic Circuits, Boston: Springer, 1997., Boston: Springer, 1997.

S. G. Narendra and A. Chandrakasan, S. G. Narendra and A. Chandrakasan, Leakage in Nanometer Leakage in Nanometer CMOS TechnologiesCMOS Technologies, Boston: Springer, 2005., Boston: Springer, 2005.


Books on Low-Power Design (3)Books on Low-Power Design (3) W. Nebel and J. Mermet, W. Nebel and J. Mermet, Low Power Design in Deep Submicron Low Power Design in Deep Submicron

ElectronicsElectronics, Boston: Springer, 1997., Boston: Springer, 1997. N. Nicolici and B. M. Al-Hashimi, N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Power-Constrained Testing of VLSI

CircuitsCircuits, Boston: Springer, 2003., Boston: Springer, 2003. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic,

Digital System Clocking: High Performance and Low-Power Digital System Clocking: High Performance and Low-Power AspectsAspects, Wiley-IEEE, 2005., Wiley-IEEE, 2005.

M. Pedram and J. M. Rabaey, M. Pedram and J. M. Rabaey, Power Aware Design MethodologiesPower Aware Design Methodologies, , Boston: Springer, 2002.Boston: Springer, 2002.

C. Piguet, C. Piguet, Low-Power Electronics DesignLow-Power Electronics Design, Boca Raton: Florida: CRC , Boca Raton: Florida: CRC Press, 2005.Press, 2005.

J. M. Rabaey and M. Pedram, J. M. Rabaey and M. Pedram, Low Power Design MethodologiesLow Power Design Methodologies, , Boston: Springer, 1996.Boston: Springer, 1996.

S. Roudy, P. K. Wright and J. M. Rabaey, S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Energy Scavenging for Wireless Sensor NetworksWireless Sensor Networks, Boston: Springer, 2003., Boston: Springer, 2003.


Books on Low-Power Design (4)Books on Low-Power Design (4) K. Roy and S. C. Prasad, K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit DesignLow-Power CMOS VLSI Circuit Design, ,

New York: Wiley-Interscience, 2000.New York: Wiley-Interscience, 2000. E. Sánchez-Sinencio and A. G. Andreaou, E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Low-Voltage/Low-Power

Integrated Circuits and Systems – Low-Voltage Mixed-Signal Integrated Circuits and Systems – Low-Voltage Mixed-Signal CircuitsCircuits,, New York: IEEE Press, 1999. W. A. Serdijn, New York: IEEE Press, 1999. W. A. Serdijn, Low-Voltage Low-Voltage Low-Power Analog Integrated CircuitsLow-Power Analog Integrated Circuits, Boston: Springer, 1995., Boston: Springer, 1995.

S. Sheng and R. W. Brodersen, S. Sheng and R. W. Brodersen, Low-Power Wireless Low-Power Wireless Communications: A Wideband CDMA System DesignCommunications: A Wideband CDMA System Design, Boston: , Boston: Springer, 1998.Springer, 1998.

G. Verghese and J. M. Rabaey, G. Verghese and J. M. Rabaey, Low-Energy FPGAsLow-Energy FPGAs, Boston: , Boston: Springer, 2001.Springer, 2001.

G. K. Yeap, G. K. Yeap, Practical Low Power Digital VLSI DesignPractical Low Power Digital VLSI Design, Boston: , Boston: Springer, 1998.Springer, 1998.

K.-S. Yeo and K. Roy, K.-S. Yeo and K. Roy, Low-Voltage Low-Power SubsystemsLow-Voltage Low-Power Subsystems, , McGraw Hill, 2004.McGraw Hill, 2004.


Books Useful in Low-Power Design Books Useful in Low-Power Design A. Chandrakasan, W. J. Bowhill and F. Fox, A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High-Performance Design of High-Performance

Microprocessor Circuits, Microprocessor Circuits, New York: IEEE Press, 2001.New York: IEEE Press, 2001. R. C. Jaeger and T. N. Blalock, R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Microelectronic Circuit Design, Third

EditionEdition, McGraw-Hill, 2006., McGraw-Hill, 2006. S. M. Kang and Y. Leblebici, S. M. Kang and Y. Leblebici, CMOS Digital Integrated CircuitsCMOS Digital Integrated Circuits, New York: , New York:

McGraw-Hill, 1996.McGraw-Hill, 1996. E. Larsson, E. Larsson, Introduction to Advanced System-on-Chip Test Design and Introduction to Advanced System-on-Chip Test Design and

OptimizationOptimization, Springer, 2005., Springer, 2005. J. M. Rabaey, A. Chandrakasan and B. Nikolić, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Digital Integrated Circuits,

Second EditionSecond Edition, Upper Saddle River, New Jersey: Prentice-Hall, 2003., Upper Saddle River, New Jersey: Prentice-Hall, 2003. J. Segura and C. F. Hawkins, J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It CMOS Electronics, How It Works, How It

FailsFails, New York: IEEE Press, 2004., New York: IEEE Press, 2004. N. H. E. Weste and D. Harris, N. H. E. Weste and D. Harris, CMOS VLSI Design, Third EditionCMOS VLSI Design, Third Edition, Reading, , Reading,

Massachusetts: Addison-Wesley, 2005.Massachusetts: Addison-Wesley, 2005.


Problem: Bus EncodingProblem: Bus Encoding

A 1-hot encoding is to be used for reducing the capacitive power consumption of an n-bit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the un-coded buses. Show that n ≥ 4 is essential for the 1-hot encoding to be beneficial.

Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp. 224-225. [Hint: You should be able to solve this problem without the help of the reference.]


Solution: Bus EncodingSolution: Bus EncodingUn-coded bus: Two consecutive bits on a wire can be 00, 01, 10 and 11, each occurring with a probability 0.25. Considering only the 0→1 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is ¼. Therefore, the average per pattern energy for all n wires of the bus is CV 2n/4.

Encoded bus: Encoded bus contains 2n wires. The 1-hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2–n, and CV 2 with probability 1 – 2–n. The average per pattern energy for the 1-hot encoded bus is CV 2(1 – 2–n).


Solution: Bus Encoding (Cont.)Solution: Bus Encoding (Cont.)Power ratio = Encoded bus power / un-coded bus power

= 4(1 – 2–n)/n → 4/n for large nFor the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 – 2–n)/n ≤ 1, or 1 – 2–n ≤ n/4, or n/4 ≥ 1 (approximately) → n ≥ 4.The following table shows 1-hot encoded bus power ratio as a function of bus width:

n 4(1 – 2–n)/n n 4(1 – 2–n)/n

1 2.0000 8 0.4981

2 1.5000 16 0.2500 = 1/4

3 1.1670 32 1/8

4 0.9375 64 1/16

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