copyright © 2009,intel corporation. all rights reserved. auto eco flow development for functional...

Copyright © 2009,Intel Corporation. All rights reserved.

Auto ECO Flow Development For Functional ECO Using Efficient Error Rectification Method Based On FV Tool

Auto ECO Flow Development For Functional ECO Using Efficient Error Rectification Method Based On FV Tool

Andal Jayalakshmi

Intel Corporation, Penang, Malaysia

[email protected]

Copyright © 2009, Intel Corporation.All rights reserved.

DisclaimersDisclaimers

The flow results discussed have been simulated and are

provided for informational purposes only. Results were

derived using EDA software tool that run on an Intel’s

VLSI design. Any difference in VLSI design or software

tool or configuration or flow may affect actual results.

This work/manuscript does not in any way constitute an

Intel endorsement of a product or supplier.


ECO (Engineering Change Order)ECO (Engineering Change Order)

ECO is a capability to integrate late RTL changes into converged

netlist as re-synthesis involves high re-convergence cost

Simple ECO changes may even require a lot of efforts to make the

corresponding changes in the converged netlist due to the deep

optimizations done by the synthesis tools.

RTL Logic Synthesis Netlist

ConvergedNetlist

Scan , ClockStitch

NewRTL ECO Tool Converged

Netlist


Auto ECO Flow Auto ECO Flow

The Auto ECO Flow encompasses 5 stages which includes verification of ECO

collaterals, rectification of error and verification of ECO changes made by the

tool.

Screen stage – Verify the netlists for old RTL and converged design for functional

equivalence as a sanity check for pre-ECO collaterals.

FV stage – Verify the synthesis netlists for Old and New RTL for functional equivalence

to identify the failing fubs to fix.

Rectification stage - Rectify the errors in each of the failing fubs iteratively and obtain

the patches.

Syn stage - Implement the patches on to the converged netlist to get the converged

netlist with the ECO fix.

Verify stage – Verify the netlists for new RTL and the converged design for functional

equivalence to verify the ECO fix.


Syn netlist(for old RTL)

Syn netlist (for New RTL)

Convergednetlist

(for old RTL)

FV(FV stage)

Failing FubsList

Generate Fix (Rectification stage)

Implement Changes

(Syn stage)

Convergednetlist

(for new RTL)

FV (Verify stage)

FV Status and Fix statistics

ECOChange list

FV (Screen stage)

Sanity checkFV rpt

Auto ECO Flow


Sanity Check FVSanity Check FV

This is to verify if the pre-ECO synthesis netlist and the converged design (pre-ECO

post-layout netlist) pass FV.

This is to ensure the correctness of the pre-ECO collaterals such as the netlists and FV

collaterals (scan and CTS mapping information).

The FV is done at the top level as we are only interested to see if they pass or not.

Pre Eco Syn Vs Pre Eco Lay(Top level)


Convergednetlist

(for old RTL)CTS

mapping

Scan ports

Scan constraints

FV RPTEquivalence

Status


FV Collaterals – CTS Mapping FV Collaterals – CTS Mapping

The clock tree which represents more than one clock signal are

to be equated to obtain functional equivalence.

For example the CLK and CLK1 represent the same clock signal.

Example CTS mapping

# Module Dir Old New

Module1 in CLK CLK1

CLK

Module1U1

DFF

U2

DFF

Golden Revised

CLK

Module1U1

DFF

U2

DFFCLK1


FV Collaterals – Scan PortsFV Collaterals – Scan Ports

The scan ports need to be identified to constrain these to proper values to suppress

the scan path from checking.

Whenever the synthesis netlist is checked against converged design the CTS

mapping is essential to remove the Clock and Scan signal differences.

#Module scanin scanin_port

Top scanin scan_in

submod1 scanin scan_in

#Module scanout scanout_port

Top scanout scan_out

submod1 scanout scan_out

#Module constin constin_port value netlist

Top constin scan_en 0 tar

submod1 constin scan_en 0 tar

Module submod1

DFF

Module Top

in1in2

scan_in

scan_en

scan_out


FV Pre-ECO Vs Post-ECO NetlistFV Pre-ECO Vs Post-ECO Netlist

The failing modules are identified by verifying the synthesis netlists for old and new

RTL.

This helps to identify the exact ECO changes to fix, which does not include the clock

and scan differences.

Pre Eco Syn netlistVs

Post Eco Syn netlistHierarchical FV


Fv RPTEquivalence

status for each sub module

Syn netlist(for new RTL)


Error Rectification Error Rectification

Identifies the logic in golden which are equivalent to revised using the FV tool and

reuses this logic.

Rectifies the error in golden by just fixing that particular portion of logic which is

erroneous.

Identifies and reuses the equivalent logic beyond the error boundary.

Uses a BDD for functional equivalence checking during error correction.

GOLDEN CONE

REVISED CONE

FINAL CONE

Error Boundary

ReusedRectif

ied


Generating Equivalent Points Using FV toolGenerating Equivalent Points Using FV tool

Auto ECO Flow uses the FV tool to recursively find equivalent points.

It recurses from the cone tip towards the Primary Inputs (PIs) until an equivalent point is found.

The run time for this depends on the location of the error. If the error lies near to the interfaces,

it will take longer run time.

InterfacesEquivalent points

P

Q

R

S

X

P

Q

R

S

XA

C

B

D

A

B

C

Post-ECO Synthesized NetlistPre-ECO Post Layout Netlist

Combinational logic cloud


Functional Equivalence Checking Using BDDsFunctional Equivalence Checking Using BDDs

The error rectification algorithm employs BDDs for logic function

verification.

These are very useful for on the fly verification compared to FV tools

as they take longer time for loading the design and libraries and are

more suitable for batch mode operations.

The disadvantage of BDDs is that the run time and memory

requirements will grow exponentially as the number of variables in

the logic function increases.


Example ECO Scenario And Error RectificationExample ECO Scenario And Error Rectification

Finds equivalent points as highlighted in yellow below.

Pre-ECO post-layout netlist Post-ECO syn netlist

U6

U5

U2

U7

U5

E11

E6

U1

U4

U6

E1

E10

U8

a

b

c

d

a

b

c

d

e

f

f

U3


Example ECO Scenario And Error Rectification contd…Example ECO Scenario And Error Rectification contd…

It marks all the cells in the sub-cone behind the equivalent points as reused

( shown in yellow) and recreates the remaining logic (shown in red) based on

the ECO netlist while trying to reuse cells (shown in green) in pre-ECO netlist.


U3

U5_ECOU4_ECO

U6_ECO

E11_ECO

E10_ECOE6_ECO

E1_ECO

U7

U5

E11

U1

U4

U6

E1

E10

U8

E6

a

b

c

d

a

b

c

d

e

f

e

f

U2U5

U6


Example ECO Scenario And Error Rectification contd…Example ECO Scenario And Error Rectification contd…

Then it removes the dangling cells which have no loads recursively.


U3

U5

U2 U6

U7

U5

U1

U4

U6

U8

a

b

c

d

e

ff

a

b

c

d

eU5_ECOU4_ECO

U6_ECO


Example ECO Scenario and Error Rectification contd…Example ECO Scenario and Error Rectification contd…

This would then be the final netlist which is equivalent to the post-ECO netlist.


U3

U2

U7

U5

U1

U4

U6

U8

a

b

c

d

e

a

b

c

d

e

ff

U5_ECOU4_ECO

U6_ECO

U6


Converged netlist

(for old RTL)

Syn netlist

(for new RTL)

Rectification Logic

ECO changelist

CTS mapping

Scan ports

Scan constraints

FUB

FV rpt

FUB

Generate ECO FixGenerate ECO Fix

The rectification logic takes the netlists and FV collaterals as the inputs and generates the

ECO changes as a TCL script.


Implement ChangesImplement Changes

The ECO changes are implemented using a synthesis tool. It takes in the

converged netlist and the TCL script as input and generates the final netlist.

The final netlist is not used directly as it is preferred to implement the

changes in the same synthesis environment.

ECO stitchConverged netlist

(for old RTL)

ECO changelist

Converged netlist

(for new RTL)


Post Eco Syn netlist Vs Post Eco Lay netlist

Syn netlist(for new RTL)

Convergednetlist

(for new RTL)CTS

mapping

Scan ports

Scan constraints

FV RPT Equivalence Status

ECO Fix VerificationECO Fix Verification

The final netlist is verified for functional equivalence with the post-ECO-

syn netlist.

This enables the ECO change list generated by the flow to be used

directly in the ECO environment for implementing the changes.


ResultsResults

The flow is successfully used in Intel for various projects and the results obtained in few of the

ECO executions are tabulated here.

The flow is robust enough to handle complex ECOs and the user feedbacks are very encouraging.

The ECO changes are found to be comparable with manual ECO changes.

Though the TPT is high it was acceptable compared to manual ECOs.

S.No Design Size

Cells Count

Cells Added

Cells Deleted

Run Time

1 3.6k -34 99 65 2h

2 2.3k 38 113 75 1h

3 20k 187 187 0 3h

4 0.8k 415 666 251 12h

5 1.6k 196 223 27 2h

6 1.5k 50 203 153 5h

7 1.9k 0 6 6 1h

8 1.8k 13 17 4 1h


Future EnhancementsFuture Enhancements

The TPT of the flow is high due to its functional equivalence

checking mechanism. It relies upon the FV tool for finding equivalent

points and BDDs for logic function verification during error

correction.

The future developments will be focused on improving the TPT

further to exploit the fullest benefits of an automation tool to handle

time critical ECOs.


SummarySummary

FV tool and BDDs were employed for the automation of the ECO

flow.

The ECO changes generated by the Flow was comparable to

manual ECOs as per the feedback from the customers.

It has improved the productivity to a large extent by reducing the ECO

efforts from weeks to hours.

The automation has enabled very complex ECOs which are

otherwise dropped as manually fixing them is impossible due to the

critical ECO schedules.

copyright © 2009,intel corporation. all rights reserved. auto eco flow development for functional...

Documents

functional eco

eco fix

old rtl fv fv stage

fv preeco vs posteco

preeco synthesis netlist

old rtl converged netlist

new rtl fv

new rtl converged netlist