copyright © 2006 mips technologies, inc and first silicon solutions. all rights reserved. at the...

Copyright © 2006 MIPS Technologies, Inc and First Silicon Solutions. All rights reserved.

At the core of the user experience ®

Getting System On Silicon to market Faster ®

Request-Response Trace for Bus Performance Analysis

Dr. Neal [email protected]

Jan. 2007

Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved

Introduction

MIPS Technologies is Leader in High Performance Embedded RISC Processors

MIPS32® 34KTM Multi-threaded RISC Processor SoC-IT Platforms Best in class applications and tools eco-systems

FS2 is Instrumentation IP and Tools Division of MIPS On-Chip Instrumentation (OCI®) Leadership Integrated Trace and Analysis Solutions for

Embedded Processor, Logic and On- Chip Bus IP Leading edge on-chip analysis tools for MIPS

based systems – RRT performance analysis as only one example


SoC Analysis and Debug Issues

Visibility and optimization is crucial to embedded design success Difficult to fix/optimize what you can not see - Unexpected on-chip Inter-relationships not always intuitive

System on Silicon Instrumentation Requirements Visibility - into non-observable sub-system interfaces

– On-chip analysis complements EDA verification Interoperable control with processor debug capabilities

– Cross-triggering, synchronization for full view of problems Reasonable gate size and trace speeds

– Range of features configurable to system requirements IO requirements

– Leverage existing debug interfaces i.e. JTAG– High performance IO allows more extensive trace


SoC On-Chip Instrumentation Evolution

Debug-Difficulty(gates/pins)

ICE /BDM

AnalysisTools

JTAG (Scan, BISTRun Ctrl)

System Level Embedded

Instrumentation

Embedded Processor / Logic Trace

1980s 1990s 2000s

Embedded Systems

ASICS

SoC (RISC+IP+RAM)

Platform SoC (Multi-Core)

50K

20K

8K

2.5K

1K

Complexity of Embedded Analysis requirement keeps increasing • Gates increase geometrically - Pins increase linearly • Significant bandwidth for leading architectures • More complex analysis needs Instrumentation

The New Frontier

EJTAG Navigator RRTPDtrace MIPS Solutions


Modeling and Verification Abstraction

SystemAnalysis

Focus

CoreIP

Modeling and Verification Abstraction

System Initialization

Instruction Level/Bus Functional

HardwareSimulation

Application Software

RTL Diagnostics

RTOSIntegration

ESL

Focus on Hardware Bugs Focus on Software Bugs

Point were Hardware is “assumed working”

HardwarePrototype/Emulation

Software DebuggerSystem platform

Multi-coreIntegration issues

Pre-silicon – EDA based analysis

Post-silicon – In System centric analysis

SystemPlatform


Drivers for Request Response Trace

Other Layers

Initiator Agent

IA

TA

IA

dedicatedlinks

OCPsocket

OCPsocket

AXIsocket

bridge

AHBsocket

bridge

OCPsocket

bridge

APBsocket

OCP socket

AHB socket

XBarfabric

RP

TargetAgent

IAPP PP

TA

bridge

PP PP

Shared Link

fabric

TA

RP

RP RP RP RP

RP RP RP RP

bridge

Source: 2006 Sonics, Inc.

Analysis of complex on chip interconnection networks Need to analyze transfer/response latencies Lower overhead analysis for critical information


RRT as a Performance Analysis Trace System

MIPS OCP IF

Other coreOCP IF

Selected IP IF

processor trace

Synch signals

Mictor 2

JTAG port

SystemTraceProbe

RRT agent –OCP capture, filter, format

RRT OCPagent -

RRT custom agent -

b

RRT AHBagent -

Navigator RRT Trace

Port

Combiner/Scheduler

“trace funnel”

DMAAHB IF

MulticoreProcessor

trace Mictor 1

Trace funnel provides prioritized transfers

Agents provide in line filtering formatting of bus data

HOSTPC

(Win/Linux)

Analyzer tools

USBEthernet


Point-to-point Timing A to B event timing measurements: event A starts counter,

event B stops counter read out duration via JTAG port, or save counter values into trace then zero counter in single

cycle

Benefit: measure loop times of algorithms, task executions, interrupt handlers, waiting for resource

System Performance Measurements

Trace history of counted values

Observe change in measured values over multiple occurrences

Example: multiple durations between A-B events

Benefit: see how loop times change over the real-time execution on system

Trace Performance Profiling


System Level Performance Analysis

Types of analysis that are important Measure activity - bus utilization, caches efficiency, co-

processors, interrupts, peripheral device events Measure latencies - interrupts, bus access, DMA transfers loop times of processing network packets, DSP Blocks Monitoring bus bandwidth utilization, efficiency Caches hit/miss ratios, DRAM pages, processor stalls

RRT provides Analysis of System operations Timestamping for interval measurements relative to real time Counter and trigger resources for real time event rates or

duration measures


On Chip Performance Trace - RRT

System Bus Fabric

Other IP blocks(video, imaging . . . )

PDtrace EJTAG

MIPS core

OtherIP

JTAG &TRACEPORT

(To SNPIO)

Trace Funnel

Cross Triggers

JTAGTAP

RRTraceAgents

RRTraceAgents

RRTraceAgents

Selective trace capability Simple event monitoring Triggers, counters in probe Probe based Trace filtering and alignment Trace limited by Port Bandwidth


RRT Debug FlowRRT IP Integration

design RTL files

Trigger/ Trace Requirements

Instrumented RTL files

SYNTHESISPlace & Route

To target

Trace and post processing GUI

Trace data

(from SNP)

VCD Export

Analyzerconfiguration

Instrumentation configuration file

Customer EDA tools

Environment


Mobileye EyeQ2 Analysis Needs

Complex automotive image processing IC 10 cores (MIPS 34K, DSPs, DMA) Complex OCP/AMBA system network Multi-layer Sonics SMX Complex memory subsystems

Debug Performance and bottlenecks Analyze bus latencies and throughput Trace bus control transactions of 4

concurrent transactions (34K, DSP, DMA) Trace full address for any transaction Correlate Bus transactions to PDtrace Track active threads to bus operations Trace at least one image frame (>1 Gbyte)

Low overhead debug solution (minimal buffering) Reduced operating speed OK Pins available for dual trace ports


RRT Instrumentation for Mobileye

Request-Response Trace – Real time Bus Transaction Analysis Solution built around SNP

64 pin target interface– Allows processor and bus trace

Deep (2 Gbyte) Probe Trace Buffer– Multi-frame trace

Complex triggers, timestamps, . . .

RRT agents and funnel IP Minimized on chip Logic Complex trace resources in probe

Upgraded PDtrace™ for multicore trace Multicore PDtrace Funnel IP

PDtrace/RRT Correlation in SW Request-Response delay analysis PDtrace/RRT Bus Correlation

Mictor 1

Mictor 2

JTAG port

FS2System Probe

RRT Agent (capture,

filter, format)

RRT Agent

RRT Agent

RRT Agent

RRT Trace

Port

RRT Trace Funnel

(combiner/Scheduler)

MIPS 0 (34K 2x OCP)

MIPS 1 (34K 2x OCP)

DMA(AHB)

VCE (XB1OCP)

MulticorePDtraceFunnel/

Port


First Silicon Solutions Introduces System Navigator Pro™ Series of High Performance Trace Probes

Next-Generation Hardware Platform Addresses SoC Debug and System-Level Verification

PORTLAND, OR, Jan. 30, 2007 -- First Silicon Solutions (FS2), a division of MIPS Technologies, Inc. (NASDAQ: MIPS), today announced the production release of System Navigator Pro™, a high performance high capacity trace probe family designed to address complex SoC debug and system-level verification. . . .


New System Navigator Pro Probe

System Navigator Pro (SNP) provides next generation probe technology for debug applications that require massive amounts of off-chip trace capture

Supports all JTAG functions of Sys Nav probe 38-pin Mictor target IO (up to 2 per probe)

– 32 bits of trace data per Mictor connection Up to 2G byte deep trace buffer Supports trace bandwidth of up to 16 Gbps

– Target interface speed up to 500MHz – USB 2.0 and 10/100/1G Ethernet PC interfaces

Supports current MDI 3rd party tools interface SNP provides value added analysis with

– Malta boards – FPGA based prototyping environments– Systems Emulation tools

System Level Debug Initiative Support Capture of large amounts of bus and processor data for post processing


System Debugger Environment Architecture

Windows MABILib/MDILib DLL

PC Interface

Cross Trigger

CommonTcl/Tk CLI

FS2 System Navigator JTAG Probe

3rd Party Source Level Debuggers

MDI

MIPSProcessor

Core

PDtrace OCI

EJTAGBus Trace OCI

JTAG PortTrace Port

OptionalEclipse IDE

GDB SDK

Off-Chip

On-ChipTrace RAM

Trace Funnel

BusTrace and Triggering GUI

Bus Data

• FS2 In System Analyzer (ISA) - Standards based IDE • Plug and play with all MDI complaint 3rd party tools • User transparent concurrent debug access (many cores/many debuggers)• Eclipse, Tcl/TK, MDI, XML, text based scripting and configuration


System Navigator Pro RRT support

•Provide correlated view of processor and bus operations• latency measurements outside of core visibility

• Common views of core and system performance • Migration to unified display and GUI


Trigger Trace from Applications or IP• Processor operations can drive analysis operations

• ex. Cross-Triggering Bus Trace with MIPS Source Code • Trigger bus trace from Breakpoint• Use bus condition as breakpoint input


On-Chip Instrumentation IP• MIPS Processor Instruments• Integrated Bus Analyzers• Multi-Core debug• Performance Analysis• Application specific/custom debug blocks

System Navigator Probes• USB 2.0, Ethernet and ECP host PC

connections• 14-pin (EJTAG & on-chip PDTrace) or 38-pin Mictor (EJTAG & off-chip PDTrace) target connections• Integrated with MIPS SDE software• Low speed and RTCK support for emulation systems integration

Software Tools and Interfaces• Integrated w/MIPS GDB• Complete EJTAG & PDTrace support• On-chip and off-chips trace tools• Performance Monitoring tools• Supports 3rd party debugger and RTOS interfaces

FS2 = Comprehensive Debug Solutions

copyright © 2006 mips technologies, inc and first silicon solutions. all rights reserved. at the...

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