copyright © 2005-2007 curt hill digital logic circuits electronics for boolean algebra

Copyright © 2005-2007 Curt Hill

Digital Logic Circuits

Electronics for Boolean Algebra


Multiplexers

• A multiplexer funnels many inputs into one output

• There are data lines and control lines

• There are as many data lines as 2 the power of control lines

• The control line chooses one of the data lines to be selected


Implementation

• There is one AND for each data line– Each AND has one input from the

data line– Each AND gets one input from each

control line• Possibly NOTted

• There is a single OR that produces the result from the ANDs


Multiplexer Picture• This has two input lines, one

control line and one output– The inputs are the dangling inputs to

ANDs


Multiplexer example: telephones

• In the old days there was one pair of wires between each house and the telephone office– A party line had one pair of wires between a

common wire for all the phones and office– The phone had a switch to ring only for right

address

• This was an easy way to implement things

• Some time ago the Telco determined that they could save money by reducing copper wires in favor of more expensive switching equipment


Multiplexed lines• Each neighborhood with say 16 houses

has a wire into a multiplexer• Each wire is sampled 3000-5000 times

per second• That value is then transmitted down the

single line• Each line is then rotated through at the

same number of times a second• At the other end of the single wire only

those lines being used are routed


Decoders

• Select one line of many• Input is an N bit number• Output is 2n lines

– All of these except one are zero

• Example: Memory is also an example of this where sixteen address bits select 64K bits

• Very similar to a multiplexer except there is no data lines and no OR


Decoder Picture


Comparators

• Compare a group of bits for equal• Compare them with XORs gives

not equal• Then NOR or OR them together


Programmable Logic Arrays

• A group of many ANDs and many ORs with some inputs and outputs

• There are numerous connectors that determine that are set to determine the actual logical function implemented

• May be field programmed or mask programmed

• Nice way to prototype a digital network


Arithmetic

• In order to do arithmetic we need several things

• Shift register• Half Adder• Full Adder• Some control circuitry


Shifts• Useful device that takes a word and

shifts it left or right• A left shift amounts to multiplication

by 2• A right shift amounts to integer

division by 2• The bits that are shifted out are lost• Bits shifted in are usually zeros• A similar device rotates

– Output becomes input


Shift Register• Consider a four bit word and we will

shift one bit to right or left– Need four data bits in– Need a control bit in

• Each bit goes to a pair of ANDs which is controlled by the control bit

• Alternate pairs are ORed together• A rotate is a shift where the bit shifted

out is shifted back in the top to supply the fill bit

• A barrel shifter allows either direction shifts any number of bits


Shift Picture


The Add is the most interesting

• The two pieces to consider are a half-adder and a full-adder for one bit– We cascade them together

• First the half adder– This takes in two input bits and

produces two output bits:• The sum• The carry bit


Half Adder Truth Table

Inputs Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

• How do we implement this?• Does the truth table suggest a

solution?


Implementation

• How do we implement this?• The Carry is clearly an AND• The Sum is less clearly an XOR• So we have accomplished the

summing of two bits and producing the two bit output


Half Adder

A

B Sum

Carry

AND

XOR


The full adder

• The difference between the full adder and the half adder– The half adder produces a carry bit,

but does not use it

• The full adder really needs to have three input bits – Two data bits and a carry

• The truth table for this is below


Full Adder Truth TableInputs Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

• Does this suggest a solution?


Full Adder Implementation

• This is not as easy to see as the half adder, but lets decompose– Divide the table in two based on the

first bit– Consider the first bit as the carry from

the prior bit– Use the second and third bit as input

to a half adder– Then XOR that output with the carry

bit


More on Full Adder– The reason we call it a half adder, is

that is takes two to make a full• The first XORs the two bits• The second the output of the first and the

input carry bit

– To compute the carry you OR the outputs of the two half adders

– There is a diagram of these in Tanenbaum 136-137


Full Adder Picture

A In

B In

CarryIn

Half Adder

Half AdderSum

Carry

Sum Out

CarryOut

Sum

Carry


Notes on Full Adder

• The previous diagram showed a one bit full adder

• N of these will be cascaded into an N bit adder

• The adds will be done in parallel• The carrys will cause the main

delays– As the carry propagates down the line


A Four Bit Adder

Carryin

A

BSumout

A

BSumout

A

BSumout

A

BSumout

Carryout


Arithmetic Logic Unit

• Shown on p 138 of Tanenbaum• Like a full adder a bit slice that is

cascaded• It has inputs and outputs • Output

– Sum (or result) bit– Carry


Inputs• A bit and B bit

– A also has an inverse• Enable A and B• Carry• Four function select bits

– AND– OR– SUM– NOT B


Outward description

• This is just one bit of an ALU• For a larger one you must gang

them together• The carry out becomes the carry in

of the next• The function bits are the same all

the way through


Picture


Internal blocks• Full adder• Logical unit which is three separate sets

of gates:– AND– OR– NOT B

• Input decoder that select one of the other logical units

• There are four ANDs selected by the decoder that multiplex the output into a final OR


What are the operations that this ALU can handle?

• A AND B• NOT A AND B• A OR B• NOT A OR B• NOT B• A+B• B-A

– Set the carry in to 1– Use NOT A– Specify sum


Picture Again


Clocking

• Most of our logic is clocked• A clock produces a square wave of

excellent regularity• Four phases

– Rising edge– High period– Falling edge– Low period


Clock Notes• A secondary clock is the clock

circuit delayed a fraction of the clock cycle

• Usually clocks are symmetric but can be made asymmetric by ANDing original with delayed clock

• Any of the four phases can be used to make something happen

• Usually the change in state occurs in rising/falling state


Memory

• How do we make memory• Start with latches• Latches

– 1 bit memory

• SR Latch– Two input values:– S stands for setting– R stands for resetting (clearing)


SR Latch


Clocked SR Latch

• Only changes when clock allows it


Flip flop• Latch is level triggered, it only

changes during the high part of the clock

• Flip flop is edge triggered, it may only change on the rising or falling edge


Registers• A register stores values in a CPU

– Special or general purpose

• A register is a group of flip flops ganged together in a single package with controls tied together

• Registers need to be fast and this type of logic may be made as fast as the CPU circuitry

• Random Access Memory is usually slower– Decoders add delays, among other things


Static RAM

• Static RAM usually uses a clocked flip flop configuration with about six transistors– This can be made fast but it is also

relatively expensive

• Dynamic RAM uses a capacitor and a transistor– Usually much smaller, so higher

capacity per package


Dynamic RAM• It is usually slower than Static RAM• The capacitor leaks over time

– It must be refreshed periodically– This refreshing must be done be external

circuitry

• Could be part of the CPU or part of the board– Most recent CPUs automatically refresh

• Hence the highest capacity RAMs are always dynamic


Interesting dichotomy

• Static RAM is often used in cache because it is very fast

• Dynamic RAM is usually used in main memory because it is slow, but inexpensive

• However, cache changes often enough you would not need to refresh and memory is so large that refreshing can be a problem


A Few RAM flavors• Fast Page Mode

– Matrix of bits– Asynchonous– Ask for the data and it will be delivered

ASAP– Not clocked on address and data lines

• Extended Data Output– Pipelining increases bandwidth– There is also some caching at the chip level– Also asynchronous

• Synchronous DRAM– Hybrid of static and dynamic– Originally used in caches– Often used in the main memories of the

high end machines


ROM

• Read Only Memory• Non volatile, maybe changeable• Mask programmed at the factory• Lots of possibilities

– PROM– EPROM– EEPROM– Flash


Changeable ROM• PROM

– Programmable ROM– Connecting fuses– Put a high voltage on them and they

blow– Hence field programmable, but just

once

• EPROM– Erasable by UV light– Usually removed and then erased and

programmed


More Changeable ROM

• EEPROM– Electrically Erasable Programmable

ROM– Erased by processor control at the

byte level– Can be reprogrammed in the circuit

that it works in

• Flash memory– Erasable by electronics but at the

block level


Data transformations

• We have two kinds of data transformations– Primitive– Composite

• The primitive ones can be implemented directly in terms of gates

• The Composite ones will need several primitives in order to accomplish


The primitives:• AND• OR• NOT• XOR• Add• Shift• Rotate• Complement or negation• These we have already seen


The composites are more complicated:

• Subtraction• Comparison• Multiplication• Division• Conditional jump or branch• Copy is just memory fetch and

store somewhere else under a counter


Subtraction • Subtraction is the addition of a

complemented argument– Complement, then add

• Most arithmetic operations also set flags or condition codes

• These record the result of the last operation:

– negative– zero– positive– overflow


Comparison

• Comparison is a funny form of subtraction– Negative means a<b– Zero means a=b– Positive means a>b

• In that regard any arithmetic instruction is a comparison as far as conditional branches are considered


Jump or branch

• Load the Program Counter with a new address

• Conditional jump or branch requires a mask in the instruction

• The mask determines which flags must be set to enable branch

• A branch not taken is a no-operation (NOOP or NOP)


Multiplication and Division

• Multiplication is a sequence of right shifts and adds– Multiplication gives a double length

result

• Divide is a series of shifts and subtracts also

• Many of the early machines such as 8080 had no multiply or divide


Algorithm• Make both numbers positive

– Sign of the result is XOR of original signs

• Put one number in double length register– Zero out top half– Call it A

• Place other in private register– Call it B

• Then start the following loop


Multiplication Algorithm II

• For the number of bits in B do the following:– If low order bit of A is 1

• Add B to higher order half of A

– Shift A right one bit

• Result ends in A• When done make negative if

needed


Multiplication example• This presentation is based on how it is

done on IBM 360, except I will use two four bit registers instead of two 32 bit registers

• Lets try to multiply 5 times 6:– = 0101, 6 = 0110

• The 6 is put in single length, non-addressable register

• The 5 is put in the low order register of a register pair with the upper half cleared


Multiplication

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Recall long multiplicationMultiply one digit by one digitProduct is shifted by place valueSum the resultsThe multiplication algorithm does this sum and shifting


The Start

0110B00000101A

0110B01100101A

Step 1a: Bit is 1 - Add

0110B00110010A

Step 1b: Shift


Step 2

0110B00110010A

0110B00110010A

Step 2a: Bit is 0 – No Add

0110B00011001A

Step 1b: Shift


Step 3

0110B00011001A

0110B01111001A

Step 2a: Bit is 1 – Add

0110B00111100A

Step 1b: Shift


Step 4

0110B00111100A

0110B00111100A

Step 2a: Bit is 0 – No Add

0110B00011110A

Step 1b: Shift


Results• Result is 00011110

– 30 = 16+8+4+2

• Having the results in a double register enables the algorithm with nice effect– The product has the sum of the significant

digits of the operands– No possibility of overflow

• Make both items positive for multiplication– The resulting sign is the XOR or the two

incoming signs


IBM 360 was exciting

• You had to use an even odd pair of registers

• Yet you load one operand into the odd register of the pair– L 5,OPERAND1– M 4,OP2– ST 5,RESULTS– M 3,IN is a specification error


Division• How badly do you want to know

integer division?• The process was sort of the reverse• The exception is that you started

with a even odd pair• The remainder ended in the even

register• The quotient ended in the odd

register• With this example, you can see that

most other instructions can be built up from simpler operations as well


Faster Multiplication

• The apparent way to speed up multiplication is using lookup table

• Recall the use of a fact table in multiplication

• Use two digits to lookup a value in a fact table

• Sum the assembled digits


Lookup Multiplication

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No real multiplicationLookup digitsDo the sum

0 1 2 3 4 …

0 0 0 0 0 0 …1 0 1 2 3 4 …

2 0 2 4 6 8 …3 0 3 6 9 12 ……


Faster Multiplication• Divide the numbers into N bit

chunks• For each chunk look up the answer• Assemble the word sums that will

contain the answers• Do the sums• The larger the lookup table the

faster the process• The Pentium division bug was a

table error

copyright © 2005-2007 curt hill digital logic circuits electronics for boolean algebra

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