copyright © 2002 synopsys, inc. and intel corporation and their licensors. all rights reserved. 1...

1 Copyright © 2002 Synopsys, Inc. and Intel Corporation and their licensors. All rights reserved.

IntelIntel® Microelectronics Services Microelectronics Services

January 2002January 2002

www.Intel.com/design/ASICswww.Intel.com/design/ASICs

VDSM Issues and Design MethodologyVDSM Issues and Design Methodology

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Intel, the Intel logo, and [other trademarks] or registered trademarks of the Intel Corporation and its subsidiaries in the United States and in other countries. *Other names and brands may be claimed as the property of others.

Intel® Microelectronics Services

Copyright © 2002 Synopsys, Inc. and Intel Corporation and their licensors. All rights reserved.

What’s Ahead for TechnologyWhat’s Ahead for Technology

Morning Summary Morning Summary

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Key Parameters of ScalingKey Parameters of Scaling

ProcessProcess

.18u to .13u to 90n….18u to .13u to 90n…

Quality / ReliabilityQuality / Reliability

DPM, FIT, SER, DPM, FIT, SER,

Hot Carrier EffectHot Carrier Effect

PerformancePerformance

300MHz to multi-GHz…300MHz to multi-GHz…

ComplexityComplexity

2M to 5M to 10M gates…2M to 5M to 10M gates…

PowerPower

Active, LeakageActive, Leakage

DensityDensity

Metal layer tradeoff, library Metal layer tradeoff, library selection, optimizationselection, optimization

Major inflections in each create Major inflections in each create significant design challengessignificant design challenges

ProductivityProductivity

Gates/designer-day, Gates/designer-day,

Design reuseDesign reuse

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Dis-aggregation of Electronic Dis-aggregation of Electronic Product DevelopmentProduct Development

Distinct Core

Distinct Core

Competencies

Competencies

Systems Design

SoftwareDevelopment

ChipArchitecture,Specification

Logic Design & Verification,

Integration

PhysicalDesign &

Validation

Manufacturing,Assembly, &

Test

Proto, Debug,FA, QA

What’s the Best Use of Internal and External Resources?

PackageDesign

Volume Prod/Yield Mgmt

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Escalating Development Escalating Development Costs and TimeCosts and Time

Source: International Business Strategies, 2002

Sample (Actual) VDSM ProjectsSample (Actual) VDSM Projects

Average: $10M+, 300+ Staff-months !Average: $10M+, 300+ Staff-months !

Application Graphics Wireless Networking Networking Wireless

Geometry 0.13µ 0.13µ 0.13µ 0.13µ 0.13µ

Transistors 30M 12M 12M 24M 12M

Cost $10.7M $9.0M $5.7M $10.9M $16.3M

Staff-months 346 326 161 333 483

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Meet New Friends: NBTI…Meet New Friends: NBTI…

Transistor Transistor performance degrades performance degrades as a function of time, as a function of time, temperature, and temperature, and voltagevoltage

Unpredictable effect Unpredictable effect on transistors - vary on transistors - vary by design parametersby design parameters

NBTI may not NBTI may not manifest itself in first manifest itself in first silicon, but during silicon, but during production useproduction use

EE Times, 4/15/2002

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Success May Be FleetingSuccess May Be Fleeting

Probability of Success

Source: International Business Strategies, 2002

0

10

20

30

40

50

60

70

80

90

100

0.25 0.18 0.15 0.13 0.10 µm(estimated)

Operates As Expected

Full Mask Re-spin

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Re-spins are EXPENSIVERe-spins are EXPENSIVE

0

2,000

4,000

6,000

8,000

10,000Costs ($K)

Proto & Validation

Support SW

Physical Design

Verification

Design Planning

IP Dev and Qual

Spec

Plus a) lost revenue, b) opportunity costsPlus a) lost revenue, b) opportunity costsSource: International Business Strategies, 2002

$10.7$10.7MM

$4.7$4.7MM

Original Re-spin

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Scaling Challenge EraScaling Challenge Era

Increasing Design ComplexityIncreasing Design ComplexityEach GenerationEach Generation

1998

0.13

0.18

0.25

0.35

Interconnect RC

Signal Integrity

Power Integrity

In-die Variation

SER on Static

0. 5 0. 7

Inflection Point

1999 2000 2001 2002

Leakage Power

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DRC/LVS ruledecks - are they

consistent ?

Are business termsacceptable ?

What about support ?

Effort to reuseinternal IP ?

Does it have allthe views I need?

I’ve got IPfrom multiple sources,will it integrate?

Is the IP available in thefab/process that I need?

Does the IP come with verification suites I can reuse?

IP Decisions

Will the IP meettiming?

IP Creation and IntegrationIP Creation and IntegrationChallengesChallenges

All IP is not created equal !All IP is not created equal !

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Hierarchical Design Method UsedHierarchical Design Method Used

SpecTop-Level

Constraints

Pre-RTLFloor planning

BlockConstraints

RTL

Pin FileLibraries

CellsRule Decks

• I/O Placement• Topology• Partitioning• Block location• Block pin location• Obstructions• Refinement

Floor planning

• Power Analysis• Power Bus/Grid• Clock Pre-routes• Other Pre-routes

Power Planning &Pre-Routing

• RTL to Gates

Synthesis

• To Placed Gates• Connectivity• Congestion• Timing Driven• Power and Clocks• Pre-Routes• Fillers/Spares• Scan Re-order

Physical Synthesis & Placement

• Clocking Topology• Skew mngt• Line delay ctrl• Fan-out ctrl Clock-Tree

Synthesis

• Critical Nets• Global, Detail• ECO• Antennae Fixing

Routing

• Extraction• Static & Formal• Without Crosstalk• With Crosstalk

Static Analysis

• ERC, DRC, LVS• Metal Fills/Slots• Re-visit Timing• GDSII Finishing

Physical Verification

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What’s AheadWhat’s Ahead

High SpeedHigh SpeedHigh SpeedHigh Speed

PowerPowerPowerPower

ReliabilityReliabilityReliabilityReliability

Device ScalingDevice ScalingDevice ScalingDevice Scaling

High SpeedHigh Speed

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Technology ConvergenceTechnology Convergence

19961996 2002200220002000199819980.010.01

0.10.1

11

1010

OCOCOCOC----3333

OCOCOCOC----12121212

OCOCOCOC----48484848

Ethernet (LAN)Ethernet (LAN)Ethernet (LAN)Ethernet (LAN)

FastFastFastFastEthernet( LAN)Ethernet( LAN)Ethernet( LAN)Ethernet( LAN)

GigabitGigabitGigabitGigabitEthernet (LAN)Ethernet (LAN)Ethernet (LAN)Ethernet (LAN)

Storage Area Networks (SAN)Storage Area Networks (SAN)Storage Area Networks (SAN)Storage Area Networks (SAN)FiberFiberFiberFiber

ChannelChannelChannelChannel

Storage (SAN)Storage (SAN)

Sonet (WAN)Sonet (WAN)

Ethernet (LAN)Ethernet (LAN)

1010GEGE1010GEGE

OCOCOCOC----192192192192

SynchronousSynchronousSynchronousSynchronousOpticalOpticalOpticalOptical

NetworksNetworksNetworksNetworks((WAN)WAN)((WAN)WAN)

Local Area NetworksLocal Area NetworksLocal Area NetworksLocal Area Networks((LAN)LAN)((LAN)LAN)

Gig

abits

per

sec

ond

Gig

abits

per

sec

ond

1010GG----FCFC1010GG FCFC

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High Speed I/O TrendsHigh Speed I/O Trends Single-ended scheme to differential Single-ended scheme to differential

Parallel bus to serial link Parallel bus to serial link

Voltage drivers to current mode driversVoltage drivers to current mode drivers

Simple signaling to timing & voltage modulationsSimple signaling to timing & voltage modulations

Multi-drop interfaces to point-to-point linksMulti-drop interfaces to point-to-point links

Source-synchronous to embedded clockingSource-synchronous to embedded clocking

Wire bond to FCBGAWire bond to FCBGA

Fundamental change in designing high speed I/OFundamental change in designing high speed I/O

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On-die & On-package Wave EquationsOn-die & On-package Wave Equations What is moving inside silicon, package and board?What is moving inside silicon, package and board?

• Electrons and electromagnetic field ?

Diffusion (RC) Equation Diffusion (RC) Equation • On-Chip, RC >> LC

Dispersion (LC) EquationDispersion (LC) Equation• On package and board, LC >> RC

2222 /),(/),(/),( ttxVLCttxVRCxtxV

ttxVRCxtxV /),(/),( 22

2222 /),(/),( ttxVLCxtxV

),( txV

On-die & on-package are On-die & on-package are mathematically & physically mathematically & physically

very different. very different.

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Diffusion and Dispersion WaveformDiffusion and Dispersion Waveform DiffusionDiffusion

• Both delay and rise/fall time are linear proportional to RC, and the Both delay and rise/fall time are linear proportional to RC, and the distance by Xdistance by X22

Delay ~ 0.4 XDelay ~ 0.4 X2 2 RC, and Rise/Fall ~ XRC, and Rise/Fall ~ X22 RC RC

DispersionDispersion• Both delay and rise/fall time are linear proportional to and XBoth delay and rise/fall time are linear proportional to and X

Delay ~ X, and amplitude ~ 1/XDelay ~ X, and amplitude ~ 1/X

DiffusionDiffusion DispersionDispersion

I/O design is fundamentally different from core designI/O design is fundamentally different from core design

2ns0.8ns 4m

20m

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Cross-talkCross-talk Inductive & capacitive Inductive & capacitive

couplingcoupling

Near and far end cross-Near and far end cross-talk noisetalk noise

Amplitude and durationAmplitude and duration• Prop. to Lm and CmProp. to Lm and Cm• Prop. to signal swingProp. to signal swing• Related to Related to

terminationterminationtransmission line transmission line

lengthlengthSlew rateSlew rate

Impact on timing and Impact on timing and noise marginnoise margin

V

tr

Near end Far end

0.5*(tr+X*sqrt(LC)) tr

Scan – more cases

vin

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Inter-Symbol Interference Inter-Symbol Interference ISIISI

• A value or symbol on a channel can corrupt another traveling on the same channel at a later time.

• This ISI occurs as a result of energy from one symbol stored in the channel sums later with a unrelated symbol.

Example:Example:• In the LVCMOS bus, the ISI

is on the order of 250ps

Clock pattern

Single pulse

time

V

Ideal pattern Realistic pattern

Scan - Data an clock pattern

RandomData Pattern

Clock Pattern

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Signal Return DiscontinuitySignal Return Discontinuity

Impedance mis-matchImpedance mis-match• Along signal return pathAlong signal return path

For example, a GAPFor example, a GAP• If the gap is comparable If the gap is comparable

to the edge rateto the edge rate

• The effect will be similar The effect will be similar to that of the serial to that of the serial inductanceinductance

EffectEffect• Inductive spike at driverInductive spike at driver

• Ledge on the signalLedge on the signal

• Significant coupling Significant coupling onto next lineonto next line

Scan -

Signal 1 Signal 2

Signal 1 Signal 2

Reference plan

Reference plane

Return current

GAP

D0.1”

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High Frequency Loss High Frequency Loss High freq. skin lossHigh freq. skin loss

• The changing current The changing current distribution due to change of distribution due to change of freq. results a increase of freq. results a increase of resistanceresistance

R ~ k * sqrt R ~ k * sqrt ( freq )( freq )

High freq. dielectric lossHigh freq. dielectric loss• Due to electric polarization, Due to electric polarization,

resulted change of dielectric resulted change of dielectric constant, usually over GHzconstant, usually over GHz

• Measured by loss tangentMeasured by loss tangent

Return lossReturn loss• Reflection due to Zo mis-matchReflection due to Zo mis-match

• Seen at 3GI/O SPECSeen at 3GI/O SPEC

Scan picture

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Transmitter EqualizationTransmitter Equalization

Freq. dependent Freq. dependent attenuationattenuation

• The “lone” pulseThe “lone” pulse

Use high-pass FIR Use high-pass FIR filter filter

• Transfer function Transfer function that approximates that approximates the inverse of Txthe inverse of Tx

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Signal Schemes, “Direction”Signal Schemes, “Direction”

Uni-directionalUni-directional• Sending signal one directionalSending signal one directional

• Receive signal at end of transmissionReceive signal at end of transmission

• Such as LVDS, LVCMOS on EagleSuch as LVDS, LVCMOS on Eagle

Bi-directional Bi-directional • Sending signal sometime one way, Sending signal sometime one way,

sometime on the opposite way, but not the sometime on the opposite way, but not the same timesame time

• Such as DDR memory bus for OcelotSuch as DDR memory bus for Ocelot

Simultaneous bi-directionalSimultaneous bi-directional• Sending signal both way “Simultaneously” Sending signal both way “Simultaneously”

• Save pins or higher BW/pinSave pins or higher BW/pin

• Such as scalability port on Intel McKinley Such as scalability port on Intel McKinley platformplatform

Uni-directional Eye

Simultaneous bi-directional Eye

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Signaling with Current and VoltageSignaling with Current and Voltage

Signaling with voltageSignaling with voltage• Driver transistor in linear Driver transistor in linear

rangerange

• Bigger mis-match with line Bigger mis-match with line Zo (~15 ohms vs. 50 Zo (~15 ohms vs. 50 ohms)ohms)

Signaling with currentSignaling with current• Driver in saturationDriver in saturation

• Driver side termination to Driver side termination to match better with line Zomatch better with line Zo

• Isolate the ground noiseIsolate the ground noise

tr

tr

50 ohms~ 15 ohms

>300ohms 50 ohms

50 ohms

50 ohms50 ohms

Signaling with voltage

Signaling with current

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Sample IME I/OsSample IME I/Os

LVDS LVCMOS SSTL2 PCI SPI-4 PECL HSTL

Link Speed (Mb/s) 1200 125 300 66 1680 840 200

Driving Scheme differentialsingle-ended

single-ended

single-ended differential differential

single-ended

Driver current voltage voltage voltage current current voltage

Driver Equalization no no no no yes no no

Driver Rise/Fall (ns) 1 2 1 3 1 3 3

Driver Swing (mv) 300 CMOS CMOS CMOS 300 CMOS

Receiverlinear

amplifier cmos cmos cmoslinear

amplifierlinear

amplifier cmos

Termination(W)50 , on-die,

drv&rev , on-die,

drv&rev no no50 , on-die,

drv&rev50 , on-die,

drv&rev no

Interconnect/PCB < 5" < 5" ~10" ~10" < 7" ~10" ~10"

Package FCBGA FCBGA FCBGA FCBGA FCBGA FCBGA FCBGA

I/O voltage (V) 3.3, 1.8 2.5, 1.8 2.5, 1.8 3.3, 1.8 3.3, 1.8 (-5.1, 1.8) 3.3, 1.8

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Why Go Smaller?Why Go Smaller?

Source: Mark Bohr Intel 2001 IVC/AVS

70 nm

Si3N4CoSi2

130nm

65nm

R. Chau IEDM 2000

LG = 30nm

Improved densityImproved density

– 0.7x feature size per generation0.7x feature size per generation

– Pack ~2x more transistors per Pack ~2x more transistors per areaarea

Faster switching speedFaster switching speed

– 0.7x gate delay per generation0.7x gate delay per generation

– >1.4x frequency increase>1.4x frequency increase

Lower switching powerLower switching power

– Reduced supply voltage (VReduced supply voltage (VDDDD))

– Reduced device areaReduced device area

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Process Technology ChallengeProcess Technology ChallengeMinimum Feature Size TrendMinimum Feature Size Trend

0.01

0.1

1

10

1970 1980 1990 2000 2010 2020

Year

Micron

3.0um

180nm0.25um

0.35um0.5um

0.8um1.0um

1.5um2.0um

130nm

65nm90nm

LGATE

LGATELGATE

Source: Mark Bohr Intel 2001 IVC/AVS

Sub-100nm is closer than you thinkSub-100nm is closer than you think

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Shrinking Transistor ChallengeShrinking Transistor ChallengePower Leakages IncreasePower Leakages Increase

IGATE

SourceDrain

GateGate Oxide Leakage (IGate Oxide Leakage (IGATEGATE))

Thinner oxide for performance Thinner oxide for performance

130 nm generation down to 130 nm generation down to 1.5 nm (~6 atoms)1.5 nm (~6 atoms)

Tunneling current becoming Tunneling current becoming significantsignificant

IOFF

SourceDrain

Gate Sub-threshold Leakage (ISub-threshold Leakage (IOFFOFF))

Reduce VReduce VDDDD for power for power

Reduce VReduce VTT for performance for performance

Lower VLower VTT increases I increases IOFFOFF

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Shrinking Transistor ChallengeShrinking Transistor ChallengePower Leakages IncreasePower Leakages Increase

Sub-threshold Leakage (ISub-threshold Leakage (IOFFOFF))

• Reduce VReduce VDDDD for power for power

• Reduce VReduce VTT for performance for performance

• Lower VLower VTT increases I increases IOFFOFF

Gate Oxide Leakage (IGate Oxide Leakage (IGATEGATE))– Thinner oxide for performance Thinner oxide for performance – 130 nm generation down to 1.5 130 nm generation down to 1.5

nm (~6 atoms)nm (~6 atoms)– Tunneling current becoming Tunneling current becoming

significantsignificant

Becoming a major design considerationBecoming a major design consideration

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

65 90 130 180 250

Technology Generation (nm)

Leakage (A/um)

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

65 90 130 180 250

Technology Generation (nm)

Leakage (A/um)

IOFF

IGATE

High-k

S. Borkhar, ISPLED ‘00

0100nm 15mm die 0.7V

6% 9% 14%19%

26%33%

41%

49%

56%

-

10

20

30

40

50

60

70

30 40 50 60 70 80 90 100

110

Temp (C)

Po

wer

(W

atts

)

LeakageActive

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Reduce equivalent oxide thickness by eliminating poly-Reduce equivalent oxide thickness by eliminating poly-gate depletiongate depletion

Shrinking Transistor ChallengeShrinking Transistor Challenge

Option 1: Metal Gate TransistorsOption 1: Metal Gate Transistors

N+

P-well

N+ N+

P+

N-well

P+ P+

M1

P-well

N+ N+

M2

N-well

P+ P+

NMOS PMOS

PolySi Gate

Metal Gate

• Eliminate poly depletionEliminate poly depletion

• Optimal performance Optimal performance requires FMS to match requires FMS to match N+ and P+ siliconN+ and P+ silicon

• Process flow is complexProcess flow is complex

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Increase drive current per unit areaIncrease drive current per unit area


Option 2: Double Gate Transistors Option 2: Double Gate Transistors

S D

G

S D

Top

Bottom

• ~2~2x drive currentx drive current

• ~2x gate capacitance~2x gate capacitance

• Better short channel Better short channel characteristicscharacteristics

• Complex processComplex process

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Reduce equivalent oxide thickness without increasing Reduce equivalent oxide thickness without increasing leakageleakage


Option 3: High-k Gate DialecticsOption 3: High-k Gate Dialectics

S

G

D

S DG

S G D

source

top gate

bottom gate drain

100 nm

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Shrinking Transistor ChallengeShrinking Transistor ChallengeOption 4: Sleep TransistorsOption 4: Sleep Transistors

Leakage control techniques are very effectiveLeakage control techniques are very effective 100X S/D leakage improvement100X S/D leakage improvement ETA second half of decadeETA second half of decade

sleep sleep transistortransistor

Virtual VssVirtual Vss

Virtual VccVirtual Vcc

sleep sleep transistortransistor

Circuit blockCircuit block

R. Krishnamurthy, Intel DAC 2002

Leakage reduction for 5% delay penaltyLeakage reduction for 5% delay penalty(32-bit KS adder)(32-bit KS adder)

Boosted

reduction

bounce

Sleep

Sleep-TR size

Virtual supply

powerLeakage

60 mV 59 mV 58 mV 50 mV

1450X 3130X 11.5X 12X

5.1% 2.3% 3.2% 11.5%

Stack-forcingMTCMOS

Boosted Sleep

Non-

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The 10,000 Foot ViewThe 10,000 Foot View

100100nm introduces a whole new nm introduces a whole new world of issuesworld of issues

• The days of simple device scaling are over

• Process technology will continue to drive to smaller geometries

New approaches, structures, design New approaches, structures, design methods and flows are needed to methods and flows are needed to meet scaling challengesmeet scaling challenges

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Power ScalingPower Scaling

Power density is increasing Power density is increasing

Surpassed hot-plate power Surpassed hot-plate power density in 0.6density in 0.6

Junction Temp <= 100 C is Junction Temp <= 100 C is recommendedrecommended

– Performance (higher freq)Performance (higher freq)

– Exponential growth in Exponential growth in leakageleakage

– Exponential impact on Exponential impact on reliabilityreliability

0

10

20

30

40

50

60

70

Wat

ts/c

m2

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Power ScalingPower Scaling

Wat

ts

30%

Vd

d

C d

ensi

ty

Are

a

Fre

qu

ency

Lea

kag

e P

ow

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0.01

0.10

1.00

Act

ive

Cap

De

ns

ity

(nf/

mm

2)

Active capacitance densityActive capacitance density

Active capacitance grows 30-35% each technology generation

Area

CDensityCap

freqV

PowerCapActive

CC

2

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1

10

100

1,000

10,000

30 40 50 60 70 80 90 100 110

Temp (C)

Ioff

(n

a/

)

0.10m

0.13m

0.18m

0.25m

Reference:Mark Bohr, et alIEDM, 1996

Constant E scaling -> Vdd scales

Higher performance -> lower Vt

Lower Vt -> higher drain Leakage

Sub Threshold Leakage Trend

Leakage PowerLeakage Power

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Leakage Effect on PowerLeakage Effect on Power

Each GenerationConstant Die Size(2x transistors)~15mm die1.5X freq increase each generation

Wat

ts

0

25

50

75

100

Po

wer

Den

sity

(W

/cm

2)Lkg Pwr

Active Pwr

Power Density

Shekhar Borkar,

ISPD 04/10/00

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Shrinking Transistor ChallengeShrinking Transistor ChallengeOption 5: Dual VOption 5: Dual VTT design design

Logic path between latch boundaries

Delay

Nu

mb

er

of

pa

ths

Delay

Nu

mb

er

of

pa

ths

Delay

Nu

mb

er

of

pa

ths

Dual VDual VT T designdesign- High V- High VT T with nominal Iwith nominal Ioffoff (lower performance)(lower performance)

- Low V- Low VT T with ~10X higher lwith ~10X higher loffoff (higher (higher performance)performance)

Employing high VEmploying high VTT everywhere yields lower everywhere yields lowerperformance, and lower leakage (1X)performance, and lower leakage (1X)

Employing low VEmploying low VT T everywhere yields highereverywhere yields higherperformance, but higher leakage (10X)performance, but higher leakage (10X)

Selective usage of low and high VSelective usage of low and high Vtt yields yields higher performance, yet low leakage higher performance, yet low leakage between 1X, and <<10Xbetween 1X, and <<10X

High VT

Low VT

Dual VT

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Soft ErrorsSoft Errors

Wear OutWear Out

DegradationDegradation

44 Copyright © 2002 Synopsys, Inc. and Intel Corporation and their licensors. All rights reserved.

The Reliability and Quality The Reliability and Quality ChallengesChallenges

The bathtub curveThe bathtub curve

Common aging and random failure mechanismsCommon aging and random failure mechanisms

Hot-e transistor degradation due to hot electronsHot-e transistor degradation due to hot electrons

EM – electromigrationEM – electromigration

SH - self heatSH - self heat

Oxide wear out Oxide wear out

NBTI – Negative bias temperature instability (P-Channel)NBTI – Negative bias temperature instability (P-Channel)

SER - Single-event soft errorsSER - Single-event soft errors

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FailuresFailures Failure rate is defined as a function of operating life of a group Failure rate is defined as a function of operating life of a group

of parts or probability per unit time of a given part to fail.of parts or probability per unit time of a given part to fail.

Time

Failu

re R

ate

Infant Mortality

Event Related

(random)

Device Wear-out

DSM effects

Useful life (years)

The classical bath tub curve presents failure rate for ICs and DSM effects

Infant Mortality

• Show up early in life of products

• Mainly due to product defects

• Detected by Burn-in

Event Related

• Show up at various intervals in life

• Random nature

• Example – Signal/Power integrity, SER

• Can be reduce by construction design

Device Wear-out

• Aging mechanism dominate

• Can be pushed out by construction design

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Reliability and QualityReliability and Quality

Reliability is defined as “the probability of a device Reliability is defined as “the probability of a device performing its purpose for a period of time intended under performing its purpose for a period of time intended under the operation conditions.”the operation conditions.”

Quality is defined as the degree of conformance to Quality is defined as the degree of conformance to specification and/or workmanship. It does not include time specification and/or workmanship. It does not include time frame, but reliability doesframe, but reliability does

Reliability means reputation, revenue, and even success to Reliability means reputation, revenue, and even success to IME’s customers.IME’s customers.

Three keys for reliable and quality IC products areThree keys for reliable and quality IC products are• Construction design Construction design

• Reliable and consistent manufacture processes Reliable and consistent manufacture processes

• Burn-in and Bake Burn-in and Bake

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Wear OutWear Out



Wear OutWear Out


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Soft Error SusceptibilitySoft Error Susceptibility

1

10

Soft error susceptibility

Logic 1 Logic 0

Vinduced

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Junction Charge CollectionJunction Charge Collection

Ion Track +V Vss

n+ diffusion p- epi

p+ substrate

Electric Field

Recombination

Diffusion Collection

Funnel Collection

Junction Collection Potential Contour

Deformation

Electron-Hole Pairs

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Single Event EnvironmentsSingle Event Environments

Satellite and other spaceborne applicationsSatellite and other spaceborne applications• High-energy heavy ions (cosmic rays)High-energy heavy ions (cosmic rays)

Long range, large dE/dx, direct interactionLong range, large dE/dx, direct interaction

• High-energy protons (trapped and solar)High-energy protons (trapped and solar)Indirect interaction through recoil SiliconIndirect interaction through recoil Silicon

Terrestrial and high-altitude applicationsTerrestrial and high-altitude applications• Alpha particles (radioactive decay)Alpha particles (radioactive decay)

Short range, small dE/dx, direct interactionShort range, small dE/dx, direct interaction

• High energy neutrons (cosmic ray byproduct)High energy neutrons (cosmic ray byproduct)Indirect interaction through recoil SiliconIndirect interaction through recoil Silicon

• Low energy neutrons (thermal)Low energy neutrons (thermal)Indirect interaction via Boron nuclear reactionIndirect interaction via Boron nuclear reaction

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Single Event Upset (SEU)Single Event Upset (SEU)

Reversed biased junctions collect chargeReversed biased junctions collect charge• Static latchesStatic latches

• SRAMsSRAMs

Circuit feedback magnifies voltage transientsCircuit feedback magnifies voltage transients• Data state flips if voltage crosses switch pointData state flips if voltage crosses switch point

Critical charge for upset decreases as the square of Critical charge for upset decreases as the square of the technology feature sizethe technology feature size

Error rates are independent of clock frequencyError rates are independent of clock frequency

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Single Event Transient (SET)Single Event Transient (SET)

Reversed biased junctions collect chargeReversed biased junctions collect charge• Combinatorial logic circuitsCombinatorial logic circuits

Voltage transients propagate un-attenuatedVoltage transients propagate un-attenuated• Indistinguishable from normal signalsIndistinguishable from normal signals

• Incorrectly latched if arrive at a clock edgeIncorrectly latched if arrive at a clock edge

Critical width for un-attenuated propagation Critical width for un-attenuated propagation decreases as the square of the feature sizedecreases as the square of the feature size

Error rates now depend on clock frequencyError rates now depend on clock frequency• Static CMOS: Proportional to frequencyStatic CMOS: Proportional to frequency

• Dynamic CMOS: Decreases with frequencyDynamic CMOS: Decreases with frequency

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Many Types of SET Induced Many Types of SET Induced ErrorsErrors

Data input transientsData input transients

Clock line transientsClock line transients

Asynchronous control line transientsAsynchronous control line transients

Synchronous control line transientsSynchronous control line transients

CLOCK

Combinatorial Logic

OUTDATA

DFF

D Q

DFF

D Q

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Errors Due to Data SETsErrors Due to Data SETs

Clock

Data

Data

Data

Data

Setup Time Hold Time

Non-Latching SET

Earliest-Latching SET

Non-Latching SET

Latest-Latching SET

Window of Vulnerability

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Wear OutWear Out



Wear OutWear Out


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Oxide Wear-OutOxide Wear-Out

Oxide wearout is a time and voltage dependent oxide Oxide wearout is a time and voltage dependent oxide breakdownbreakdown

• Very little changes in transistor characteristics before failureVery little changes in transistor characteristics before failure

• Failure evolves from recoverable soft breakdown to non-Failure evolves from recoverable soft breakdown to non-recoverable hard breakdown recoverable hard breakdown

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Device Wearout/Life Time TrendDevice Wearout/Life Time Trend

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Wear OutWear Out



Wear OutWear Out


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Common Aging Failure Common Aging Failure MechanismsMechanisms

Hot Electron DegradationHot Electron Degradation

Negative Bias Temperature instability Negative Bias Temperature instability

Oxide wear-outOxide wear-out

ElectromigrationElectromigration

Self-HeatSelf-Heat

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Hot-E DegradationHot-E Degradation

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Hot-E DegradationHot-E Degradation

nn --SiOSiO22

nn --

nn ++nn ++

spacerspacer

TheThe nn -- region acts as a series resistor therefore the transistor’s Vds is region acts as a series resistor therefore the transistor’s Vds is reduced. This lightly doped region also reduces the electric field reduced. This lightly doped region also reduces the electric field across the pinch-off region. (Side effect - the transistor is slower!)across the pinch-off region. (Side effect - the transistor is slower!)

SourceSourceSiOSiO22

NMOS GateNMOS Gate

DrainDrain

Substrate hole currentSubstrate hole current

Trapped electronTrapped electron

e-h paire-h pairIdsIds

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Hot-e DegradationHot-e Degradation

How to reduce the hot-e degradation – partial How to reduce the hot-e degradation – partial listlist

• Decrease Cload (reduce fan out).Decrease Cload (reduce fan out).

• Speed up the input edge rate.Speed up the input edge rate.

• Avoid slowly varying output signals where possible.Avoid slowly varying output signals where possible.

• Avoid capacitive coupling above VCC.Avoid capacitive coupling above VCC.

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Negative Bias Temperature Negative Bias Temperature instabilityinstability

What is it?What is it?• The P Transistor performance (Idsat, Vt) degrades as a function of The P Transistor performance (Idsat, Vt) degrades as a function of

time, temperature, and voltagetime, temperature, and voltage

• The cause is not fully understood but is believed to be caused by The cause is not fully understood but is believed to be caused by dopant migration into the gate while the P-Channel is “off”dopant migration into the gate while the P-Channel is “off”

Are all transistors effected equally?Are all transistors effected equally?• No. It is a function of the design. No. It is a function of the design.

Activity (“On” devices degrade quicker than “off” devices)Activity (“On” devices degrade quicker than “off” devices)High voltage outputs degrade faster than internal devices High voltage outputs degrade faster than internal devices The temperature is not uniform across a die. “Hot spots” will The temperature is not uniform across a die. “Hot spots” will

degrade quicker (i.e. clock drivers).degrade quicker (i.e. clock drivers).Analog functions dependent upon Idsat, Vt relationshipsAnalog functions dependent upon Idsat, Vt relationships

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Designing for NBTIDesigning for NBTI

Use “end of life” simulation filesUse “end of life” simulation files• Suitable for digital circuits Suitable for digital circuits

• More area and higher power if applied indiscrimatelyMore area and higher power if applied indiscrimately

• First silicon can be misleading indication of success First silicon can be misleading indication of success The ASIC runs faster than expected and meets a The ASIC runs faster than expected and meets a

customer’s acceptance specs….. today…..customer’s acceptance specs….. today…..

AgeSimAgeSim• Intel uses a transistor age simulator to simulate transistor Intel uses a transistor age simulator to simulate transistor

behavior as it degrades over its entire life cycle (important for behavior as it degrades over its entire life cycle (important for analog functions)analog functions)

Intel uses a combination of AgeSim and EOL Intel uses a combination of AgeSim and EOL

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Testing for NBTITesting for NBTI

Burn In Burn In • Burn In accelerates NBTI quicklyBurn In accelerates NBTI quickly

• Burn in adds to the cost Burn in adds to the cost

• Need to assure that burn in patterns are complex enough to be Need to assure that burn in patterns are complex enough to be representative of actual activity representative of actual activity

Guardband tester parameters with the expected Guardband tester parameters with the expected degradationdegradation

Intel uses a combination of Burn In and Tester guard Intel uses a combination of Burn In and Tester guard bandingbanding

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Electromigration DamagesElectromigration Damages

ILD Crack

Interlayer metal voids

Voids

Hillock

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Electro Migration Failure MechanismElectro Migration Failure Mechanism

Electro Migration (EM) - migration of metal ions along the electrons flux in Electro Migration (EM) - migration of metal ions along the electrons flux in case of DC currents. Causes opens and shorts in metal segmentscase of DC currents. Causes opens and shorts in metal segments

Ion motion due to momentum transferIon motion due to momentum transfermostly lattice vacancies (few interstitial ions)mostly lattice vacancies (few interstitial ions)grain boundary is vacancy source/sinkgrain boundary is vacancy source/sink

• Vacancies drift against electron windVacancies drift against electron windaccumulate at cathode, deplete at anodeaccumulate at cathode, deplete at anode

• Pressure inverse to vacancy concentrationPressure inverse to vacancy concentrationlow density = high pressure (crack surrounding glass and subsequent low density = high pressure (crack surrounding glass and subsequent

metal short)metal short)high density = low pressure (coalesce into metal void and subsequent high density = low pressure (coalesce into metal void and subsequent

high resistance or open circuit)high resistance or open circuit)

• Electro-migration is exponentially enhanced at elevated temperatures ==> Electro-migration is exponentially enhanced at elevated temperatures ==> requires strict interconnect SH rulesrequires strict interconnect SH rules

e

I

migrated ions(short hazard)

void(open)

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EM Failure TypesEM Failure Types

(a)

(b)

(c)

(d)(a) Open in a line (void)

(b) Short between two lines (whisker)

(c) Short between lines on different layers (hillock)

(d) Open between line and via (via void)

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VIA Electro MigrationVIA Electro Migration

• Left - voids under a via, high resistance or open circuitLeft - voids under a via, high resistance or open circuit• Right - ILD crack, possible short circuit with adjacent wiresRight - ILD crack, possible short circuit with adjacent wires

I

Electron direction

Vcc

Vss I

Electron direction

Damage

Damage

eHigh Resistance

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EM Via Failure CalculationEM Via Failure Calculation

The AE (Activation Energy) changes the temperature The AE (Activation Energy) changes the temperature factor (TF).factor (TF).

Vias will use activation energy according to current Vias will use activation energy according to current direction:direction:

Current up Current up take AE of metal below. take AE of metal below.

Current dn Current dn take AE of metal above. take AE of metal above.

Temperature factor is computed per current Temperature factor is computed per current direction.direction.

Baseoject TTk

ae

eTF

11

PrActivation energy

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Self-HeatSelf-Heat

IBM CMOS 7S copper process, 0.16 m

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Self Heat (SH)Self Heat (SH)

SH is the rise in temperature due to the electron SH is the rise in temperature due to the electron movement within a conductor.movement within a conductor.

It is also known as Joule Heating, since it is related It is also known as Joule Heating, since it is related to the power that is dissipated onto the interconnect. to the power that is dissipated onto the interconnect.

SH is dependant on SH is dependant on bi-directionalbi-directional AC (Root Mean AC (Root Mean Squared) current, since Joule heating is a result of Squared) current, since Joule heating is a result of P=IP=I22R. R.

SH also has a Design Rule Current Density SH also has a Design Rule Current Density JJMAXMAX for for

each layer. A SH violation occurs when each layer. A SH violation occurs when J > JJ > JMAXMAX..

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Self Heating = More EMSelf Heating = More EM

Self HeatingSelf Heating More EMMore EM..

Since SH increases temperature, self-heating on a Since SH increases temperature, self-heating on a metal line can aggravate EM effects.metal line can aggravate EM effects.

SH on a line can also increase EM effects on SH on a line can also increase EM effects on neighboring lines.neighboring lines.

Because self-heating contributes to electro-Because self-heating contributes to electro-migration, failures are typically labeled as migration, failures are typically labeled as EMEM, not , not SH.SH.

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