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FUJITSU SEMICONDUCTORCONTROLLER MANUAL

FR6032-BIT MICROCONTROLLER

MB91319 SeriesHARDWARE MANUAL

CM71-10126-2E

FR6032-BIT MICROCONTROLLER

MB91319 SeriesHARDWARE MANUAL

FUJITSU LIMITED

PREFACE

Objectives and Intended Reader

The MB91319 is a standard single-chip microcontroller that has a 32-bit high-performance RISCCPU as well as built-in I/O resources for embedded controller that requires high-performanceand high-speed CPU processing.

The MB91319 is most suitable for embedded applications, such as TV and PDP controllers, thatrequire a high level of CPU processing power.

The MB91319 is one of the FR60 series of microcontrollers, which are based on the FR30/40family of CPUs. It has enhanced bus access and is optimized for high-speed use.

This manual is intended for engineers who will develop products using the MB91319 anddescribes the functions and operations of the MB91319. Read this manual thoroughly.

For more information on instructions, see the "Instructions Manual".

Trademarks

FR, which is an abbreviation of FUJITSU RISC controller, is a product of Fujitsu Limited.

REALOS (Real-time Operating System) is a trademark of FUJITSU LIMITED.

The names of other systems and products appearing in this manual are the trademarks of theirrespective companies or organizations.

License

Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to

use, these components in an I2C system provided that the system conforms to the I2C StandardSpecification as defined by Philips.

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Organization of This Manual

This manual consists of the following 20 chapters and an appendix.

CHAPTER 1 "OVERVIEW"

This chapter provides basic information required to understand the MB91319 series, andcovers features, a block diagram, and functions.

CHAPTER 2 "HANDLING THE DEVICE"

This chapter provides precautions on handling the MB91319 series.

CHAPTER 3 "CPU AND CONTROL UNITS"

This chapter provides basic information required to understand the functions of the MB91319series. It covers architecture, specifications, and instructions.

CHAPTER 4 "I/O PORT"

This chapter describes the I/O ports and the configuration and functions of registers.

CHAPTER 5 "16-BIT RELOAD TIMER"

This chapter describes the 16-bit reload timer, the configuration and functions of registers,and 16-bit reload timer operation.

CHAPTER 6 "PROGRAMMABLE PULSE GENERATOR (PPG) TIMER"

This chapter gives an outline of the PPG (Programmable Pulse Generator) timer andexplains the register configuration and functions and the timer operations.

CHAPTER 7 "MULTIFUNCTION TIMER"

This chapter gives an overview of the multifunction timer and explains the registerconfiguration and functions and the timer operation.

CHAPTER 8 "16-BIT PULSE WIDTH COUNTER"

This chapter gives an overview of the 16-bit pulse width counter and explains the registerconfiguration and functions and the counter operation.

CHAPTER 9 "INTERRUPT CONTROLLER"

This chapter describes the interrupt controller, the configuration and functions of registers,and interrupt controller operation. It also presents an example of using the hold requestcancellation request function.

CHAPTER 10 "EXTERNAL INTERRUPT AND NMI CONTROLLER"

This chapter describes the external interrupt and NMI controller, the configuration andfunctions of registers, and operation of the external interrupt and NMI controller.

CHAPTER 11 "REALOS-RELATED HARDWARE"

This chapter explains the delayed interrupt module and bit search module that are REALOS-related hardware. REALOS-related hardware is used by the real-time OS. When REALOS isused, the hardware cannot be used with the user program.

CHAPTER 12 "10-BIT A/D CONVERTER"

This chapter gives an overview of the 10-bit A/D converter, register configuration andfunctions, and 10-bit A/D converter operation.

CHAPTER 13 "U-TIMER"

This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER operation.

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CHAPTER 14 "UART"

This chapter describes the UART, the configuration and functions of registers, and UARToperation.

CHAPTER 15 "I2C INTERFACE"

This chapter describes the I2C interface, the configuration and functions of registers, and I2Cinterface operation.

CHAPTER 16 "DMA CONTROLLER (DMAC)"

This chapter describes the DMA controller (DMAC), the configuration and functions ofregisters, and DMAC operation.

CHAPTER 17 "USB FUNCTION"

This chapter gives an overview of the USB function, register configuration and functions,operation of the USB function, and supplementary notes on the USB function.

CHAPTER 18 "OSDC"

This chapter explains the features, block diagram, display function, control function, anddisplay control command of the on-screen display controller (OSDC).

CHAPTER 19 "FLASH MEMORY"

This chapter provides an outline of flash memory and explains its register configuration,register functions, and operations.

CHAPTER 20 "SERIAL PROGRAMMING CONNECTION"

The built-in FLASH product supports the serial onboard writing (Fujitsu standard) of the flashROM. The following explains its specification.

APPENDIX

This appendix consists of the following parts: the I/O map, interrupt vector, dot clockgeneration PLL, USB clock, external bus interface setting, and instruction lists. The appendixcontains detailed information that could not be included in the main text and referencematerial for programming.

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©2006 FUJITSU LIMITED Printed in Japan

• The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document arepresented solely for the purpose of reference to show examples of operations and uses of FUJITSUsemiconductor device; FUJITSU does not warrant proper operation of the device with respect to use basedon such information. When you develop equipment incorporating the device based on such information, youmust assume any responsibility arising out of such use of the information. FUJITSU assumes no liability forany damages whatsoever arising out of the use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not beconstrued as license of the use or exercise of any intellectual property right, such as patent right orcopyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of anythird-party's intellectual property right or other right by using such information. FUJITSU assumes no liabilityfor any infringement of the intellectual property rights or other rights of third parties which would result fromthe use of information contained herein.

• The products described in this document are designed, developed and manufactured as contemplated forgeneral use, including without limitation, ordinary industrial use, general office use, personal use, andhousehold use, but are not designed, developed and manufactured as contemplated (1) for useaccompanying fatal risks or dangers that, unless extremely high safety is secured, could have a seriouseffect to the public, and could lead directly to death, personal injury, severe physical damage or other loss(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,medical life support system, missile launch control in weapon system), or (2) for use requiring extremely highreliability (i.e., submersible repeater and artificial satellite).Please note that FUJITSU will not be liable against you and/or any third party for any claims or damagesarising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage orloss from such failures by incorporating safety design measures into your facility and equipment such asredundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

• If any products described in this document represent goods or technologies subject to certain restrictions onexport under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanesegovernment will be required for export of those products from Japan.

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READING THIS MANUAL

Terms Used in This Manual

The following defines principal terms used in this manual.

Term Meaning

I-bus32-bit bus for internal instructions. In the FR family, which is based on an internal Harvard architecture, independent buses are used for instructions and data. A bus converter is connected to the I-bus.

D-bus Internal 32-bit data bus. An internal resource is connected to the D-bus.

F-busPrinceton bus on which internal instructions and data are multiplexed. The F-bus is connected via a switch to the I-bus and D-bus. Built-in resources such as ROM and RAM are connected to the F-bus.

X-busExternal interface bus. An external interface module is connected to the X-bus. Data and instructions are multiplexed on the external data bus.

R-bus

Internal 16-bit data bus. The R-bus is connected to the D-bus via an adapter. I/O, a clock generator, and an interrupt controller are connected to the R-bus. Since addresses and data are multiplexed on an R-bus that is only 16 bits wide, more than one cycle is required for the CPU to access these resources.

E-unit Execution unit for operations.

CLKP

System clock. Clock generated by the clock generator for each of the internal resources connected to the R-bus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,... or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as determined by the divide-by rate specified by the B3 to B0 bits in the clock generator DIV0 register.

CLKB

System clock. Operating clock for the CPU and each of the other resources connected to a bus other than the R-bus and X-bus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ... or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as determined by the divided-by rate specified by the P3 to P0 bits in the clock generator DIV0 register.

CLKT

System clock. Operating clock for the external bus interface connected to the X-bus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ... or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as determined by the divide-by rate specified by the T3 to T0 bits in the clock generator DIV1 register.

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CONTENTS

CHAPTER 1 OVERVIEW ................................................................................................... 11.1 Features .............................................................................................................................................. 21.2 Block Diagram .................................................................................................................................... 71.3 External Dimensions ........................................................................................................................... 81.4 Pin Layout ........................................................................................................................................... 91.5 List of Pin Functions ......................................................................................................................... 101.6 Input-output Circuit Forms ................................................................................................................ 17

CHAPTER 2 HANDLING THE DEVICE .......................................................................... 232.1 Precautions on Handling the Device ................................................................................................. 24

CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 293.1 Memory Space .................................................................................................................................. 303.2 Internal Architecture .......................................................................................................................... 313.3 Programming Model ......................................................................................................................... 363.4 Data Configuration ............................................................................................................................ 433.5 Word Alignment ................................................................................................................................ 443.6 Memory Map ..................................................................................................................................... 453.7 Branch Instructions ........................................................................................................................... 463.8 EIT (Exception, Interrupt, and Trap) ................................................................................................. 49

3.8.1 EIT Interrupt Levels ..................................................................................................................... 503.8.2 Interrupt Control Unit (ICR) .......................................................................................................... 523.8.3 System Stack Pointer (SSP) ........................................................................................................ 533.8.4 Table Base Register (TBR) ......................................................................................................... 543.8.5 Multiple EIT Processing ............................................................................................................... 583.8.6 EIT Operations ............................................................................................................................ 60

3.9 Operating Modes .............................................................................................................................. 643.10 Reset (Device Initialization) .............................................................................................................. 67

3.10.1 Reset Levels ................................................................................................................................ 683.10.2 Reset Sources ............................................................................................................................. 693.10.3 Reset Sequence .......................................................................................................................... 713.10.4 Oscillation Stabilization Wait Time .............................................................................................. 723.10.5 Reset Operation Modes ............................................................................................................... 74

3.11 Clock Generation Control ................................................................................................................. 753.11.1 PLL Controls ................................................................................................................................ 763.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time ...................................................... 783.11.3 Clock Distribution ......................................................................................................................... 803.11.4 Clock Division .............................................................................................................................. 823.11.5 Block Diagram of Clock Generation Controller ............................................................................ 833.11.6 Register of Clock Generation Controller ...................................................................................... 843.11.7 Peripheral Circuits of Clock Controller ....................................................................................... 100

3.12 Device State Control ....................................................................................................................... 1043.12.1 Device States and State Transitions ......................................................................................... 105

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3.12.2 Low-power Modes ..................................................................................................................... 1103.13 Watch Timer ................................................................................................................................... 1143.14 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 120

CHAPTER 4 I/O PORT .................................................................................................. 1274.1 Overview of the I/O Port ................................................................................................................. 1284.2 I/O Port Registers ........................................................................................................................... 130

CHAPTER 5 16-BIT RELOAD TIMER ........................................................................... 1375.1 Overview of the 16-bit Reload Timer .............................................................................................. 1385.2 16-bit Reload Timer Registers ........................................................................................................ 139

5.2.1 Control Status Register (TMCSR) ............................................................................................. 1405.2.2 16-bit Timer Register (TMR) ...................................................................................................... 1435.2.3 16-bit Reload Register (TMRLR) ............................................................................................... 144

5.3 16-bit Reload Timer Operation ....................................................................................................... 145

CHAPTER 6 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ...................... 1516.1 Outline ............................................................................................................................................ 1526.2 Block Diagram of the PPG Timer .................................................................................................... 1536.3 Registers of the PPG Timer ............................................................................................................ 155

6.3.1 Control Status Register (PCNH, PCNL) .................................................................................... 1566.3.2 PPG Cycle Setting Register (PCSR) ......................................................................................... 1596.3.3 PPG Duty Setting Register (PDUT) ........................................................................................... 1606.3.4 PPG Timer Register (PTMR) ..................................................................................................... 161

6.4 PWM Mode ..................................................................................................................................... 1626.5 One-shot Mode ............................................................................................................................... 1646.6 Interrupts ......................................................................................................................................... 1666.7 PPG Output of ALL-L and ALL-H .................................................................................................... 1676.8 Precautions on Using the PPG Timer ............................................................................................. 168

CHAPTER 7 MULTIFUNCTION TIMER ........................................................................ 1697.1 Overview of the Multifunction Timer ............................................................................................... 1707.2 Registers of the Multifunction Timer ............................................................................................... 172

7.2.1 Low-Pass Filter Control Register (TxLPCR) .............................................................................. 1737.2.2 Capture Control Register (TxCCR) ............................................................................................ 1747.2.3 Timer Setting Register (TxTCR) ................................................................................................ 1767.2.4 Entire Timer Control Register (TxR) .......................................................................................... 1787.2.5 Timer Compare Data Register (TxDRR) ................................................................................... 1797.2.6 Capture Data Register (TxCRR) ................................................................................................ 1807.2.7 Test Mode Register (TMODE) ................................................................................................... 1817.2.8 Used Bit Description for Each Mode .......................................................................................... 182

7.3 Multifunction Timer Operation ......................................................................................................... 184

CHAPTER 8 16-BIT PULSE WIDTH COUNTER .......................................................... 1898.1 Overview of the 16-Bit Pulse Width Counter .................................................................................. 1908.2 Registers of the 16-Bit Pulse Width Counter .................................................................................. 191

8.2.1 PWC Control Register (PWCCL) ............................................................................................... 192

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8.2.2 PWC Control Register (PWCCH) .............................................................................................. 1948.2.3 PWC Data Register (PWCD) ..................................................................................................... 1968.2.4 PWC Control Register 2 (PWCC2) ............................................................................................ 1978.2.5 Upper Value Setting Register (PWCUD) ................................................................................... 198

8.3 Operation of the 16-Bit Pulse Width Counter .................................................................................. 199

CHAPTER 9 INTERRUPT CONTROLLER ................................................................... 2039.1 Overview of the Interrupt Controller ................................................................................................ 2049.2 Interrupt Controller Registers .......................................................................................................... 206

9.2.1 Interrupt Control Register (ICR) ................................................................................................. 2089.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) ........................................ 210

9.3 Interrupt Controller Operation ......................................................................................................... 2119.4 Example of Using the Hold Request Cancellation Request Function (HRCR) ............................... 214

CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 21710.1 Overview of the External Interrupt and NMI Controller ................................................................... 21810.2 External Interrupt and NMI Controller Registers ............................................................................. 219

10.2.1 Interrupt Enable Register (ENIR) ............................................................................................... 22010.2.2 External Interrupt Source Register (EIRR) ................................................................................ 22110.2.3 External Interrupt Request Level Setting Register (ELVR) ........................................................ 222

10.3 Operation of the External Interrupt and NMI Controller .................................................................. 223

CHAPTER 11 REALOS-RELATED HARDWARE .......................................................... 22711.1 Delayed Interrupt Module ............................................................................................................... 22811.2 Delayed Interrupt Module Registers ............................................................................................... 22911.3 Operation of the Delayed Interrupt Module ..................................................................................... 23011.4 Bit Search Module .......................................................................................................................... 23111.5 Bit Search Module Registers .......................................................................................................... 23211.6 Bit Search Module Operation .......................................................................................................... 235

CHAPTER 12 10-BIT A/D CONVERTER ........................................................................ 23912.1 Overview of the 10-Bit A/D Converter ............................................................................................. 24012.2 Registers of the 10-Bit A/D Converter ............................................................................................ 241

12.2.1 A/DC Control Register (ADCTH, ADCTL) ................................................................................. 24212.2.2 Software Conversion Analog Input Select Register ................................................................... 24412.2.3 A/D Conversion Result Register (Channels 0 to 9) ................................................................... 24512.2.4 A/D Converter Test Register ..................................................................................................... 246

12.3 Operation of the 10-Bit A/D Converter ............................................................................................ 247

CHAPTER 13 U-TIMER ................................................................................................... 24913.1 Overview ......................................................................................................................................... 25013.2 U-TIMER Registers ......................................................................................................................... 25113.3 U-TIMER Operation ........................................................................................................................ 254

CHAPTER 14 UART ........................................................................................................ 25514.1 Overview of the UART .................................................................................................................... 25614.2 UART Registers .............................................................................................................................. 258

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14.2.1 Serial Mode Register (SMR) ...................................................................................................... 25914.2.2 Serial Control Register (SCR) ................................................................................................... 26114.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................... 26414.2.4 Serial Status Register (SSR) ..................................................................................................... 26514.2.5 UART Operation ........................................................................................................................ 26914.2.6 Asynchronous (Start-stop Synchronization) Mode .................................................................... 27114.2.7 Clock Synchronous Mode .......................................................................................................... 27214.2.8 Occurrence of Interrupts and Timing for Setting Flags .............................................................. 274

14.3 Example of Using the UART ........................................................................................................... 27714.4 Example of Setting U-TIMER Baud Rates and Reload Values ...................................................... 279

CHAPTER 15 I2C INTERFACE ....................................................................................... 28115.1 Overview of the I2C Interface .......................................................................................................... 28215.2 I2C Interface Registers ................................................................................................................... 287

15.2.1 Bus Status Register (IBSR) ....................................................................................................... 28915.2.2 Bus Control Register (IBCR) ..................................................................................................... 29215.2.3 Clock Control Register (ICCR) .................................................................................................. 29815.2.4 10-bit Slave Address Register (ITBA) ........................................................................................ 30015.2.5 10-bit Slave Address Mask Register (ITMK) ............................................................................. 30115.2.6 7-bit Slave Address Register (ISBA) ......................................................................................... 30315.2.7 7-bit Slave Address Mask Register (ISMK) ............................................................................... 30415.2.8 Data Register (IDAR) ................................................................................................................. 30515.2.9 Clock Disable Register (IDBL) ................................................................................................... 306

15.3 I2C Interface Operation ................................................................................................................... 31015.4 Operation Flowcharts ...................................................................................................................... 315

CHAPTER 16 DMA CONTROLLER (DMAC) .................................................................. 31916.1 Overview of the DMA Controller (DMAC) ....................................................................................... 32016.2 DMA Controller (DMAC) Registers ................................................................................................. 322

16.2.1 Control/Status Registers A (DMACA0 to DMACA4) .................................................................. 32416.2.2 Control/Status Registers B (DMACB0 to DMACB4) .................................................................. 32916.2.3 Transfer Source/Transfer Destination Address Setting Registers

(DMASA0 to 4/DMADA0 to 4) ................................................................................................... 33616.2.4 All-Channel Control Register (DMACR) .................................................................................... 33816.2.5 Other Functions ......................................................................................................................... 340

16.3 DMA Controller Operation .............................................................................................................. 34116.3.1 Setting a Transfer Request ........................................................................................................ 34416.3.2 Transfer Sequence .................................................................................................................... 34616.3.3 General Aspects of DMA Transfer ............................................................................................. 35116.3.4 Addressing Mode ....................................................................................................................... 35316.3.5 Data Types ................................................................................................................................ 35416.3.6 Transfer Count Control .............................................................................................................. 35516.3.7 CPU Control .............................................................................................................................. 35616.3.8 Hold Arbitration .......................................................................................................................... 35716.3.9 Operation from Starting to End/Stopping ................................................................................... 35816.3.10 DMAC Interrupt Control ............................................................................................................. 36216.3.11 Channel Selection and Control .................................................................................................. 363

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16.3.12 Supplement on External Pin and Internal Operation Timing ..................................................... 36516.4 Operation Flowcharts ...................................................................................................................... 37016.5 Data Bus ......................................................................................................................................... 373

CHAPTER 17 USB FUNCTION ....................................................................................... 37717.1 Overview of the USB Function ........................................................................................................ 37817.2 USB Interface Registers ................................................................................................................. 381

17.2.1 Data Transmission Registers (for End Points) .......................................................................... 38417.2.2 Status Registers ........................................................................................................................ 38717.2.3 Control Registers ....................................................................................................................... 394

17.3 Operation of the USB Function ....................................................................................................... 40917.3.1 Flow of Data Transfer ................................................................................................................ 41017.3.2 CPU Access Operation .............................................................................................................. 41617.3.3 Interrupt Sources ....................................................................................................................... 42317.3.4 Setting of End Point Buffer ........................................................................................................ 42417.3.5 Examples of Software Control ................................................................................................... 426

17.4 Supplementary Notes on the USB Function ................................................................................... 43517.4.1 Double Buffer ............................................................................................................................. 43617.4.2 Controlling the D+ Terminating Resistor on the Board .............................................................. 44117.4.3 Automatic Response of Macro Program to USB Standard Request Commands ...................... 44217.4.4 USB Function Macro Program Operation in the Default Status ................................................ 44417.4.5 USB Clock Control in the Suspended Status ............................................................................ 44517.4.6 Detection of USB Connector Connection and Disconnection .................................................... 44617.4.7 Accuracy of UCLK48 ................................................................................................................. 44717.4.8 Setting of Transfer Enable bit (BFOK) during Control Transfer ................................................. 44817.4.9 Precautions for Control Transfer ............................................................................................... 44917.4.10 Macro Program Status after USB Bus Reset ............................................................................ 451

CHAPTER 18 OSDC ........................................................................................................ 45318.1 ON-SCREEN DISPLAY CONTROLLER (OSDC) ........................................................................... 454

18.1.1 Features .................................................................................................................................... 45518.1.2 Block Diagram ........................................................................................................................... 457

18.2 Display Functions ........................................................................................................................... 45818.2.1 Screen Configuration ................................................................................................................. 45918.2.2 Screen Display Modes ............................................................................................................... 46218.2.3 Screen Output Control ............................................................................................................... 46418.2.4 Screen Display Position Control ................................................................................................ 46518.2.5 Font Memory Configuration ....................................................................................................... 47518.2.6 Display Memory (VRAM) Configuration ..................................................................................... 47618.2.7 Writing to Display Memory (VRAM) ........................................................................................... 47718.2.8 Palette Configuration ................................................................................................................. 48018.2.9 Character Display ...................................................................................................................... 48118.2.10 Character Background Display .................................................................................................. 51518.2.11 Line Background Display ........................................................................................................... 52418.2.12 Screen Background Display ...................................................................................................... 53318.2.13 Sprite Character Display ............................................................................................................ 538

18.3 Control Functions ............................................................................................................................ 542

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18.3.1 Dot Clock Control ...................................................................................................................... 54318.3.2 Sync Signal Input ....................................................................................................................... 54818.3.3 Display Signal Output ................................................................................................................ 55618.3.4 Display Period Control ............................................................................................................... 55918.3.5 Synchronization Control ............................................................................................................ 56118.3.6 Interrupt Control ......................................................................................................................... 56418.3.7 OSDC Operation Control ........................................................................................................... 567

18.4 Display Control Commands ............................................................................................................ 56918.4.1 List of Display Control Commands ............................................................................................ 57018.4.2 VRAM Write Address Set (Command 0) ................................................................................... 57218.4.3 Character Data Set (Commands 1 and 2) ................................................................................. 57318.4.4 Line Control Data Set (Commands 3 and 4) ............................................................................. 57518.4.5 Screen Output Control (Commands 5-00 and 5-1) .................................................................... 57718.4.6 Display Position Control (Commands 5-2 and 5-3) ................................................................... 57918.4.7 Character Vertical Size Control (Command 6-0) ....................................................................... 58018.4.8 Shaded Background Frame Color Control (Command 6-1) ...................................................... 58118.4.9 Transparent/Translucent Color Control (Command 6-2) ........................................................... 58218.4.10 Graphic Color Control (Command 6-3) ...................................................................................... 58318.4.11 Screen Background Character Control (Commands 7-1 and 7-3) ............................................ 58518.4.12 Sprite Character Control (Commands 8-1, 8-2, 9-0 and 9-1) .................................................... 58718.4.13 Synchronization Control (Command 11-0) ................................................................................ 59018.4.14 I/O Pin Control (Commands 13-0 and 13-1) .............................................................................. 59118.4.15 Display Period Control (Commands 14-0 to 14-3) ..................................................................... 59318.4.16 Interrupt Control (Command 15-0) ............................................................................................ 59618.4.17 Palette Control (Commands 16-0 to 16-15) ............................................................................... 59718.4.18 OSDC Operation Control (Commands 17-0 and 17-1) .............................................................. 59918.4.19 PLLA Clock Control (Commands 18-0 to 18-3) ......................................................................... 60118.4.20 PLLB Clock Control (Commands 18-4 to 18-7) ......................................................................... 60318.4.21 PLLC Clock Control (Commands 18-8 to 18-11) ....................................................................... 60518.4.22 Clock Selection Control (Commands 18-12 to 18-13) ............................................................... 607

18.5 Display Control Command (CC) ..................................................................................................... 60918.5.1 CC Screen and Display Control Command List ........................................................................ 61018.5.2 VRAM Write Address Setting (Command 0) ............................................................................. 61118.5.3 Character Data Setting (Command 1, Command 2) ................................................................. 61218.5.4 Line Control Data Setting (Command 3, Command 4) .............................................................. 61418.5.5 Display Output Control (Command 5-00, Command 5-1) ......................................................... 61618.5.6 Display Position Control (Command 5-2, Command 5-3) ......................................................... 61818.5.7 Character Vertical Size Control (Command 6-0) ....................................................................... 61918.5.8 Transparent Color Control (Command 6-2) ............................................................................... 62018.5.9 Display Period Control (Command 14-0, 14-1, 14-2, 14-3) ....................................................... 62118.5.10 Interrupt Control (Command 15-0) ............................................................................................ 62318.5.11 Palette Control (Command 16-0 to Command 16-15) ............................................................... 624

18.6 FONT RAM Interface ...................................................................................................................... 625

CHAPTER 19 FLASH MEMORY ..................................................................................... 62919.1 Outline of Flash Memory ................................................................................................................. 63019.2 Flash Memory Registers ................................................................................................................. 637

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19.2.1 Flash Control/Status Register (FLCR) ....................................................................................... 63819.2.2 Flash Memory Wait Register (FLWC) ........................................................................................ 640

19.3 Flash Memory Access Modes ......................................................................................................... 64219.4 Automatic Algorithm of Flash Memory ............................................................................................ 64419.5 Execution Status of the Automatic Algorithm .................................................................................. 64819.6 Writing to and Erasing from Flash Memory .................................................................................... 653

19.6.1 Read/Reset Status .................................................................................................................... 65419.6.2 Data Writing ............................................................................................................................... 65519.6.3 Data Erasure (Chip Erasure) ..................................................................................................... 65719.6.4 Data Erasure (Sector Erasure) .................................................................................................. 65819.6.5 Temporary Sector Erase Stop ................................................................................................... 66019.6.6 Sector Erase Restart ................................................................................................................. 661

CHAPTER 20 SERIAL PROGRAMMING CONNECTION .............................................. 66320.1 Serial Programming Connection ..................................................................................................... 664

APPENDIX ......................................................................................................................... 669APPENDIX A I/O Map ................................................................................................................................ 670APPENDIX B Interrupt Vector .................................................................................................................... 685APPENDIX C Dot Clock Generation PLL ................................................................................................... 688APPENDIX D USB Clock ............................................................................................................................ 690APPENDIX E Macro Reset ......................................................................................................................... 691APPENDIX F USB Low-power Consumption Mode ................................................................................... 692APPENDIX G External Bus Interface Setting ............................................................................................. 693APPENDIX H Pin State List ........................................................................................................................ 695APPENDIX I Instruction Lists .................................................................................................................... 699

I.1 How to Read the Instruction Lists .................................................................................................. 700I.2 FR Family Instruction Lists ............................................................................................................. 704

INDEX................................................................................................................................... 721

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xv

Main changes in this edition

Page Changes (For details, refer to main body.)

-

Change pin names(TO0 → TOUT0)(TO1 → TOUT1)(TO2 → TOUT2)

3 Change Built-in RAM (MASK: Add 32KB RAM)

4 Change A/D Converter (conversion time: about 10 µs → conversion time: about 8.5 µs)

6 Change CMOS technology of Other Features

6 Change Supply voltage of Other Features

7

Change the Figure 1.2-1 Block Diagram(Add DSU)(Add MASK 512KB to Flash 1MB)(Add MASK 32KB to RAM)(PWC 1ch → PWC 4ch)(Add Font ROM product)

9

Change Figure 1.4-1 Pin Layout of the MB91319(MB91F318A → MB91F318A/S)(MB91FV319A → MB91FV319A/R)(Change the Note)

24 Add a sentence to Quartz Oscillation Circuit

26 Change Low Power Consumption Mode of Limitations

27 Change Note on using A/D

27 Add About Software Reset of Synchronous Mode

28Change Unique characteristic of the evaluation chip MB91FV319A

(MB91FV319A → MB91FV319A/R)

30Change Figure 3.1-1 Memory Map

(MB91F318 → MB91F318A/S and MB91FV319R)(MB91F318, MB91316 → MB91F318A/S, MB91316)

70 Add Reference: to Software Reset (STCR: SRST Bit Writing)

70Change Watchdog Reset (watchdog reset postpone register (WPR) → time base counter clear register (CTBR))

74 Add Reference: to Synchronous Reset Operation

81 Add items to Notes: for External Bus Clock (CLKT)

83Change Figure 3.11-1 Block Diagram of Clock Generation Controller

(Delete WPR register)

85 Change [bit9, bit8] WT1, WT0 (Watchdog interval Time select) (WPR → CTBR)

87 Add Reference: to [bit4] SRST (Software ReSeT)

90 Add Note: to [bit9] SYNCR (SYNChronous Reset enable)

xvi

90 Add Note: to [bit8] SYNCS (SYNChronous Standby enable)

91 Change Time Base Counter Clear Register (CTBR)

94 Delete Watchdog Reset Postpone Register (WPR)

100Change [Postponing a watchdog reset] (watchdog reset postpone register (WPR) → time base counter clear register (CTBR))

106 Change Figure 3.12-1 Transition of Device States

111 Delete [Normal and synchronous standby operations]

130 Change Figure 4.2-1 Configuration of the Port Data Registers (PDR) (P75 → − )

131 Change Figure 4.2-2 Configuration of the Data Direction Registers (DDR) (P75 → − )

137 to 150 Replace the entire chapter CHAPTER 5 16-BIT RELOAD TIMER

180 Change Capture Data Register (TxCRR)

182 Add 7.2.8 Used Bit Description for Each Mode

240 Change Features of the 10-Bit A/D Converter

240Change Figure 12.1-2 Block Diagram of the 10-Bit A/D Converter

(Add AN9) (Add AN8)

241 Change Figure 12.2-1 Register Configuration of the 10-Bit A/D Converter

244

Change the bit9 and bit8 of Figure 12.2-3 Bit Configuration of the Software Conversion Analog Input Select Register

("0" → i9)("0" → i8)

244 Change the [bit9 to bit0] i9 to i0 (i7 to i0 → i9 to i0)

247 Change A/D Conversion Started by External Trigger

254 Change Asynchronous (start-stop synchronization) mode

254 Change CLK synchronous mode

256Change the Features (Delete "The DMAC interrupt source is cleared if the DRCL register is written to.")

258 Change Figure 14.2-1 UART Registers (Delete DMA request clear register (DRCL))

269 Delete DRCL Register description

276Change Precautions on Usage (Delete "Write to the DRCL register before starting DMA transfer due to an interrupt for the first time.")

293 Add a sentence to Note:

353 Change the second bullet under the Address Register Specifications

362 Change DMA Transfer during Sleep

365 Change Timing to Stop a Demand Transfer Request and Timing to Invalidate the DREQ Pin Input

366Change Figure 16.3-6 Example of the Timing for Negating the DREQ Pin Input for 2-Cycle Transfer from an External Circuit to an Internal Circuit


xvii

366 Change • For transfer from internal to external circuits:

367 Change For fly-by transfer

367Change Figure 16.3-7 Example of the Timing for Negating the DREQ Pin Input for Fly-by (Timing to IORD Pin) Transfer

456Change Interrupt functions (MAIN is connected to the external interrupt ch5, cc is connected to the external interrupt ch6) (Add "MAIN is connected to the external interrupt ch5, cc is connected to the external interrupt ch6" )

546 Change Table 18.3-5 Oscillating VCO Selection Control

632 Change Figure 19.1-2 Memory Mapping for Access in Flash Memory Mode/CPU Mode

633Change the title of Figure 19.1-3 Sector Configuration in CPU Mode (MB91FV319A, MB91F318A) (add (MB91FV319A, MB91F318A))

634 Add Figure 19.1-4 Sector Configuration in CPU Mode (MB91F318S, MB91FV319R)

635Change the title of Figure 19.1-5 Sector Configuration in FLASH Mode (MB91FV319A, MB91F318A) (add (MB91FV319A, MB91F318A))

636 Add Figure 19.1-6 Sector Configuration in FLASH Mode (MB91F318S, MB91FV319R)

644 Change Basic Configuration of Serial Programming Connection

644Change the title of Table 19.4-1 Command Sequence (MB91FV319A, MB91F318A) (add (MB91FV319A, MB91F318A))

644 Add Table 19.4-2 Command Sequence (MB91F318S, MB91FV319R)

665Change Notes: (MB91FV319A Write control pin → MB91FV319A/R MB91F318A/S Write control pin)

666Change Figure 20.1-1 Example of Serial Programming Connection

(MB91FV319A → MB91FV319A/R, MB91F318A/S)

671 to 679

Change the Table A-1 I/O Map(DRCL0 [W] -------- → DRCL0 --------*3)(DRCL1 [W] -------- → DRCL1 --------*3)(DRCL2 [W] -------- → DRCL2 --------*3)(DRCL3 [W] -------- → DRCL3 --------*3)(Change 000160H to 00017CH and 000180H to 00019CH to "Reserved")(WPR [W] XXXXXXXX → WPR --------*3)(Delete Address 007100H line)(Delete Address 007104H line)(Add *3: Reserved register. Access is disabled.)

688 Change Figure C-1 CP0 Pin Connection

689Change the table and add a table

(Table C-2 0.25 µm: EVA, FLASH)(Table C-3 0.18 µm: EVA, FLASH, MASK)


CHAPTER 1OVERVIEW

This chapter provides basic information required to understand the MB91319 series, and covers features, a block diagram, and functions.

1.1 Features

1.2 Block Diagram

1.3 External Dimensions

1.4 Pin Layout

1.5 List of Pin Functions

1.6 Input-output Circuit Forms

1

CHAPTER 1 OVERVIEW

1.1 Features

The FR family is a single-chip microcontroller that has a 32-bit high-performance RISC CPU as well as built-in I/O resources for embedded controllers requiring high-performance and high-speed CPU processing.The FR family is the most suitable for embedded applications, for example, TV and PDP control, that require a high level of CPU processing performance.This model is an FR60 series model that is based on the FR30/40-family of CPUs. It has enhanced bus access and is optimized for high-speed use.

FR CPU

• 32-bit RISC, load/store architecture, five stages pipeline

• Operating frequency of 40 MHz [PLL used, original oscillation at 10 MHz]

• 16-bit fixed-length instructions (basic instructions), one instruction per cycle

• Memory-to-memory transfer, bit processing, instructions including barrel shift, etc.:instructions appropriate for embedded applications

• Function entry and exit instructions, multi load/store instructions:instructions compatible with high-level languages

• Register interlock function to facilitate assembly-language coding

• Built-in multiplier/instruction-level support

• Signed 32-bit multiplication: 5 cycles

• Signed 16-bit multiplication: 3 cycles

• Interrupts (saving of PC and PS): 6 cycles, 16 priority levels

• Harvard architecture enabling simultaneous execution of both program access and dataaccess

• 4-word queues in the CPU provided to add an instruction prefetch function

• Instructions compatible with the FR family

Bus Interface

This bus interface is used for macro connections (USB and OSDC).

• Maximum operating frequency of 20 MHz

• 16-bit data input-output (interface with USB and OSDC)

• Totally independent 8-area chip select outputs that can be defined in the minimum units of64K bytes The CS1, CS2, and CS3 areas are reserved as shown below.

• CS1 area: Reserved

• CS2 area: USB function

• CS3 area: OSDC

• Basic bus cycle (2 cycles)

2

CHAPTER 1 OVERVIEW

• Automatic wait cycle generator that can be programmed for each area and can insert waitsbecause CS1, CS2, and CS3 are reserved, the setting is fixed.

Built-in RAM

• EVA: 64KB RAM, FLASH: 48KB RAM, MASK: 32KB RAM

• This RAM can be used as data RAM and instruction RAM if instruction codes are written to it.

DMAC (DMA Controller)

• 5 channels (channels 0 and 1 are connected to the USB function.)

• 3 transfer sources (internal peripherals, software)

• Addressing mode with 32-bit full address specifications (increase, decrease, fixed)

• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)

• Transfer data size that can be selected from 8, 16, and 32 bits

Bit Search Module (Used by REALOS)

• Searches for the position of the first bit varying between 1 and 0 in the MSB of a word

Reload Timer (Including One Channel for REALOS)

• 16-bit timer; 3 channels

• Internal clock that can be selected from those resulting from frequency divided by 2, 8, and 32

UART

• Full-duplex double buffer

• 5 channels

• Parity or no parity can be selected.

• Either asynchronous (start-stop synchronization) or CLK synchronous communication can beselected.

• Built-in timer for dedicated baud rates

• An external clock can be used as the transfer clock.

• Plentiful error detection functions (parity, frame, overrun)

3

CHAPTER 1 OVERVIEW

I2C Interface

• 4 channels (channel 3 can be used for two ports.)

• Master/slave transmission and reception

• Clock synchronization function

• Transfer direction detection function

• Bus error detection function

• Supports standard mode (Max. 100 Kbps) and high-speed mode (Max, 400 Kbps).

• Arbitration function

• Slave address/general call address detection function

• Start condition repetitious occurrence and detection function

• 10-bit/7-bit slave address

• Built-in FIFO function: each 16-byte sending/receiving

Interrupt Controller

• Total of 5 external interrupts (one unmaskable pin (NMI) and four regular interrupt pins (INT3to INT0))

• Interrupts from internal peripherals

• Priority level can be defined as programmable (16 levels) except for the unmaskable pin

• Can be used for wake-up during stop.

A/D Converter

• 10-bit resolution, 10 channels

• Sequential comparison and conversion type (conversion time: about 8.5 µs)

• Conversion modes (single conversion mode and scan conversion mode)

• Causes of startup (software and external triggers)

PPG

• 4 channels

• 16-bit data register with 16-bit down counter and cycle setting buffer

• Internal clock: Frequency-divide-by number selectable from 1, 4, 16, and 64

PWC

• 1 channel (1 input)

• 16-bit up counter

• Simple LFP digital filter

4

CHAPTER 1 OVERVIEW

Multifunction Timer

• Low-pass filter that removes noise that is below the frequency of the set clock

• Pulse width measurement that can be performed by precise settings using seven types ofclock signals

• Event count for signals from pin input

• Interval timer using seven types of clocks and external input clocks

USB Function

• USB2.0 full-speed, double buffer

• CONTROL IN/OUT, BULK IN/OUT, and INTERRUPT IN

OSDC Function

• 3 bits per color - Red, Green and Blue (of 512 colors, 16 can be displayed)

• Analog RGB output maximum 50 MHz

• Digital RGB output maximum 90 MHz

• Display 24 × 32 dots font can be displayed as maximum 80 × 32

• MAIN/CC two-layer display (font is fixed at 18 dots wide for the CC layer)

• Maximum 4096 character types (font RAM: 16 characters)

Closed Caption Decoder Function

• 2 channels available

• CC decode function

• ID-1 (480i/480p) decode function

Video Clock PLL

• PLLs available to generate dot clock and VBI clock

Other Interval Timers

• 16-bit timer: 3 channels (U-TIMER)

• Watchdog timer

I/O Ports

• Maximum of 88 ports

5

CHAPTER 1 OVERVIEW

Other Features

• Has a built-in oscillation circuit as a clock source.

• INIT is provided as a reset pin.

• Additionally, a watchdog timer reset and software resets are provided.

• Stop mode and sleep mode supported as low-power modes

• Gear function

• Built-in time base timer

• Package: LQFP-176, 0.5 mm pitch, and 24 mm × 24 mm

• CMOS technology: 0.25 µm (EVA(MB91FV319A), FLASH (MB91F318A))0.18 µm (MASK(MB91316), EVA(MB91FV319R), FLASH (MB91F318S))

• Supply voltage: two sources of 3.3 V (-0.3 V to +0.3 V) and 2.5 V (-0.2 V to +0.2 V) (0.25 µm : EVA(MB91FV319A), FLASH (MB91F318A))two sources of 3.3 V (-0.3 V to +0.3 V) and 1.8 V (-0.15 V to +0.15 V) (0.18 µm : MASK(MB91316), EVA(MB91FV319R), FLASH (MB91F318S))

THE I2C LICENSE:

Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to

use, these components in an I2C system provided that the system conforms to the I2CStandard Specification as defined by Philips.

6

CHAPTER 1 OVERVIEW

1.2 Block Diagram

Figure 1.2-1 is a block diagram of the MB91319.

Block Diagram

Figure 1.2-1 Block Diagram

OSDCFont ROMFLASH 512 KB*2

ROM 384 KB*2

32 to 16 adapter

USBfunction

Multifunction timer 4ch

Interruptcontroller

Clockcontrol

FR CPU Core

Flash 1MBMASK 512KB

RAMEVA 64KBFLASH 48KBMASK 32KB

Bit search

Bus converterDMAC5ch

DSU*1

Reloadtimer 3ch

PWC4ch

PPG4ch

Port

A/D10ch

CCD2ch

UART5ch

I2C4ch

32

32

Externalinterrupt

Externalmemory

I/F

*1 : DSU is loaded only in MB91FV319A/R*2 : Font ROM: MB91FV319A/R: FLASH 512 KB : MB91F318A/S, MB91316 : MASK ROM 384 KB

7

CHAPTER 1 OVERVIEW

1.3 External Dimensions

The MB91319 is available in one type of package.Figure 1.3-1 shows the dimensions of the MB91319.

Dimensions of the MB91319

Figure 1.3-1 External Dimensions of MB91319

176-pin plastic LQFP Lead pitch 0.50 mm

Package width ×package length

24.0 × 24.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Code(Reference)

P-LQFP-0176-2424-0.50

176-pin plastic LQFP(FPT-176P-M07)

(FPT-176P-M07)

C 2004 FUJITSU LIMITED F176013S-c-1-1

Details of "A" part

0˚~8˚

0.50±0.20(.020±.008)0.60±0.15

(.024±.006)

0.25(.010)

(Stand off)(.004±.004)0.10±0.10

1.50+0.20–0.10

+.008–.004.059

(Mounting height)

0.08(.003)

(.006±.002)0.145±0.055

"A"

INDEX

1LEAD No. 44

45

88

89132

133

176

0.50(.020) 0.22±0.05(.009±.002)

M0.08(.003)

*24.00±0.10(.945±.004)SQ

26.00±0.20(1.024±.008)SQ

Dimensions in mm (inches).Note: The values in parentheses are reference values.

Note 1) * : Values do not include resin protrusion.Resin protrusion is +0.25(.010)Max(each side).

Note 2) Pins width and pins thickness include plating thicknessNote 3) Pins width do not include tie bar cutting remainder.

8

CHAPTER 1 OVERVIEW

1.4 Pin Layout

This section shows the pin layout of the MB91319.

Pin Layout of the MB91319

Figure 1.4-1 is a diagram of the pin layout of the MB91319.

Figure 1.4-1 Pin Layout of the MB91319

Note: Do not be connected anything to TRST, ICS2 to ICS0, ICD3 to ICD0, ICLK and IBREAK pins on MB91FV319AR.Because these pins are used as open pins on MB91F318A/S, and MB91316.

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

123456789

101112131415161718192021222324252627282930313233343536

132131130129128127126125124123122121120119118117116115114113112111110109108107106105104103102101100999897

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

TOP VIEW

LQFP-176MB91FV319A/RMB91F318A/S

MB91316

140

139

138

137

136

135

134

133

3738394041424344

9695949392919089

81 82 83 84 85 86 87 88

P02/SCK4/TIN2P01/SO4/TIN1P00/SI4/TIN0P74P73P72P71P70VDDEVSSVDDIP57P56P55P54P53P52/SCK3P51/SO3P50/SI3P47/SCK2P46/SO2P45/SI2P44/SDA4P43/SDA3P42/SCL4P41/SCL3P40/SDA2P37/SCL2P36/TRG3P35/TRG2P34/TRG1P33/TRG0NMIXPA2/INT3PA1/INT2PA0/INT1VDDIX1AVSSX0AVDDEP97/INT0P96/TMI3P95/TMI2

VS

YN

CD

OC

KI

DC

KO

FH

VO

B1

VO

B2

VD

DI

R2

R1

R0

G2

G1

G0

B2

B1

B0

UD

PU

DM

VD

DE

X0B

VS

SX

1BV

DD

IP

B7

PB

6P

B5

PB

4P

B3

PB

2P

B1

PB

0P

17P

16/A

TR

GP

15/P

PG

3P

14/P

PG

2P

13/P

PG

1P

12/P

PG

0P

11/T

MO

3P

10/T

MO

2P

07/T

MO

1P

06/T

MO

0P

05/T

OU

T2

P04

/TO

UT

1P

03/T

OU

T0

P94/T

MI1

P93/T

MI0

P92/R

INP

91/SC

K1

P90/S

O1

P87/S

I1P

86/SC

K0

P85/S

O0

P84/S

I0P

83/SD

A1

P82/S

CL1

P81/S

DA

0P

80/SC

L0IN

ITX

MD

3M

D2

MD

1M

D0

ICD

3IC

D2

ICD

1IC

D0

ICS

2IC

S1

ICS

0IB

RE

AK

ICLK

TR

ST

XV

DD

IX

1V

SS

X0

VD

DE

P32

P31

P30

P27

P26

P25

P24

P23

P22

P21/A

N9

P20/A

N8

PC7/AN7PC6/AN6PC5/AN5PC4/AN4PC3/AN3PC2/AN2PC1/AN1PC0/AN0

AVSS/AVRLAVRHAVCCVDDI

VSSSVDDIS

VIN1VIN0

VSSBBOUTVDDBVSSGGOUTVDDGVSSRROUT

VR0(2.7kΩ)VRef(1.1V)

VDDRVDDP3VSSP3

VGS3/BCI3CP03

VDDP2VSSP2

CP02VGS2/BCI2

VDDP1VSSP1

CP01VGS1/BCI1

VSSVDDDE

HSYNC3HSYNC2HSYNC1

9

CHAPTER 1 OVERVIEW

1.5 List of Pin Functions

This section describes the pin functions of the MB91319.

List of Pin Functions

Table 1.5-1 lists the pin functions.

Table 1.5-1 Pin Functions of the MB91319 (1 / 7)

Pin number Pin name I/O circuit type Function

1 HSYNC1 G Horizontal synchronous input 1



4 VDDE - I/O power supply

5 VSS - Ground

6 VGS1/VCI1 - Guard band ground

7 CPO1 K Charge pump output

8 VSSP1 - Dot clock PLL ground

9 VDDP1 - Dot clock PLL power supply (2.5 V)









18 VDDR - D/A power supply for Red

19 VREF(1.1V) K Voltage reference input

20 VRO(2.7kΩ) K Resistor connection pin

21 ROUT K Output for Red (analog)

22 VSSR - D/A ground for Red

23 VDDG - D/A power supply for Green

24 GOUT K Output for Green (analog)

25 VSSG - D/A ground for Green

26 VDDB - D/A power supply for Blue

27 BOUT K Output for Blue (analog)

28 VSSB - D/A ground for Blue

29 VIN0 K Data slicer input 0

30 VIN1 K Data slicer input 1

10

CHAPTER 1 OVERVIEW

31 VDDIS - Data slicer power supply (2.5 V)

32 VSSS - Data slicer ground

33 VDDI - Internal logic power supply (2.5 V)

34 AVCC - A/D power supply

35 AVRH - A/D reference power supply

36 AVSS/AVRL - A/D ground

37PC0

EGeneral-purpose port

AN0 Analog input

38PC1


AN1 Analog input

39PC2


AN2 Analog input

40PC3


AN3 Analog input

41PC4


AN4 Analog input

42PC5


AN5 Analog input

43PC6


AN6 Analog input

44PC7


AN7 Analog input

45P20


AN8 Analog input

46P21


AN9 Analog input

47 P22 C General-purpose port









56 VDDE - 3.3 V power supply

57 X0 A 10 MHz oscillation pin

58 VSS - Ground

59 X1 A 10 MHz oscillation pin



11

CHAPTER 1 OVERVIEW


61TRSTX

BDSU tool reset (this pin is open in the MB91F31x model series. DO NOT CONNECT)

62ICLK

MDSU clock (this pin is open in the MB91F31x model series. DO NOT CONNECT)

63IBREAK

LDSU break (this pin is open in the MB91F31x model series. DO NOT CONNECT)

64ICS0

ODSU status (this pin is open in the MB91F31x model series. DO NOT CONNECT)

65ICS1


66ICS2


67ICD0

PDSU data (this pin is open in the MB91F31x model series. DO NOT CONNECT)

68ICD1


69ICD2


70ICD3


71 MD0 F Mode pin

72 MD1 F Mode pin

73 MD2 F Mode pin

74 MD3 L Mode pin

75 INITX B Initial (reset) pin

76P80

JGeneral-purpose port

SCL0 I2C clock pin

77P81


SDA0 I2C data pin

78P82


SCL1 I2C clock pin

79P83


SDA1 I2C data pin

80P84

CGeneral-purpose port

SI0 UART 0 serial input

81P85


SO0 UART 0 serial output

82P86


SCK0 UART 0 clock I/O

83P87





12

CHAPTER 1 OVERVIEW

84P90



85P91



86P92


RIN PWC input

87P93


TMI0 Multifunction timer 0 input

88P94



89P95



90P96



91P97

OGeneral-purpose port

INT0 External interrupt input 0


93 X0A A 32 kHz oscillation pin

94 VSS - Ground

95 X1A A 32 kHz oscillation pin


97PA0



98PA1



99PA2



100 NMIX B NMIX input

101P33


TRG0 PPG 0 trigger input

102P34



103P35



104P36



105P37

NGeneral-purpose port

SCL2 I2C clock pin



13

CHAPTER 1 OVERVIEW

107P41


SCL3 I2C clock pin

108P42


SCL4 I2C clock pin

106P40


SDA2 I2C data pin

109P43


SDA3 I2C data pin

110P44


SDA4 I2C data pin

111P45



112P46



113P47



114P50



115P51



116P52



117P53


CS7X Chip select

118P54


CS6X Chip select

119P55


CS5X Chip select

120P56


CS4X Chip select

121P57


CS0X Chip select


123 VSS - Ground








14

CHAPTER 1 OVERVIEW


130

P00

C

General-purpose port


TIN0 Reload timer 0 trigger input

131

P01

C




132

P02

C




133P03


TOUT0 Reload timer 0 output

134P04



135P05



136P06


TMO0 Multifunction timer 0 output

137P07



138P10



139P11



140P12


PPG0 PPG 0 output

141P13


PPG1 PPG 1 output

142P14


PPG2 PPG 2 output

143P15


PPG3 PPG 3 output

144P16


ATRG A/D conversion trigger input


146 PB0 C General-purpose port


148 PB2 I General-purpose port




15

CHAPTER 1 OVERVIEW



152 PB6 H General-purpose port


154 VDDI - Internal power supply (2.5 V)

155 X1B A 48 MHz oscillation pin

156 VSS - Ground

157 X0B A 48 MHz oscillation pin


159 UDMUSB

USB-Function

160 UDP USP-Function

161 B0 D RGB digital output



164 G0 D RGB digital output



167 R0 D RGB digital output




171 VOB2 D Semi-transparent color period output

172 VOB1 D OSD display period output

173 FH D Horizontal synchronous output

174 DCKO D Dot clock output

175 DOCKI G Dot clock input

176 VSYNC G Vertical synchronous output



16

CHAPTER 1 OVERVIEW

1.6 Input-output Circuit Forms

This section describes the input-output circuit types of the MB91319.

Input-Output Circuit Types

Table 1.6-1 lists the input-output circuit types of the MB91319.

Table 1.6-1 Input-Output Circuit Types of the MB91319 (1 / 6)

Classification Circuit type Remarks

A

Oscillation feedback

B

CMOS level hysteresis input with pull-up resistors

C

• CMOS level outputCMOS level hysteresis input with standby control

Clock input

Standby control

XO

X1

Digital input

Digital output

Digital output

Digital input

Standby control

17

CHAPTER 1 OVERVIEW

D

2.5 V CMOS level outputCMOS level hysteresis input with standby control

E

CMOS level outputCMOS level hysteresis input withstandby controlUse of analog input switch

F

CMOS level input without standby control



Digital input

Digital output

Digital output

2.5V

Standby control

Analog input

Digital output

Digital output

Digital input

Control

Standby control

Digital input

18

CHAPTER 1 OVERVIEW

G

CMOS level hysteresis input without standby control

H

CMOS level outputCMOS level hysteresis input with standby control and pull-down resistor

I

CMOS level outputCMOS level hysteresis input with standby control and pull-up resistor



Digital input

Digital output

Pull down control

Digital output

Digital input

Standby control

Digital output

Digital output

Digital input

Standby control

19

CHAPTER 1 OVERVIEW

J

Open-drain outputCMOS level hysteresis input withstandby control provided

K

Analog pin

L

CMOS level hysteresis input with pull-down resistor



Open-drain control

Digital output

Digital input

Standby control

Digital input

20

CHAPTER 1 OVERVIEW

M

CMOS level output

N

3 ports for I2CCMOS level hysteresis inputCMOS level outputUse of stop control



Digital output

Digital output

Digital input

Digital output

Open-drain control

Digital input

Digital input

Digital output

Open-drain control

Control

Control

Digital output

Open-drain control

21

CHAPTER 1 OVERVIEW

O

CMOS level outputCMOS level hysteresis input withoutstandby control

P

CMOS level outputCMOS level hysteresis input withoutstandby controlUse of pull-down resistor



Digital output

Digital output

Digital input

Digital output

Digital output

Digital input

22

CHAPTER 2HANDLING THE DEVICE

This chapter provides precautions on handling the MB91319 series.

2.1 Precautions on Handling the Device

23

CHAPTER 2 HANDLING THE DEVICE

2.1 Precautions on Handling the Device

This section contains information on preventing a latch up and on the handling of pins.

Preventing a Latch Up

A latch up can occur if, on a CMOS IC, a voltage higher than VCC or a voltage lower than VSS isapplied to an input or output pin or a voltage higher than the rating is applied between VCC andVSS. A latch up, if it occurs, significantly increases the power supply current and may causethermal destruction of an element. When you use a CMOS IC, be very careful not to exceed themaximum rating.

Unused Input Pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by, forexample, using a pull-up or pull-down resistor.

Power Supply Pins

If more than one VCC or VSS pin exists, those that must be kept at the same potential aredesigned to be connected to one other inside the device to prevent malfunctions such as latch up.Be sure to connect the pins to a power supply and ground external to the device to minimizeundesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase inground level, and conform to the total output current rating. Given consideration to connecting thecurrent supply source to VCC and VSS of the device at the lowest impedance possible.

It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VCCand VSS at circuit points close to the device as a bypass capacitor.

Quartz Oscillation Circuit

Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boardsso that X0, X1, the quartz oscillator (or ceramic oscillator), and the bypass capacitor to groundare located as near to one another as possible.

It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pinswith ground be used to increase the expectation of stable operation.

Please ask the crystal maker to evaluate the oscillation characteristics of the crystal and thisdevice.

Mode Pins (MD0 to MD3)

These pins must be directly connected to VCC or VSS when they are used. Keep the patternlength between a mode pin on a printed circuit board and VCC or VSS as short as possible sothat they can be connected at a low impedance.

Tool Reset Pins (TRST)

Be sure to input the same signal as the INIT, when this pin is not used for the tool. The sameprocessing is executed for the product.

24


Power-on

Immediately after power-on, be sure to apply a reset with the INIT pin to initialize the settings(INIT).

Also immediately after power-on, keep the INIT pin at the L level until the oscillator has reachedthe required frequency stability. (For initialization by INIT from the INIT pin, the oscillationstabilization wait time is set to the minimum value.)

Source Oscillation Input at Power-on

At power-on, be sure to input a source clock until the oscillation stabilization wait time is reached.

Precautions at Power-On/Power-Off

Precautions when turning on and off VDDI (internal 2.5 V power supply) and VDDE (external 3.3 V power supply)

To ensure the reliability of LSI devices, do not continuously apply only VDDE (external) whenVDDI (internal) is off.

When VDDE (external) is changed from off to on, the power noise may make it impossible toretain the internal state of the circuit.

• Power-on: VDDI (internal) → analog → VDDE (external) → signal

• Power-off: Signal → VDDE (external)→ analog → VDDI (internal)

Clocks

Notes on using external clock

When using an external clock under normal conditions, supply clock signals to X0 (X0A, X0B)pins and simultaneously supply the antiphase signals to X1 (X1A, X1B) pins. In this case,however, do not use STOP mode (oscillation stop mode) because in the STOP mode, the X1(X1A, X1B) pins stop at "H" output state. When operating at 12.5 MHz or lower frequency,however, the clock signal input is needed only to the X0 (X0A, X0B) pins.Examples of using an external clock are illustrated in Figure 2.1-1 and Figure 2.1-2.

Figure 2.1-1 Circuit Using External Clock (Normal)

Figure 2.1-2 Circuit Using External Clock (12.5 MHz or Lower)

X0, X0A, X0B

X1, X1A, X1B

MB91FV319A/MB91F318A

[STOP mode (oscillation stop mode) cannot be used.]

X0, X1A, X1B

X1, X1A, X1BOPEN MB91FV319A/MB91F318A

25


Note:

Signal delay time between the X0 (X0A, X0B) and X1 (X1A, X1B) pins must be within 15 ns (operating at 10 MHz).

Notes on using MS clock

For MSCLK, MS transfer clock signal is output externally from an internal I/O cell and thenreentered. Therefore, insert damping resistor exteriorly to reduce reflection noise that may affectthe internal circuit.

Limitations

Common of MB91319 series

Clock controller

INIT must be kept at the L level until the oscillation stabilization wait time is reached.

Bit search module

Data register for detection 0 (BSD0), data register for detection 1 (BSD1), and data register forchange point detection BSDC are word access only.

I/O port

Only byte access is permitted for ports.

Low Power Consumption Mode

To switch to standby mode, use synchronous standby mode (set by the SYNCS bit, that is bit8of the TBCR, time-base counter control register) and be sure to use the following sequence:

/* STCR write */ldi #_STCR, r0 ; STCR register (0x0481)ldi #val_of_Stby, rl ; Val_of_Stby is write data to STCRstb rl, @r0 ; Write to STCR

/* CTBR write */ldi #_CTBR, r2 ; CTBR register (0x0483)ldi #0xA5, rl ; Clear command (1)stb rl, @r2 ; Write A5 to CTBRldi #0x5A, rl ; Clear command (2)stb rl, @r2 ; Write 5A to CTBR

/* Time base counter is cleared here */ldub @r0, rl ; Read STCR

/* Synchronous standby transition start */ldub @r0, rl ; Dummy read STCRnop ; nop ×5 for timing adjustmentnopnopnopnop

When using the monitor debugger, do not:

• Set a break point within the above sequence of instructions.

• Step of the instructions within the above sequence of instructions.

26


Prefetch

When allowing prefetch in the little endian area, only word access (in 32-bit word) should beused to access the area.

Byte access and half-word access are not working properly.

Notes on using PS register

PS register is processed by some instructions in advance so that exception operations asstated below may cause breaks during interruption handling routine when using debugger,and may cause updates to the display contents of PS flags.

In either case, this device is designed to carry out reprocessing properly after returning fromsuch EIT events. The operations before and after the events are performed as prescribed inthe specification.

1. The following operations may be performed (c) if an instruction immediately before a dataevent or a DIVOU/DIVOS emulator menu instruction (a) receives a user interrupt/NMI, or (b)breaks during stepping.

• D0 and D1 flags are updated in advance.

• EIT handling routine (user interrupt/NMI, or emulator) is executed.

• After returning from the EIT, a DIVOU/DIVOS instruction is executed and the D0 and D1flags are updated to the same values as in (1).

2. The following operations are performed if each instruction from ORCCR, STILM, MOV Ri andPS is executed to allow an interruption while user interrupt/NMI trigger exists.

• PS register is updated in advance.

• EIT handling routine (user interrupt/NMI) is executed.

• After returning from the EIT, the above instructions are executed and the PS register isupdated to the same value as in (1).

Watchdog Timer Function

The watchdog timer equipped in this model operates to monitor programs to ensure that theyexecute reset defer function within a certain period of time, and to reset the CPU if the resetdefer function is not executed due to the program runaway. For that reason, once thewatchdog timer function is enabled, it keeps its operation until it is reset.

By way of exception, the watchdog timer automatically defers a reset under the conditionwhere the CPU program executions are stopped. For more detail, refer to the descriptionsection of the watchdog timer function.

If the system gets out of control and the situation becomes as mentioned above, watchdogreset may not be generated. In that case, please reset (INIT) from the external INIT pin.

Note on using A/D

Nevertheless the MB91319 series contains an A/D converter, be sure not to apply the higherpower supply than VCC to the AVCC.

About Software Reset of Synchronous Mode

To use the software reset of synchronous mode, be sure to meet the following 2 conditions.

• Set interrupt enable flag (I-Flag) to "disabled" (I-Flag= 0)

• Do not use NMl

27


Unique characteristic of the evaluation chip MB91FV319A/R

Simultaneous occurrences of software break and user interrupt/NMI (MB91FV319A/R only)

If software break and user interrupt/NMI occur together, emulator debugger may:

• Stop at a point other than the programmed break points.

• Not reexecute properly after halting.

If such failures occur, use hardware break instead of software break. When using monitordebugger, do not set any break points within the corresponding instructions.

Stepping of the RETI Instruction

In the environment where interruptions occur frequently during stepping, the RETI is executedrepeatedly for the corresponding interrupt process routines after the stepping. As the result ofit, the main routine and low-interrupt-level programs are not executed. To avoid this situation,do not step the RETI instruction. Otherwise, perform debugging by disabling the interruptionswhen the debug on the corresponding interrupt routines becomes unnecessary.

Operand Break

Do not set the access to the areas containing the address of stack pointer as a target of dataevent break.

Sample Batch File for Configuration

When a program is downloaded to internal RAM to execute debug, be sure to execute thefollowing batch file after RESET.#-------------------------------------------------------------------------------# Set MODR (0x7fd) = Enable In memory + 16bit External Busset mem/byte 0x7fd=0x5#-------------------------------------------------------------------------------

28

CHAPTER 3CPU AND CONTROL UNITS

This chapter provides basic information required to understand the functions of the MB91319 series. It covers architecture, specifications, and instructions.

3.1 Memory Space

3.2 Internal Architecture

3.3 Programming Model

3.4 Data Configuration

3.5 Word Alignment

3.6 Memory Map

3.7 Branch Instructions

3.8 EIT (Exception, Interrupt, and Trap)

3.9 Operating Modes

3.10 Reset (Device Initialization)

3.11 Clock Generation Control

3.12 Device State Control

3.13 Watch Timer

3.14 Main Clock Oscillation Stabilization Wait Timer

29

CHAPTER 3 CPU AND CONTROL UNITS

3.1 Memory Space

The MB91319 has a logical address space of 4 GB (232 addresses), which the CPU accesses linearly.

Memory Space

The MB91319 has a logical address space of 4GB (232 addresses), while the CPU accesslineally.

Direct addressing area

The areas in the address space listed below are used for input-output.These areas called the direct addressing area. The address of an operand can be directlyspecified in an instruction.The size of the direct addressing area varies according to the size of data to be accessed:• Byte data access : 000H to 0FFH

• Half word data access : 000H to 1FFH

• Word data access : 000H to 3FFH

Memory Map

Figure 3.1-1 shows the memory space of this product.

Figure 3.1-1 Memory Map

Program

Font


Refer to I/O map

Single-chip mode

0000 0000H

0000 0400H

0001 0000H

0003 0000H

0002 F800H

0004 0000H

0005 0000H

0006 0000H

0007 0000H

0008 0000H

0018 0000H

0020 0000H

FFFF FFFFH

512KB *3

*1: Internal RAM area of MB91F318A/S and MB91FV319R becomes 0003 4000H to 0003 FFFFH.

*2: For the MB91316, MASK ROM 512KB is used (0008 0000H to 000F FFFFH).

I/O

I/O

FlashROM1

FlashROM2

USB-FUNC

OSDC

Access disabled

Access disabledAccess disabled

Font RAM

Access disabled

Internal RAM *1

1MB *2

Internal RAM area of MB91316 becomes 0003 8000H to 0003 FFFFH.

*3: For the MB91F318A/S, MB91316, MASK ROM 384KB is used (0008 0000H to 0019 7FFFH).

30


3.2 Internal Architecture

The MB91319 CPU is a high-performance core that is designed based on a RISC architecture with high-level function instructions for embedded applications.

Features

RISC architecture used

Basic instruction: One instruction per cycle

32-bit architecture

General-purpose register: 32 bits × 16

4 GB linear memory space

Multiplier installed

• 32-bit by 32-bit multiplication: 5 cycles

• 16-bit by 16-bit multiplication: 3 cycles

Enhanced interrupt processing function

• Quick response speed: 6 cycles

• Support of multiple interrupts

• Level mask function: 16 levels

Enhanced instructions for I/O operations

• Memory-to-memory transfer instruction

• Bit-processing instructions

Efficient code

Basic instruction word length: 16 bits

Low-power consumption

Sleep and stop modes

Gear function

31


Internal Architecture

The FR CPU uses the Harvard architecture, in which the instruction bus and data buses areindependent of each other.

A 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interfacebetween the CPU and peripheral resources. A Harvard ↔ Princeton bus converter is connectedto the I-bus and D-bus to provide an interface between the CPU and the bus controller.

Figure 3.2-1 shows connections in the internal architecture.

Figure 3.2-1 Internal Architecture

32

32

32

32

32

32

16

24

16

FRex CPU

D-bus I-bus

32 bits

16 bits

DataRAM

Princeton bus

converter

Harvard

F-bus

Bus converter

Peripheral resources Bus controllersInternal I/O

R-bus

I address

D address

Address

Data

D data

I data

External address

External data

32


CPU

The CPU is a compact implementation of the 32-bit RISC FR architecture.

Five instruction pipe lines are used to execute one instruction per cycle. A pipeline consists of thefollowing stages:

• Instruction fetch (IF): Outputs an instruction address to fetch an instruction.

• Instruction decode (ID): Decodes a fetched instruction. Also reads a register.

• Execution (EX): Executes an arithmetic operation.

• Memory access (MA): Performs a load or store access to memory.

• Write-back (WB): Writes an operation result (or loaded memory data) to a register.

Figure 3.2-2 Instruction Pipelines

Instructions are never executed randomly. If Instruction A enters a pipeline before Instruction B, italways reaches the write-back stage before Instruction B.

In general, one instruction is executed per cycle. However, multiple cycles are required toexecute a load/store instruction with a memory wait, a branch instruction without a delay slot, or amultiple-cycle instruction. The execution of instructions slows down if the instructions are notsupplied fast enough.

32-bit/16-bit bus converter

The 32-bit/16-bit bus converter provides an interface between the F-bus accessed with 32-bitwidth and the R-bus accessed with 16-bit width and enables data access from the CPU to built-inperipheral circuits.

If the CPU performs a 32-bit width access to the R bus, this bus converter converts the accessinto two 16-bit width accesses. Some of the built-in peripheral circuits have limitations on theaccess bus width.

Harvard/Princeton bus converter

The Harvard/Princeton bus converter coordinates instruction and data accesses of the CPU toprovide a smooth interface between it and external buses.

The CPU has a Harvard architecture with separate buses for instructions and data. On the otherhand, the bus controller that performs control of external buses has a Princeton architecture witha single bus. The Harvard/Princeton bus converter assigns priorities to instruction and dataaccesses from the CPU to control accesses to the bus controller. This function allows the order ofexternal bus accesses to be permanently optimized.

Instruction 1

Instruction 2

Instruction 3

Instruction 4

Instruction 5

Instruction 6

CLK

WBIF ID EX MA

IF ID EX MA WB

ID EX MA WB

EX MA WB

MA WB

WB

33


Overview of Instructions

The FR supports the general RISC instruction set as well as logical operation, bit manipulation,and direct addressing instructions optimized for embedded applications. For the instruction set,see "APPENDIX I Instruction Lists". Each instruction is 16-bit long (except for some instructionsare 32- or 48-bit long), resulting in superior efficiency of memory use.

An instruction set is classified into the following function groups:

• Arithmetic operation

• Load and store

• Branch

• Logical operation and bit manipulation

• Direct addressing

• Other

Arithmetic operation

Arithmetic operation instructions include standard arithmetic operation instructions (addition,subtraction, and comparison) and shift instructions (logical shift and arithmetic shift). The additionand subtraction instructions include an operation with carries for use with multiple-word-lengthoperations and an operation that does not change flag values, a convenience in addresscalculations.

Furthermore, 32-bit-by-32-bit and 16-bit-by-16-bit multiplication instructions and a 32-bit-by-32-bitstep division instruction are provided.

Additionally, an immediate data transfer instruction that sets immediate data in a register and aregister-to-register transfer instruction are provided.

An arithmetic operation instruction is executed using the general-purpose registers and themultiplication and division registers in the CPU.

Load and store

Load and store instructions read and write to external memory. They are also used to read andwrite to a peripheral circuit (I/O) on the chip.

Load and store instructions have three access lengths: byte, halfword, and word. In addition toindirect memory addressing via general registers, indirect memory addressing via registers withdisplacements and via registers with register incrementing or decrementing are provided for someinstructions.

Branch

The branch group includes branch, call, interrupt, and return instructions. Some branchinstructions have delay slots while others do not. These may be optimized according to theapplication. The branch instructions are described in detail later.

Logical operation and bit manipulation

Logical operation instructions perform the AND, OR, and EOR logical operations betweengeneral-purpose registers or a general-purpose register and memory (and I/O). Bit manipulationinstructions directly manipulate the contents of memory (and I/O). They access memory usinggeneral register indirect addressing.

34


Direct addressing

Direct addressing instructions are used for access between an I/O and a general-purpose registeror between an I/O and the memory. High-speed and high-efficiency access can be achievedsince an I/O address is directly specified in an instruction instead of using register indirectaddressing. Indirect memory addressing via registers with register incrementing or decrementingare provided for some instructions.

Other types of instructions

Other types of instructions include instructions that provide flag setting, stack manipulation, sign/zero extension, and other functions in the PS register. Also, function entry and exit instructionsthat support high-level languages and register multi-load/store instructions are provided.

35


3.3 Programming Model

This section explains the programming model in detail.

Basic Programming Model

Figure 3.3-1 Basic Programming Model

32 bits

[Initial value]

R0

XXXX XXXX H

R1

General-purpose register

R12

R13 A

C

R14 F

P

XXXX XXXX H

R15 S

P

0000 0000 H

Program counter PC

Program status PS ILM SCR CCR

Table base register TBR

Return pointer RP

System stack pointer SSP

User stack pointer USP

Multiply and divide registers MDH MDL

36


Registers

General-purpose registers

Figure 3.3-2 General-Purpose Registers

Registers R0 to R15 are general-purpose registers. They are used as the accumulator for variousoperations and pointers for memory access.

Of these 16 registers, the following registers are intended for special applications and thereforeenhanced instructions are provided for them:

R13: Virtual accumulator

R14: Frame pointer

R15: Stack pointer

The initial value after reset is not defined for R0 though R14 and is 00000000H (SSP value) forR15.

Program status (PS)

The program status (PS) register holds the program status and consists of three parts: ILM, SCR,and CCR.

In the figure, all the undefined bits are reserved. During reading, 0 is always read.

This register cannot be written.

[Initial value]

R0 XXXX XXXX H

R1

R12

R13 A C

R14 F P XXXX XXXX H

R15 S P 0000 0000 H

32 bits

Bit location 31 20 16 10 8 7 0

ILM SCR CCR

37


Condition code register (CCR)

[bit5] Stack flag

Specifies the stack pointer to be used as R15.

Reset clears this bit to 0.

Set this bit to 0 when executing a RETI instruction.

[bit4] Interrupt enable flag

Enable or disable a user interrupt request.


[bit3] Negative flag

Indicate the sign when the operation result is regarded as an integer represented by its 2'scomplement.

The initial value after reset is undefined.

[bit2] Zero flag

Indicate whether the operation result is 0.


7 6 5 4 3 2 1 0

- - S I N Z V C --00XXXX B

[Initial value]

Value Description

0The system stack pointer (SSP) is used as R15.When an EIT occurs, this bit is automatically set to 0.(Note that the value saved on the stack is the value before it is cleared.)

1 The user stack pointer (USP) is used as R15.

Value Description

0User interrupt disabled.When the INT instruction is executed, this bit is cleared to 0.(Note that the value saved on the stack is the value before it is cleared.)

1User interrupt enabled.The mask processing of a user interrupt request is controlled by the value held in ILM.

Value Description

0 Indicates that the operation result is a positive value.

1 Indicates that the operation result is a negative value.

Value Description

0 Indicates that the operation result is not 0.

1 Indicates that the operation result is 0.

38


[bit1] Overflow flag

Indicate whether an overflow has occurred as a result of the operation when the operand isregarded as an integer represented by its 2's complement.


[bit0] Carry flag

Indicate whether a carry or a borrow has occurred from the most significant bit in theoperation.


System condition code register (SCR)

[bit10, bit9] Step division flag

Hold the intermediate data when step division is executed.

Do not change these bits during step division.

To execute other processing during a step division, save and restore the value of the PSregister to ensure that the step division is restarted.


When the DIVOS instruction is executed, the multiplicand and divisor are accessed and thisflag is set.

When the DIV0U instruction is executed, this flag is cleared.

[bit8] Step trace trap flag

This bit specifies whether the step trace trap is to be enabled.


The step trace trap function is also used by emulators. When being used by an emulator, thisfunction cannot be used in a user program.

Value Description

0 Indicates that the operation did not cause an overflow.

1 Indicates that the operation caused an overflow.

Value Description

0 Indicates that no carry or borrow has occurred.

1 Indicates that a carry or borrow has occurred.

10 9 8 [Initial value]

D1 D0 T XX0B

Value Description

0 The step trace trap is disabled.

1The step trace trap is enabled.All user NMIs and user interrupts are prohibited.

39


ILM

The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILMis used as a level mask.

An interrupt request to the CPU is accepted only when its interrupt level is higher than the levelindicated in this ILM.

The highest level is 0 (00000B), and the lowest level is 31 (11111B).

The program setting range is limited.

• When the original value is between 16 and 31:A new value between 16 and 31 can be set. If an instruction that sets a value between 0 and15 is executed, the specified value plus 16 is transferred.

• When the original value is between 0 and 15:Any value between 0 and 31 can be set.

Reset initializes this bit to 15 (01111B).

Program counter (PC)

[bit31 to bit0]

These are the bits of the program counter that indicates the address of the instruction beingexecuted.

Bit0 is set to 0 when the PC is updated after an instruction is executed. Bit0 can become 1only if the branch address is an odd number address.

However, even if the branch address is an odd number address, bit0 is invalid and thereforethe instruction should be placed at an even number address.


Table base register (TBR)

The table base register holds the first address of the vector table to be used during EITprocessing.

The initial value after reset is 000FFC00H.

20 19 18 17 16 [Initial value]

ILM4 ILM3 ILM2 ILM1 ILM0 01111B

PC XXXXXXXXH

31 0 [Initial value]

TBR 000FFC00H


40


Return pointer (RP)

The return pointer holds the address returned from a subroutine.

When a CALL instruction is executed, the PC value is transferred to this RP.

When a RET instruction is executed, the RP contents are transferred to PC.


System stack pointer (SSP)

SSP is the system stack pointer.

SSP functions as R15 when the S flag is 0.

SSP can also be specified explicitly.

This register is also used as a stack pointer that specifies the stack on which the PS and PCcontents are to be saved if an EIT occurs.

The initial value after reset is 00000000H.

User stack pointer (USP)

USP is the user stack pointer

USP functions as R15 when the S flag is 1.

USP can also be specified explicitly.


This register cannot be used by the RETI instruction.

RP XXXXXXXXH


SSP 00000000H


USP XXXXXXXXH


41


Multiply and divide register

The multiply and divide registers are 32-bit long.


When multiplication is executed

For a 32-bit-by-32-bit multiplication, the 64-bit long operation result is stored in the multiplyand divide registers as follows:

MDH: High-order 32 bits

MDL: Low-order 32 bitsFor a 16-bit-by-16-bit multiplication, the result is stored as follows:

MDH: Undefined

MDL: 32-bit result

When division is executed

At the start of calculation, the dividend is stored in MDL.

If a DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction is executed for a division, the resultis stored in MDL and MDH as follows:

MDH: Remainder

MDL: Quotient

MDHMDL

31 0

42


3.4 Data Configuration

The MB91319 uses the following two data ordering methods:• Bit ordering• Byte ordering• Bit ordering

Bit Ordering

Use the little endian method for bit ordering.

Byte Ordering

Use the big endian method for byte ordering.

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSBMSB

MSB LSBMemory bit 31 23 15 7 0

bit7 0

10101010 11001100 11111111 00010001

10101010Address n

Address (n+1)

Address (n+2)

Address (n+3)

11001100

11111111

00010001

43


3.5 Word Alignment

Since instructions and data are accessed in byte units, the addresses at which they are placed depend on the instruction length or the data width.

Program Access

A program must be placed at an address that is a multiple of 2.

Bit0 of the PC is set to 0 if the PC is updated when an instruction is executed.

Bit0 can be set to 1 only if an odd-number address is specified as the branch address.

If bit0 is set to 1, however, bit0 is invalid and an instruction must be placed at the address that isa multiple of 2.

No odd-number address exception exists.

Data Access

If data is accessed, forced alignment is applied to the address based on the width.

Word access: An address must be a multiple of 4. (The lowest-order 2 bits are forcibly setto 00.)

Halfword access: An address must be a multiple of 2. (The lowest-order bit is forcibly set to0.)

Byte access: -

During word or halfword data access, some of the bits in the result of calculating an effectiveaddress are forcibly set to 0. For example, in @(R13, Ri) addressing mode, the register beforeaddition is used without change in the calculation (even if the lowest-order bit is 1) and the low-order bits are masked. A register before calculation is not masked.

[Example] LD @(R13, R2), R0

R13 00002222H

R2 00000003H

Addition result 00002225H

Lower 2 bits forcibly masked

Address pin 00002224H

+)

44


3.6 Memory Map

This section shows the memory map for the MB91319.

Memory Map

The address space is 32 bits linear.

Figure 3.6-1 Memory Map


The following areas in the address space are the areas for I/O. When direct addressing is used inthese areas, an operand address can be directly specified in an instruction.

The size of an address area for which an address can be directly specified varies is determinedby the data length as follows:

• Byte data (8 bits): 000H to 0FFH

• Halfword data (16 bits): 000H to 1FFH

• Word data (32 bits): 000H to 3FFH

Vector table initial area

The area from 000FFC00H to 000FFFFFH is the initial EIT vector table area.

You can place the vector table that will be used during EIT processing at any address by rewritingthe TBR. Initialization by a reset places the table at this address.

0000 0000H

0000 0100H

0000 0200H

0000 0400H

000F FC00H

000F FFFFH

Byte data

Direct addressing areaHalfword data

Word data

Vector table initial area

FFFF FFFFH

45


3.7 Branch Instructions

An operation with or without a delay slot can be specified for a branch instruction used in the MB91319.

Branch Instruction with Delay Slot

Instructions written as follows perform a branch operation with a delay slot:

Operation Explanation

In operation with a delay slot, the instruction located just after a branch instruction (placed in a"delay slot") is executed before the instruction that branches is executed.

Since an instruction in the delay slot is executed before the branch operation, the apparentexecution speed is one cycle. However, a NOP instruction must be placed in the delay slot ifthere is no valid instruction put there.

[Example]

If a conditional branch instruction is used, an instruction placed in the delay slot is executedwhether or not the condition for branching is met.

If a delay branch instruction is used, the order of execution for some instructions seems to bereversed. However, this occurs only for updating the PC and the instructions are executed in thespecified order for other operations (register update and reference, etc.)

The following is a concrete example.

Ri referenced by the JMP:D @Ri / CALL:D @Ri instruction is not affected even though Ri isupdated by the instruction in the delay slot.

JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D

BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9

BC:D label9 BNC:D label9 BN:D label9 BP:D label9

BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9

BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9

; List of instructions

ADD R1, R2, ;

BRA:D LABEL ; Branch instruction

MOV R2, R3, ; Delay slot ... Executed before branch

...

LABEL: ST R3, @R4 ; Branch destination

46


[Example]

RP referenced by the RET:D instruction is not affected even though RP is updated by theinstruction in the delay slot.

[Example]

The flag referenced by the Bcc:D rel instruction is not affected by the instruction in the delay slot.

[Example]

If RP is referenced by an instruction in the delay slot of the CALL:D instruction, the data that hasbeen updated by the CALL:D instruction is read.

[Example]

Instructions that can be placed in the delay slot

Only an instruction meeting the following conditions can be executed in the delay slot.

• One-cycle instruction

• Instruction other than a branch instruction

• Instruction whose operation is not affected even though the order is changed

A one-cycle instruction is an instruction denoted in the Number of Cycles column in the list ofinstructions as 1, a, b, c, and d.

LDI:32 #Label, R0

JMP:D @R0 ; Branch to Label

LDI:8 #0, R0 ; No effect on the branch destination address

...

RET:D ; Branch to address defined beforehand in RP

MOV R8, RP ; No effect on the return operation

...

ADD #1, R0 ; Flag change

BC:D Overflow ; Branch to execution result of above instruction

ANDCCR #0 ; This flag update is not referenced by the above branch instruction.

...

CALL:D Label ; Updating RP and branching

MOV RP, R0 ; Transferring RP, execution result of above CALL:D

...

47


Step trace trap

A step trace trap does not occur between the execution of a branch instruction with a delay slotand the delay slot.

Interrupt NMI

An interrupt NMI is not accepted between the execution of a branch instruction with a delay slotand the delay slot.

Undefined instruction exception

An undefined instruction exception does not occur if there is an undefined instruction in the delayslot. If an undefined instruction is in the delay slot, it operates as a NOP instruction.

Branch Instruction without Delay Slot

Instructions written as follows perform a branch operation without a delay slot:

Operation Explanation

In operation without a delay slot, instructions are executed in the order in which they arespecified. An instruction immediately following a branch is never executed before it.

[Example]

A branch instruction without a delay slot is executed in two cycles if a branch occurs and in onecycle if no branch occurs.

Since no appropriate instruction can be placed in the delay slot, this instruction results in a moreefficient instruction code than a branch instruction with a delay slot and with NOP specified.

For both optimal execution speed and code efficiency, select an operation with a delay slot if avalid instruction can be placed in the delay slot; otherwise, select an operation without a delayslot.

JMP @Ri CALL label12 CALL @Ri RET

BRA label9 BNO label9 BEQ label9 BNE label9

BC label9 BNC label9 BN label9 BP label9

BV label9 BNV label9 BLT label9 BGE label9

BLE label9 BGT label9 BLS label9 BHI label9

; List of instructions

ADD R1, R2, ;

BRA LABEL ; Branch instruction (without a delay slot)

MOV R2, R3, ; Not executed

...

LABEL: ST R3, @R4 ; Branch destination

48


3.8 EIT (Exception, Interrupt, and Trap)

EIT, a generic term for exception, interrupt, and trap, refers to suspending program execution if an event occurs during execution and then executing another program.

EIT (Exception, Interrupt, and Trap)

An exception is an event that occurs related to the execution context. Execution restarts from theinstruction that caused the exception.

An interrupt is an event that occurs independently of execution context. The event is caused byhardware.

A trap is an event that occurs related to the execution context. Some traps, such as system calls,are specified in a program. Execution restarts from the instruction following the one that causedthe trap.

Features

ETI for the MB91319 has the following features:

• Multi-interrupt support

• Level masking function (15 levels available to the user)

• Trap instruction (INT)

• Emulator activation EIT (hardware/software)

EIT Causes

The following are causes of EIT:

• Reset

• User interrupt (internal resource, external interrupt)

• NMI

• Delayed interrupt

• Undefined instruction exception

• Trap instruction (INT)

• Trap instruction (INTE)

• Step trace trap

• No-coprocessor trap

• Coprocessor error trap

Return from EIT

• RETI instruction.

49


3.8.1 EIT Interrupt Levels

The interrupt levels are 0 to 31 and are managed with five bits.

Interrupt Levels

Table 3.8-1 shows the allocation of the levels.

Operation is possible for levels 16 to 31.

The interrupt level does not affect an undefined instruction exception, no-coprocessor trap,coprocessor error trap, or an INT instruction. It does not change the ILM, either.

I Flag

A flag that specifies whether an interrupt is permitted or prohibited. This flag is provided as bit4 ofthe PS register.

Table 3.8-1 EIT Interrupt Levels

Level

Binary Decimal

00000......

00011

00100

00101......

01110

0......3

4

5......14

(Reserved for system)......(Reserved for system)

(Reserved for system)......(Reserved for system)

If the original ILM value is between 16 and 31, a program cannot set a value in this ILM range.

01111 15 NMI (for user)

1000010001

...

...1111011111

1617......3031

InterruptInterrupt......Interrupt-

User interrupts prohibited if ILM is set

Interrupts prohibited if ICR is set

INTE instructionStep trace trap

Value Description

0Interrupts prohibitedCleared to 0 if the INT instruction is executed.(Note that a value saved on the stack is the value before it is cleared.)

1Interrupts permittedThe mask processing of an interrupt request is controlled by the value in the ILM register.

50


Interrupt Level Mask (ILM) Register

A PS register (bit20 to bit16) that holds an interrupt level mask value.

The CPU accepts only an interrupt request sent to it with an interrupt level higher than the levelindicated by the ILM.

The highest level is 0 (00000B) and the lowest level is 31 (11111B).

Values that can be set by a program have a limit. If the original value is between 16 and 31, thenew value must be between 16 and 31. If an instruction that sets a value between 0 and 15 isexecuted, the specified value plus 16 is transferred.

If the original value is between 0 and 15, any value between 0 and 31 may be set.

Note:

Use the STILM instruction to set this register.

Level Mask for Interrupt and NMI

If an NMI or interrupt request occurs, the interrupt level (Table 3.8-1) of the interrupt source iscompared with the level mask value held in the ILM. A request meeting the following condition ismasked and is not accepted:

Interrupt level of cause ≥ Level mask value

51


3.8.2 Interrupt Control Unit (ICR)

The interrupt control register (ICR: Interrupt Control Register), located in the interrupt controller, sets the level of an interrupt request. An ICR is provided for each of the interrupt request inputs. The ICR is mapped on the I/O space and is accessed from the CPU through a bus.

Configuration of Interrupt Control Register (ICR)

[bit4] ICR4

ICR4 is always set to 1.

[bit3 to bit0] ICR3 to 0

These bits are the low-order 4 bits of the interrupt level of the corresponding interrupt source.They can be read and written to.

Together with bit4, a value between 16 and 31 can be set in the ICR.

Mapping of Interrupt Control Register (ICR)

7 6 5 4 3 2 1 0

R R/W R/W R/W R/W

- - - ICR4 ICR3 ICR2 ICR1 ICR0 Initial value ---11111B

Table 3.8-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors

Interrupt source

Interrupt control register

Corresponding interrupt vector

NumberAddress

Hexadecimal Decimal

IRQ00 ICR00 00000440H 10H 16 TBR + 3BCH

IRQ01 ICR01 00000441H 11H 17 TBR + 3B8H

IRQ02 ICR02 00000442H 12H 18 TBR + 3B4H

...

.........

...

.........

...

.........

IRQ45 ICR45 0000046DH 3DH 61 TBR + 308H

IRQ46 ICR46 0000046EH 3EH 62 TBR + 304H

IRQ47 ICR47 0000046FH 3FH 63 TBR + 300H

Note: See "CHAPTER 9 INTERRUPT CONTROLLER".

52


3.8.3 System Stack Pointer (SSP)

The system stack pointer (SSP) is used to point to the stack to save and restore data when EIT is accepted or a return operation occurs.

System Stack Pointer (SSP)

Eight is subtracted from the register value during EIT processing and eight is added to theregister value during the return operation from EIT that occurs when the RETI instruction isexecuted.

The system stack pointer (SSP) is initialized to 00000000H by a reset.

The SSP is also used as general-purpose register R15 if the S flag in the CCR is set to 0.

Interrupt Stack

The value in the PC or PS is saved to or restored from the area indicated by SSP. After aninterrupt occurs, the PC contents are stored at the address indicated by SSP and the PS contentsare stored at the address indicated by SSP plus 4.

Figure 3.8-1 Interrupt Stack

SSP 00000000H

bit 31 0 [Initial value]

[Example] [Before interrupt] [After interrupt]

SSP 80000000H SSP 7FFFFFF8H

Memory

80000000H 80000000H

7FFFFFFCH 7FFFFFFCH PS7FFFFFF8H 7FFFFFF8H PC

53


3.8.4 Table Base Register (TBR)

Indicate the beginning address of the vector table for EIT.

Table Base Register (TBR)

The table base register (TBR) consists of 32 bits as shown below:

Obtain a vector address by adding to the TBR the offset value predetermined for an EIT cause.

The table base register (TBR) is initialized to 000FFC00H by a reset.

EIT Vector Table

A 1 KB area from the address indicated in the table base register (TBR) is the vector area for EIT.

The size for each vector is 4 bytes. The relationship between a vector number and a vectoraddress can be expressed as follows:

vctadr = TBR + vctofs

= TBR + (3FCH - 4 × vct)

vctadr: Vector address

vctofs: Vector offset

vct: Vector number

The low-order two bits of the addition result are always handled as 00.

The area from 000FFC00H to 000FFFFFH is the initial area for the vector table upon reset.

Special functions are allocated to some of the vectors.

Table 3.8-3 shows the vector table on the architecture.

TBR 000FFC00H

bit 31 0 [Initial value]

54


Table 3.8-3 Vector Table (1 / 3)

Interrupt sourceInterrupt number

Interrupt level OffsetDefault

address of TBRDecimal Hexadecimal

Reset *1 0 00 - 3FCH 000FFFFCH

Mode vector *1 1 01 - 3F8H 000FFFF8H

Reserved for system 2 02 - 3F4H 000FFFF4H

Reserved for system 3 03 - 3F0H 000FFFF0H

Reserved for system 4 04 - 3ECH 000FFFECH

Reserved for system 5 05 - 3E8H 000FFFE8H

Reserved for system 6 06 - 3E4H 000FFFE4H

No-coprocessor trap 7 07 - 3E0H 000FFFE0H

Coprocessor error trap 8 08 - 3DCH 000FFFDCH

INTE instruction 9 09 - 3D8H 000FFFD8H

Instruction break exception 10 0A - 3D4H 000FFFD4H

Operand break trap 11 0B - 3D0H 000FFFD0H

Step trace trap 12 0C - 3CCH 000FFFCCH

NMI request (tool) 13 0D - 3C8H 000FFFC8H

Undefined instruction exception 14 0E - 3C4H 000FFFC4H

NMI request 15 0F Fixed to 15(FH) 3C0H 000FFFC0H

External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH

External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H



External Interrupt 4 20 14 ICR04 3ACH 000FFFACH

External Interrupt 5 21 15 ICR05 3A8H 000FFFA8H



Reload Timer 0 24 18 ICR08 39CH 000FFF9CH

Reload Timer 1 25 19 ICR09 398H 000FFF98H

Reload Timer 2 26 1A ICR10 394H 000FFF94H

Maskable interrupt source *2 27 1B ICR11 390H 000FFF90H

Maskable interrupt source *2 28 1C ICR12 38CH 000FFF8CH

55


Maskable interrupt source *2 29 1D ICR13 388H 000FFF88H

Maskable interrupt source *2 30 1E ICR14 384H 000FFF84H

Maskable interrupt source *2 31 1F ICR15 380H 000FFF80H

Maskable interrupt source *2 32 20 ICR16 37CH 000FFF7CH

Maskable interrupt source *2 33 21 ICR17 378H 000FFF78H









Maskable interrupt source *2 42 2A ICR26 354H 000FFF54H





Time base timer overflow 47 2F ICR31 340H 000FFF40H











Maskable interrupt source *2 58 3A ICR42 314H 000FFF14H





56


*1: Even though the TBR value is changed, the reset vector and the mode vector are always fixedaddresses. 000FFFFCH and 000FFFF8H are used.

*2: The maskable interrupt source is defined for each model.For the vector table, see "APPENDIX B Interrupt Vector".





Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H

Reserved for system (used in REALOS) 64 40 - 2FCH 000FFEFCH

Reserved for system (used in REALOS) 65 41 - 2F8H 000FFEF8H

Reserved for system 66 42 - 2F4H 000FFEF4H

Reserved for system 67 43 - 2F0H 000FFEF0H

Reserved for system 68 44 - 2ECH 000FFEECH

Reserved for system 69 45 - 2E8H 000FFEE8H



Reserved for system 72 48 - 2DCH 000FFEDCH

Reserved for system 73 49 - 2D8H 000FFED8H

Reserved for system 74 4A - 2D4H 000FFED4H

Reserved for system 75 4B - 2D0H 000FFED0H

Reserved for system 76 4C - 2CCH 000FFECCH

Reserved for system 77 4D - 2C8H 000FFEC8H

Reserved for system 78 4E - 2C4H 000FFEC4H

Reserved for system 79 4F - 2C0H 000FFEC0H

Used in INT instruction80:

255

50:

FF-

2BCH:

000H

000FFEBCH:

000FFC00H





57


3.8.5 Multiple EIT Processing

If multiple EIT causes occur at the same time, the CPU repeats the operation of selecting and accepting one of the EIT causes, executing the EIT sequence, and then detecting EIT causes again. If there are no more EIT causes be accepted while the CPU is detecting EIT causes, the CPU executes the handler instruction of the last accepted EIT cause. As a result, the order of executing handlers for multiple EIT causes that occur at the same time is determined according to the following two elements:• Priority of EIT causes to be accepted• How other causes can be masked when one cause is accepted

Priority of EIT Causes To Be Accepted

The priority of EIT causes to be accepted is the order of causes for which the EIT sequence is tobe executed (that is, saving the PS and PC, updating the PC, and masking other causes, ifrequired). The handler of a cause accepted earlier is not necessarily executed earlier.

Table 3.8-4 lists the acceptance priority of EIT causes.

*: The priority is 6 only if the INTE instruction and the NMI for emulators occur at the same time. (The NMI for emulators is used for breaks due to data access).

Table 3.8-4 Priority of EIT Causes to Be Accepted and Masking of Other Causes

Priority of acceptance

Cause Masking of other causes

1 Reset Other causes are abandoned.

2 Undefined instruction exception Canceled

3 INT instruction I flag=0

4 No-coprocessor trap Coprocessor error trap

5 User interrupt ILM=level of cause accepted

6 NMI (for users) ILM=15

7 (INTE instruction) ILM=4 *

8 NMI (for emulators) ILM=4

9 Step trace trap ILM=4

10 INTE instruction ILM=4

58


In consideration of masking other causes after an EIT cause is accepted, the handlers of EITcauses that occur at the same time are executed in the order shown in Table 3.8-5.

Figure 3.8-2 Multiple EIT Processing

Table 3.8-5 Order of Executing EIT Handlers

Order of executing handlers

Cause

1 Reset *1

2 Undefined instruction exception

3 Step trace trap *2

4 INTE instruction *2

5 NMI (for users)

6 INT instruction

7 User interrupt

8 No-coprocessor trap, coprocessor error trap

*1: Other causes are abandoned.*2: If the INTE instruction is executed in steps, only a step trace trap EIT occurs. An INTE

cause is ignored.

[Example]

(High) NMI occurring

Priority

(Low) INT instruction executed

(2) Executed next

(1) Executed first

INT instruction handler

NMI handler

Main routine

59


3.8.6 EIT Operations

This section describes EIT operations.

EIT Operations

In the following, it is assumed that the destination source PC indicates the address of theinstruction that detected an EIT cause.

In addition, "address of the next instruction" means that the instruction that detected EIT is asfollows:

• If LDI is 32: PC + 6

• If LDI is 20 and COPOP, COPLD, COPST, and COPSV are used: PC + 4

• Other instructions: PC + 2

Operation of User Interrupt/NMI

If an interrupt request for a user interrupt or a user NMI occurs, whether the request can beaccepted is determined with the following procedure:

1. Compare the interrupt levels of requests that have occurred simultaneously and select therequest with the highest level (the smallest value). As levels to be compared, the value held inthe corresponding ICR is used for a maskable interrupt and a predetermined constant is usedfor an NMI.

2. If multiple interrupt requests with the same level occur, select the interrupt request with thesmallest interrupt number.

3. Mask and do no accept an interrupt request with an interrupt level greater than or equal to thelevel mask value. Go to Step 4. if the interrupt level is less than the level mask value.

4. Mask and do not accept the selected interrupt request if it is maskable and the I flag is set to0. Go to Step 5. if the I flag is 1. If the selected interrupt request is an NMI, go to Step 5)regardless of the I flag value.

5. If the above conditions are met, the interrupt request is accepted at a break in the instructionprocessing.

If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU operatesas follows, using an interrupt number corresponding to the accepted interrupt request.Parentheses in [Operation] show an address indicated by the register.

[Operation]

1. SSP-4 → SSP

2. PS → (SSP)

3. SSP-4 → SSP

4. Address of next instruction → (SSP)

5. Interrupt level of accepted request → ILM

6. "0" → S flag

7. (TBR + Vector offset of accepted interrupt request) → PC

60


If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU operatesas follows, using an interrupt number corresponding to the accepted interrupt request.Parentheses show an address indicated by the register.

Operation of INT Instruction

INT #u8

A branch to the interrupt handler for the vector indicated by u8 generation.

[Operation]

1. SSP-4 → SSP

2. PS → (SSP)

3. SSP-4 → SSP

4. PC + 2 → (SSP)

5. "0" → I flag

6. "0" → S flag

7. (TBR + 3FCH-4 × u8) → PC

Operation of INTE Instruction

INTE

A branch to the interrupt handler for the vector indicated by vector number #9 generation.

[Operation]

1. SSP-4 → SSP

2. PS → (SSP)

3. SSP-4 → SSP

4. PC + 2 → (SSP)

5. "00100" → ILM

6. "0" → S flag

7. (TBR+3D8H) → PC

Do not use the INTE instruction in the processing routine of the INTE instruction or a step tracetrap.

During step execution, no EIT due to INTE generation.

61


Operation of Step Trace Trap

Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break thenoccur every time an instruction is executed.

[Step trace trap detection conditions]

T flag =1

There is no delayed branch instruction.

A processing routine other than the INTE instruction or a step trace trap is in progress.

If the above conditions are met, a break occurs between instruction operations.

[Operation]

1. SSP-4 → SSP

2. PS → (SSP)

3. SSP-4 → SSP


5. "00100" → ILM

6. "0" → S flag

7. (TBR+3CCH) → PC

Set the T flag to enable the step trace trap to prohibit a user NMI and a user interrupt. No EIToccurs due to the INTE instruction.

A trap occurs in the instruction following the one in which the T flag has been set.

Operation of Undefined Instruction Exception

If, during instruction decode, an undefined instruction is detected, an undefined instructionexception occurs.

An undefined instruction exception is detected under the following conditions:

• An undefined instruction is detected during instruction decode.

• The instruction is not located in the delay slot (it does not immediately follow the delay branchinstruction).

If the above conditions are met, an undefined instruction exception and a break occur.

[Operation]

1. SSP-4 → SSP

2. PS → (SSP)

3. SSP-4 → SSP

4. PC → (SSP)

5. "0" → S flag

6. (TBR+3C4H) → PC

The PC value to be saved is the address of an instruction that detected an undefined instructionexception.

62


No-coprocessor Trap

If a coprocessor instruction using a coprocessor that is not installed is executed, a no-coprocessor trap occurs.

[Operation]

1. SSP-4 → SSP

2. PS → (SSP)

3. SSP-4 → SSP


5. "0" → S flag

6. (TBR+3E0H) → PC

Coprocessor Error Trap

If an error occurs while a coprocessor is being used and then a coprocessor instruction thatoperates on the coprocessor is executed, a coprocessor error trap occurs.

[Operation]

1. SSP-4 → SSP

2. PS → (SSP)

3. SSP-4 → SSP


5. "0" → S flag

6. (TBR+3DCH) → PC

Operation of RETI Instruction

The RETI instruction specifies return from the EIT processing routine.

[Operation]

1. (R15) → PC

2. R15+4 → R15

3. (R15) → PS

4. R15+4 → R15

The RETI instruction must be executed while the S flag is set to 0.

Precaution on Delay Slot

A delay slot for a branch instruction has restrictions regarding EIT.

See "3.7 Branch Instructions".

63


3.9 Operating Modes

Two operating modes are provided: bus mode and access mode. This section describes these modes.

Operating Modes

Bus mode

Bus mode refers to a mode in which the operations of internal ROM and the external accessfunction are controlled. A bus mode is specified using the setting pins (MD2, MD1, and MD0) andthe ROMA bit in the mode data.

Access mode

An access mode is specified using the WTH1 and WTH0 bits in the mode register and the DBW1and DBW0 bits in ACR0 to ACR7 (Area Configuration Register).

Bus Modes

The MB91319 has the following three bus modes.

Bus Mode 0 (single-chip mode)

In this mode, internal I/O, DbusRAM, FbusRAM, and FbusROM are valid. Access to other areasis invalid.

External pins do not serve as bus pins, but serve as peripheral or general-purpose I/O ports.

Bus Mode 1 (internal-ROM/external-bus mode)

In this mode, internal I/O, DbusRAM, and FbusRAM, as well as FbusROM, are valid. Access toan area that enables external access is handled as access to an external space. Some externalpins serve as bus pins.

Bus Mode 2 (external-ROM/external-bus mode)

In this mode, internal I/O, DbusRAM, and FbusRAM are valid, but access to FbusROM is invalid.All accesses are handled as access to an external space. Some external pins serve as bus pins.

Single chipInternal ROM/external busExternal ROM/external bus

16-bit bus width

8-bit bus width

Access modeBus mode

64


Mode Settings

For the MB91319, set the operating mode using the mode pins (MD3, MD2, MD1, and MD0) andthe mode register (MODR).

Mode pins

Use the three mode pins (MD3, MD2, MD1, and MD0) to specify mode vector fetch.

Note:

Mode settings other than the above are prohibited.

Mode register (MODR)

Mode data is data written to the mode register by a mode vector fetch (see "3.10.3 ResetSequence").

Mode data is always set in the mode register when any reset source arises. A user programcannot write data to the mode register.

Note:

Nothing exists at the address (0000_07FFH) of the MB91319 mode register.

Data can be rewritten to the mode register in emulator mode. Use an 8-bit long data transferinstruction to rewrite data. A 16-bit or 32-bit long data transfer instruction cannot be used torewrite data to the mode register.

Figure 3.9-1 shows the bit configuration of the mode register (MODR).

Figure 3.9-1 Bit Configuration of the Mode Register (MODR)

[bit7 to bit3] Reserved bits

These bits are reserved.

Mode pinMode name

Reset vector access area

RemarksMD3 MD2 MD1 MD0

0 0 0 0Internal ROM mode vector

Internal -

0 1 0 0Serial write

mode vector-

WTH00 0 WTH1000

01234567 Initial value

xxxxxxxxB

MODR

000FFFF8H

Operating mode setting bits

1

65


Note:

Be sure to set bit7 to bit3 to 00000. If any other value is set for these bits, operation is unpredictable.

[bit2] Reserved bit

Be sure to set this bit to 1.

[bit1, bit0] WTH1, WTH0 (Bus width specification bit)

These bits indicate the bus width specification to be used in external bus mode.

In external bus mode, this value is set in the BW1 and BW0 bits of AMD0 (CS0 area).

WTH1 WTH0 Function Remarks

0 0 - Setting prohibited


1 0 32-bit bus width -


66


3.10 Reset (Device Initialization)

This section describes a reset (that is, initialization) of the MB91319.

Reset (Device Initialization)

If a reset source occurs, the device stops all the programs and hardware operations andcompletely initializes the state. This state is called the reset state.

When a reset source no longer exists, the device starts programs and hardware operations fromtheir initial state. The series of operations from the reset state to the start of operations is calledthe reset sequence.

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3.10.1 Reset Levels

The reset operations of the MB91319 are classified into two levels, each of which has different causes and initialization operations. This section describes these reset levels.

Settings Initialization Reset (INIT)

The highest-level reset, which initializes all settings, is called a settings initialization reset (INIT).

A settings initialization reset (INIT) mainly performs the following initialization:

Items initialized in a settings initialization reset (INIT)

• Device operation mode (bus mode and external bus width settings)

• All internal clock settings (clock source selection, PLL control, and divide-by setting)

• All settings on external bus CS0 area

• All settings on pin statuses other than the above settings

• All sections initialized by an operation initialization reset (RST)

For more information, see the description of each of these functions.

Note:

After power-on, be sure to apply the settings initialization reset (INIT) at the INIT pin.

Operation Initialization Reset (RST)

A normal-level reset that initializes the operation of a program is called an operation initializationreset (RST).

If a settings initialization reset (INIT) occurs, an operation initialization reset (RST) also occurs.

An operation initialization reset (RST) mainly initializes the following items:

Items initialized by an operation initialization reset (RST)

• Program operation

• CPU and internal buses

• Register settings of peripheral circuits

• I/O port settings

• All CS0 area settings of external buses

For more information, see the description of each of these functions.

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3.10.2 Reset Sources

This section describes the reset sources and the reset levels in the MB91319.To determine reset sources that have occurred in the past, read the RSRR (reset source register). For more information about registers and flags described in this section, see "3.11.5 Block Diagram of Clock Generation Controller" and "3.11.6 Register of Clock Generation Controller".

INIT Pin Input (Settings Initialization Reset Pin)

The INIT pin, which is an external pin, is used as the settings initialization reset pin.

A settings initialization reset (INIT) request is generated while the L level is being input to this pin.

Input the H level to this pin to clear a settings initialization reset (INIT) request.

If a settings initialization reset (INIT) is generated in response to a request from this pin, bit15(INIT bit) of the RSRR (reset source register) is set.

Because a settings initialization reset (INIT) in response to a request from this pin has the highestinterrupt level among all reset sources, it has precedence over any other input, operation, orstate.

Immediately after power-on, be sure to apply a settings initialization reset (INIT) at the INIT pin.To assure the oscillation stabilization wait time for the oscillation circuit immediately after power-on, input the L level to the INIT pin for the stabilization wait time required by the oscillation circuit.INIT at the INIT pin initializes the oscillation stabilization wait time to the minimum value.

• Reset source: L level input to the external INIT pin

• Source of clearing: H level input to the external INIT pin

• Reset level: Settings initialization reset (INIT)

• Corresponding flag: bit15 (INIT)

Software Reset (STCR: SRST Bit Writing)

If 0 is written to bit4 (SRSI bit) of the standby control register (STCR), a software reset requestoccurs. A software reset request is an operation initialization reset (RST) request.

When the request is accepted and a operation initialization reset (RST) is generated, the softwarereset request is cleared.

If an operation initialization reset (RST) is generated due to a software reset request, a bit11(SRST bit) in the RSRR (reset source register) is set.

An operation initialization reset (RST) is generated due to a software reset request only after allbus access has stopped and if bit7 (SYNCR bit) of the time base counter control register (TBCR)has been set (synchronization reset mode). Thus, depending on the bus usage status, a longtime is required before an operation initialization reset (RST) occurs.

• Reset source: Writing 0 to bit4 (SRST) of the standby control register (STCR)

• Source of clearing: Generation of an operation initialization reset (RST)

• Reset level: Operation initialization reset (RST)

• Corresponding flag: bit11(SRST)

69


Reference:

For details on using software reset of synchronous mode, see restrictions of bit7: SYNCR bit of TBCR (timebase counter control register).

Watchdog Reset

Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Unless A5H/5AHis written to the time base counter clear register (CTBR) within the cycle specified in bit9 and bit8(WT1 and WT0 bits) in the RSRR, a watchdog reset request occurs.

A watchdog reset request is a settings initialization reset (INIT) request. If, after the request isaccepted, a settings initialization reset (INIT) occurs or an operation initialization reset (RST)occurs, the watchdog reset request is cleared.

If a settings initialization reset (INIT) is generated due to a watchdog reset request, bit13 (WDOGbit) in the reset source register (RSRR) is set.

Note that, if a settings initialization reset (INIT) is generated due to a watchdog reset request, theoscillation stabilization wait time is not initialized.

• Reset source: Setting cycle of the watchdog timer elapses

• Source of clearing: Generation of a settings initialization reset (INIT) or an operationinitialization reset (RST)

• Reset level: Settings initialization reset (INIT)

• Corresponding flag: bit13 (WDOG)

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3.10.3 Reset Sequence

When a reset source no longer exists, the device starts to execute the reset sequence.A reset sequence has different operations depending on the reset level.This section describes the operations of the reset sequence for different reset levels.

Setting Initialization Reset (INIT) Clear Sequence

If a settings initialization reset (INIT) request is cleared, the following operations are performedone step at a time for the device.

1. Clear the settings initialization reset (INIT) and enter the oscillation stabilization wait state.

2. For the oscillation stabilization wait time (set with bit3 and bit2 [OS1 and OS0 bits] in theSTCR), maintain the operation initialization reset (RST) state and stop the internal clock.

3. In the operation initialization reset (RST) state, start internal clock operation.

4. Clear the operation initialization reset (RST) and enter the normal operating state.

5. Read the mode vector from address 000FFFF8H.

6. Write the mode vector to the MODR (mode register) at address 000007FDH.

7. Read the reset vector from address 000FFFFCH.

8. Write the reset vector to the program counter (PC).

9. The program starts execution from the address loaded in the program counter (PC).

Operation Initialization Reset (RST) Clear Sequence

If an operation initialization reset (RST) request is cleared, the following operations are performedone step at a time for the device.

1. Clear the operation initialization reset (RST) and enter the normal operating state.

2. Read the mode vector from address 000FFFF8H.

3. Write the mode vector to the mode register (MODR) at address 000007FDH.

4. Read the reset vector from address 000FFFFCH.

5. Write the reset vector to the program counter (PC).

6. The program starts execution from the address loaded in the program counter (PC).

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3.10.4 Oscillation Stabilization Wait Time

If a device returns from the state in which the original oscillation was or may have been stopped, the device automatically enters the oscillation stabilization wait state. This function prevents the use of oscillator output after starting before oscillation has stabilized.For the oscillation stabilization wait time, neither an internal nor an external clock is supplied; only the built-in time base counter runs until the stabilization wait time set in the standby control register (STCR) has elapsed.This section describes the oscillation stabilization wait operation.

Sources of an Oscillation Stabilization Wait

The following lists sources of an oscillation stabilization wait.

Clearing of a settings initialization reset (INIT)

The device enters the oscillation stabilization wait state if a settings initialization reset (INIT) iscleared for a variety of reasons.

When the oscillation stabilization wait time has elapsed, the device enters the operationinitialization reset (RST) state.

Returning from stop mode

The device enters the oscillation stabilization wait state immediately after stop mode is cleared.

However, if it is cleared by a settings initialization reset (INIT) request, the device enters thesettings initialization reset (INIT) state. Then, after the settings initialization reset (INIT) iscleared, the device enters the oscillation stabilization wait state.

When the oscillation stabilization wait time has elapsed, the device enters the statecorresponding to the source that cleared stop mode:

• Return due to input of a valid external interrupt request (including NMI):The device enters the normal operating state.

• Return due to a settings initialization reset (INIT) request:The device enters the operation initialization reset (RST) state.

• Return due to an operation initialization reset (RST) request:The device enters the operation initialization reset (RST) state.

Returning from an abnormal state when PLL is selected

If, while the device is operating with PLL as the source clock, an abnormal condition* occurs inPLL control, the device automatically enters an oscillation stabilization wait to assure the PLL locktime.

When the oscillation stabilization wait time has elapsed, the device enters the normal operatingstate.

*: The multiply-by rate is changed while PLL is working, or an incorrect bit such as a bitequivalent to PLL operation enable bit is generated.

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Selecting an Oscillation Stabilization Wait Time

The oscillation stabilization wait time is measured with the built-in time base counter.

If a source for an oscillation stabilization wait occurs and the device enters the oscillationstabilization wait state, the built-in time base counter is initialized and then it starts to measure theoscillation stabilization wait time.

Using bit3 and bit2 (OS1 and OS0 bits) of the standby control register (STCR), select and set oneof the four types of oscillation stabilization wait time.

Once selected, a setting is initialized only if a settings initialization reset (INIT) is generated due tothe external INIT pin. The oscillation stabilization wait time that has been set before a reset ismaintained if a settings initialization reset (INIT) is generated or an operation initialization reset(RST) is generated due to a watchdog reset condition.

The four types of oscillation stabilization wait time settings are designed for the following fourtypes of use:

• OS1, OS0=00: No oscillation stabilization wait time (if neither PLL nor the oscillator shouldstop in stop mode)

• OS1, OS0=01: PLL lock wait time (if an oscillator should not stop in stop mode)

• OS1, OS0=10: Oscillation stabilization wait time (intermediate) (if an oscillator that stabilizesquickly, such as a ceramic vibrator, is used)

• OS1, OS0=11: Oscillation stabilization wait time (long) (if an ordinary quartz oscillator will beused)

Immediately after power-on, be sure to apply the settings initialization reset (INIT) at the INIT pin.

To assure the oscillation stabilization wait time of the oscillation circuit immediately after power-on, maintain L-level input to the INIT pin for the stabilization wait time required by the oscillationcircuit. (INIT generated due to the INIT pin initializes the oscillation stabilization wait time settingto the minimum value.)

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3.10.5 Reset Operation Modes

Two modes for an operation initialization reset (RST) are provided: normal (asynchronous) reset mode and synchronous reset mode. The operation initialization reset mode is selected with bit7 (SYNCR bit) of the time base counter control register (TBCR). This mode setting is initialized only by a settings initialization reset (INIT). A settings initialization reset always results in an asynchronous reset.This section describes the operation of these modes.

Normal Reset Operation

Normal reset operation refers to a transition to the operation initialization rest (RST) stateimmediately after an operation initialization reset (RST) request.

If a rest (RST) request is accepted in this mode, the device immediately enters the reset (RST)state regardless of the status of internal bus access.

In this mode, the result of a bus access being performed prior to each state transition isunpredictable. However, these requests can certainly be accepted.

If bit7 (SYNCR bit) of the time base counter control register (TBCR) is set to 0, normal resetmode is selected. The initial value after a settings initialization reset (INIT) is normal reset mode.

Synchronous Reset Operation

Synchronous reset operation refers to a transition to the operation initialization reset (RST) stateafter all bus access has stopped when an operation initialization reset (RST) request occurs.

Even if a reset (RST) request is accepted in this mode, the device does not enter the reset (RST)state while internal bus access is in progress.

If the above request is accepted, a sleep request is issued to the internal buses. If all the busesstop and enter the sleep state, the device enters the operation initialization reset (RST) state.

In this mode, the result of all bus accesses is guaranteed because all bus access is stopped priorto each status transition.

If bus access does not stop for some reason, no requests can be accepted while the bus accessis in progress. Even in this case, the settings initialization reset (INIT) is immediately valid.

Bus access may not stop in the following cases:

• A bus release request (BRQ) continues to be input to the external extended bus interface, busrelease acknowledge (BGRNT) is valid, and a new bus access request arrives from an internalbus.

• A ready request (RDY) continues to be input to the external extended bus interface and buswait is valid. In the following cases, the device eventually enters another state but only after along time:

Reference:

For details on using software reset of synchronous mode, see restrictions of bit7: SYNCR bit of TBCR (timebase counter control register).

The DMA controller, which stops transfer when a request is accepted, does not delay transition to anotherstate. If bit7 (SYNCR bit) of the time base counter control register (TBCR) is set to 1, synchronous reset modeis selected. The initial value after a settings initialization reset (INIT) is normal reset mode.

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3.11 Clock Generation Control

This section describes clock generation and control.

Clock Generation Control

The internal operating clock of the MB91319 is generated as follows:

• Selection of a source clock: Select a clock supply source.

• Generation of a base clock: Divide the source clock by two or perform PLL oscillation togenerate a base clock.

• Generation of an internal clock:Divide the base clock and generate four types of operatingclocks, which are supplied to each section.

Each clock generation and its control is described. The description of each register and thedetailed explanation of the flag refer to this chapter of clock generation controller "3.11.5 BlockDiagram of Clock Generation Controller" and "3.11.6 Register of Clock Generation Controller".

Selection of Source Clock

A resonator is connected to external oscillator pins X0/X1 and X0A/X1A, and the clock pulsesgenerated by the built-in oscillator circuit is used as the source clock.

The MB91319 is the source of all clocks, including the external bus clock.

The external oscillator pins and built-in oscillator circuit can use the main clock or subclock, andthese two clocks can be arbitrarily switched during operation.

• Main clockThe main clock, generated from the X0/X1 pins, is intended for use as a high-speed clock.

• SubclockThe subclock, generated from the X0A/X1A pins, is intended for use as a low-speed clock.

The main clock and subclock are multiplied by the built-in main PLL and subclock, each of whichcan be independently controlled.

Generate an internal base clock by selecting one of the following source clocks:

• Main clock divided by two

• Main clock multiplied in the main PLL

• Subclock as is

Select a source clock by setting the clock source control register (CLKR).

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3.11.1 PLL Controls

The operation (oscillation) enable and disable and multiply-by-rate setting can be independently controlled for each of the PLL oscillator circuits provided for each of main source clock and subclock. Each control is set in the clock source control register (CLKR).This section describes each control.

PLL Operation Enable

To enable or disable the main PLL oscillator circuit operation, set bit10 (PLL1EN bit) of the clocksource control register (CLKR).

To enable or disable the subclock oscillator circuit operation, set bit11 (PLL2EN bit) of the clocksource control register (CLKR).

After a setting initialization reset (INIT), bits PLL1EN and PLL2EN are initialized to 0, causing thePLL oscillator circuit operation to stop. While it is stopped, PLL output cannot be selected as thesource clock.

When the program operation starts, set the multiply-by rate of the PLL to be used as the clocksource, enable it, and switch the source clock after the PLL lock wait time elapses. For the PLLlock wait time, use of a time base timer interrupt is recommended.

While PLL output is selected as the source clock, the PLL cannot be stopped (writing to theregister is disabled). To stop a PLL upon transition to stop mode, reselect as the source clock themain clock divided by two before stopping the PLL.

If bit0 (OSCD1 bit) or bit1 (OSCD2 bit) of the standby control register (STCR) is set to stoposcillation in stop mode, the corresponding PLL automatically stops when the device enters stopmode. As a result, you do not need to set operation stop. When the device returns from stopmode later, the PLL automatically restarts the oscillation operation. If oscillation is not set to stopin stop mode, the PLL does not automatically stop. In this case, set operation stop beforetransition to stop mode as required.

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PLL Multiply-by Rate

Set the multiply-by rate of the main PLL in bit14 to bit12 (PLL1S2, PLL1S1, and PLL1S0 bits) ofthe clock source control register (CLKR).

After a setting initialization reset (INIT), all bits are initialized to 0.

PLL multiply-by rate setting

To change the PLL multiply-by rate setting from the initial value, do so before or as soon as thePLL is enabled after the program has started execution. After changing the multiply-by rate,switch the source clock after the lock wait time elapses. For the PLL lock wait time, use of a timebase timer interrupt is recommended.

To change the PLL multiply-by rate setting during operation, switch the source clock to a clockother than the PLL in question before making the change. After changing the multiply-by rate,switch the source clock after the lock wait time has elapsed, as described above.

You can also change the PLL multiply-by rate setting while using a PLL. In this case, however,the program stops running after the device automatically enters the oscillation stabilization waitstate after the multiply-by rate setting is rewritten and does not resume execution until thespecified oscillation stabilization wait time has elapsed.

The program does not stop running if the clock source is switched to a clock other than a PLL.

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3.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time

If a clock selected as the source clock is not already stabilized, an oscillation stabilization wait time is required (See "3.10.4 Oscillation Stabilization Wait Time").For a PLL, a lock wait time is required after operation starts until the output stabilizes to the specified frequency.This section describes the wait time used in various situations.

Wait Time after Power-On

After power-on, an oscillation stabilization wait time for the main clock oscillation circuit isrequired.

Since the oscillation stabilization wait time setting is initialized to the minimum value due to INITpin input (settings initialization reset pin), assure the oscillation stabilization wait time by using thetime during which the L level is sent to the INIT pin input.

In this state, since no PLL is enabled, no lock wait time needs to be considered.

Wait Time after Setting Initialization

If a settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization waitstate. In this case, the specified oscillation stabilization wait is internally generated. In the firstoscillation stabilization wait state after input from the INIT pin, the setting time is initialized to theminimum value, soon ending this state, and the device enters the operation initialization reset(RST) state.

If, after a program starts running, a settings initialization reset (INIT) is generated for a reasonother than INIT pin input and is then cleared, the oscillation stabilization wait time specified in theprogram is internally generated.

In these states, since no PLL is enabled, no lock wait time needs to be considered.

Wait Time after Enabling a PLL

If you enable a stopped PLL after a program starts execution, use the PLL output only after thelock wait time elapses. If the PLL is not selected as the source clock, the program can run evenduring the lock wait time. For the PLL lock wait time, use of a time base timer interrupt isrecommended.

Wait Time after Changing the PLL Multiply-by Rate

If you change the multiply-by rate setting of a running PLL after a program starts execution, usethe PLL output only after lock wait time elapses.

If the PLL is not selected as the source clock, the program can run even during the lock wait time.

For the PLL lock wait time, use of a time base timer interrupt is recommended.

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Wait Time after Returning from Stop Mode

If, after a program starts execution, the device enters stop mode and then stop mode is cleared,the oscillation stabilization wait time specified in the program is internally generated. If the clockoscillation circuit selected as the source clock is set to stop in stop mode, the oscillationstabilization wait time of the oscillation circuit or the lock wait time of the PLL in use, whichever islonger, is required. Set the oscillation stabilization wait time before entering stop mode.

If the clock oscillation circuit selected as the source clock is not set to stop in stop mode, the PLLdoes not automatically stop. No oscillation stabilization wait time is required unless the PLL hasstopped. Setting the oscillation stabilization wait time to the minimum value before stop mode isentered is recommended.

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3.11.3 Clock Distribution

An operating clock for each function is generated based on the base clock generated from the source clock. A total of three internal operating clocks are provided. A divide-by rate can be set independently for each of them.This section describes these internal operating clocks.

CPU Clock (CLKB)

This clock is used for the CPU, internal memory, and internal buses.

It is used by the following circuits:

• CPU

• Instruction cache

• Built-in RAM and ROM

• Bit search module

• I-bus, D-bus, X-bus, and F-bus

• DMA controller

• DSU

Note:

Since 40 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rateand divide-by rate that results in a frequency exceeding this limit.

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Peripheral Clock (CLKP)

This clock is used for peripheral circuits and peripheral buses.


• Peripheral bus

• Clock controller (only for the bus interface)

• Interrupt controller

• Peripheral I/O ports (port*, port*)

• I/O port bus

• External interrupt input

• UART

• 16-bit timer

• A/D converter

• ICU

• Free-run timer

• Reload timer

• Up/down counter

• Input capture

• Output compare

• I2C interface

• PPG

Note:

Since 20 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rateand divide-by rate that results in a frequency exceeding this limit.

External Bus Clock (CLKT)

This clock is used for external extended bus interfaces.


• External extended bus interface

• External CLK output

Notes:

• Since 20 MHz is the upper-limit frequency for operation, do not set a combination of multiply-byrate and divide-by rate that results in a frequency exceeding this limit.

• Processing capability of CPU is affected by the setting of wait register (FLWC). Be sure to set theappropriate value to this register. See Section "19.2.2 Flash Memory Wait Register (FLWC)".

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3.11.4 Clock Division

A divide-by rate can be set independently for each of the internal operating clocks. With this function, an optimal operating frequency can be set for each circuit.

Clock Division

Set a divide-by rate in Basic Clock Division Setting Register 0 (DIVR0) and Basic Clock DivisionSetting Register 1 (DIVR1). Each of these registers has four setting bits and (Register settingvalue + 1) is the divide-by rate of the clock in relation to the base clock. Even if the divide-by ratesetting is an odd number, the duty is always 50%.

If the setting value is changed, the new divide-by rate becomes valid at the leading edge of thenext clock after the setting is made.

The divide-by rate setting is not initialized if an operation initialization reset (RST) occurs and thesetting made before the reset occurs is retained. The divide-by rate setting is initialized only if asettings initialization reset (INIT) occurs. In the initial state, all clocks other than the peripheralclock (CLKP) have a divide-by rate of 1. Thus, be sure to set the divide-by rate before changingthe source clock to a faster clock.

Note:

An upper-limit frequency for the operation is set for each clock. If you set a combination of sourceclock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequency exceedingthis upper-limit frequency, operation is not guaranteed. (Be extra careful of the order in which youchange settings to select the source clock and to configure the associated setting items.)

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3.11.5 Block Diagram of Clock Generation Controller

This section provides a block diagram of the clock generation controller.The detailed description of register in the figure refers to 8 Detailed explanation for register of clock generation controller.

Block Diagram

Figure 3.11-1 shows a block diagram of the clock generation controller.

Figure 3.11-1 Block Diagram of Clock Generation Controller

X1

X0

1/2

PLL

X1A

X0A

Selector

[Clock generator]

CPU clock division

Peripheral clock division

External bus clock division

Sto

p co

ntro

l

CPU clock

Peripheral clock

External bus clock

R-b

us

DIVR0,1 registers

Peripheral circuit operation stop control register

Perip

hera

l ci

rcui

t ope

ratio

n st

op c

ontro

l

Oscilla-tion circuit

Oscilla-tion circuit

Sele

ctor

CLKR register

Main clock oscillator stabilization wait timer (for subclock selection)

Resetoccurrence F/F

Resetoccurrence F/F

Statustransition control circuit

STCR register

Internal reset

Internal interrupt

[Stop and sleep controller]

Stop status

Sleep status

Internal reset (RST)

Internal reset (INIT)

Counter clock

Interrupt enable

INIT pin

CTBR register

Time base counter

Watchdog F/F

Overflow detection F/FTBCR register

RSRR register

Time base timerinterrupt reques

[Watchdog controller]

Selector

[Reset source circuit]

Main clock

Sub clock

Watch timer

Selector

Selector

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3.11.6 Register of Clock Generation Controller

This section describes the functions of registers to be used in the clock generation controller.

Reset Source Register/Watchdog Timer Control Register (RSRR)

Figure 3.11-2 shows the configuration of the reset source register/watchdog timer control register(RSRR).

Figure 3.11-2 Configuration of Reset Source Register/Watchdog Timer Control Register (RSRR) Bits

This register holds the source of the last reset that occurred as well as the interval setting andstartup control for the watchdog timer. If the timer is read, the reset source that has been held iscleared after it is read. If more than one reset is generated before this register is read, resetsource flags are accumulated and the multiple flags are set.

Writing to this register starts the watchdog timer. Thereafter, the watchdog timer continuesrunning until a reset (RST) occurs.

[bit15] INIT (INITialize reset occurred)

This bit indicates whether a reset (INIT) occurred due to INIT pin input.

• This bit is initialized to 0 after it is read.

• This bit is readable; writing to the bit has no effect on the bit value.

[bit14] (Reserved bit)

[bit13] WDOG (WatchDOG reset occurred)

This bit indicates whether a reset (INIT) occurred due to the watchdog timer.

• This bit is initialized to 0 after a reset (INIT) due to INIT pin input or just after it is read.


bit 15 14 13 12 11 10 9 8

R R R R R R R R/W

Address:00000480H INIT - WDOG - SRST - WT1 WT0

Initial value (INIT) * * * x x * 0 0Initial value (RST) x x x * * x 0 0*: Varies according to the source.x: Not initialized

Initial value (INIT pin) 1 0 0 0 0 0 0 0

0 INIT occurred due to INIT pin input.

1 INIT occurred due to INIT pin input.

0 No INIT occurred due to the watchdog timer.

1 INIT occurred due to watchdog timer.

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This bit is reserved.

[bit11] SRST (Software ReSeT occurred)

This bit indicates whether a reset (RST) occurred due to writing to the SRST bit of the STCRregister (a software reset).

• This bit is initialized to 0 after a reset (INIT) due to INIT pin input or just after it is read.




[bit9, bit8] WT1, WT0 (Watchdog interval Time select)

This bit sets the interval of the watchdog timer.

The values written to these bits determine the interval of the watchdog timer, which can beselected from the four types shown in the following table.

• These bits are initialized to 00 after a reset (RST).

• These bits are readable, but are writable only once after a reset (RST). Any further writing isdisabled.

0 No RST occurred due to a software reset.

1 RST occurred due to a software reset.

WT1 WT0Minimum required interval for

writing to the CTBR to suppress a watchdog reset

Time from writing the last 5AH to the CTBR until a watchdog reset

occurs

0 0 φ × 216 (initial value) φ × 216 to φ × 217

0 1 φ × 218 φ × 218 to φ × 219

1 0 φ × 220 φ × 220 to φ × 221

1 1 φ × 222 φ × 222 to φ × 223

φ: Frequency of the system base clock

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Standby Control Register (STCR)

Figure 3.11-3 shows the configuration of the standby control register (STCR).

Figure 3.11-3 Configuration of Standby Control Register (STCR) Bits

The standby control register controls the operating mode of the device.

This register controls the transition to the two standby modes of stop and sleep, pins when in stopmode, and the stopping of oscillation stop. It also sets the oscillation stabilization wait time andissues software resets.

The following describes the functions of the standby control register (STCR) bits.

[bit7] STOP (STOP mode)

This bit specifies entry into stop mode. If 1 is written to both bit6 (SLEEP bit) and this bit, thisbit has precedence and the device enters stop mode

• This bit is initialized to 0 by a reset (RST) and by a stop return source.

• This bit is readable and writable.

[bit6] SLEEP (SLEEP mode)

This bit specifies entry into stop mode. If 1 is written to both bit7 (STOP bit) and this bit, thisbit (STOP) has precedence and the device enters stop mode.

• This bit is initialized to 0 by a reset (RST) and by a sleep return source.


bit 7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

Address:00000481H STOP SLEEP HIZ SRST OS1 OS0 OSCD2 OSCD1

Initial value (HSTX)* 0 0 1 1 1 1 1 1

Initial value (INIT pin) 0 0 1 1 0 0 1 1

Initial value (RST) 0 0 x 1 x x x x Initial value (INIT) 0 0 1 1 x x 1 1

*: Occurs only at the same time as initialization due to the INIT pin. Otherwise, the same as INIT.

0 Stop mode not entered (initial value)

1 Stop mode entered

0 Sleep mode not entered (initial value)

1 Sleep mode entered

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[bit5] HIZ (HIZ mode)

This bit controls the pin state in stop mode.

• This bit is initialized to 0 by a reset (INIT).


[bit4] SRST (Software ReSeT)

This bit specifies issuing of a software reset (RST).

• This bit is initialized to 1 by a reset (RST).

• This bit is readable and writable. The read value is always 1.

Reference:

For details on using software reset of synchronous mode, see restrictions of bit7: SYNCR bitof TBCR (time base counter control register).

[bit3, bit2] OS1, OS0 (Oscillation Stabilization time select)

These bits set the oscillation stabilization wait time used after a reset (INIT), return from stopmode, etc.

The values written to these bits determine the interval of the watchdog timer, which can beselected from the four types shown in the following table.

• These bits are initialized to 00 by a reset (INIT) generated due to INIT pin input. If both resets(INIT) generated due to INIT and HSTX pin input are valid, these bits are initialized to 11.

• These bits are readable and writable.

0 The pin state before stop mode entered is maintained.

1 Pin output is set to high-impedance state in stop mode (initial value).

0 A software reset is issued.

1 A software reset is not issued (initial value).

OS1 OS0Oscillation stabilization

wait timeIf the source oscillation is

10 MHz

0 0 φ × 21 (initial value) 0.4 [µs]

0 1 φ × 211 410 [µs]

1 0 φ × 216 13.1 [ms]

1 1 φ × 222 839 [ms]

φ: Frequency of the system base clock; in this case, twice the cycle of the source oscillation input

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[bit1] OSCD2 (OSCillation Disable mode for XIN2)

This bit controls stopping of the sub-oscillation input (XIN2) in stop mode.



[bit0] OSCD1 (OSCillation Disable mode for XIN1)

This bit controls stopping of main oscillation input (XIN1) in stop mode.



Time Base Counter Control Register (TBCR)

Figure 3.11-4 shows the configuration of the time base counter control register (TBCR) bits.

Figure 3.11-4 Configuration of Time Base Counter Control Register (TBCR) Bits

The time base counter control register controls time base timer interrupts, among other things.

This register enables time base timer interrupts, selects an interrupt interval time, and sets anoptional function for the reset operation.

[bit15] TBIF (TimeBasetimer Interrupt Flag)

This bit is the time base timer interrupt flag. It indicates that the interval time (TBC2-0 bits,which are bit13 to bit11) specified by the time base counter has elapsed.

A time base timer interrupt request is generated if this bit is set to 1 when interrupts areenabled by bit14 (TBIE bit, TBIE=1).


• This bit is readable and writable, although only 0 can be written to it. Writing 1 does notchange the bit value. The value read by a read modify write instruction is always 1.

0 Not stopping the sub-oscillation in stop mode

1 Stopping the sub-oscillation in stop mode (initial value)

0 Main oscillation does not stop in stop mode.

1 Main oscillation stops in stop mode (initial value).

bit 15 14 13 12 11 10 9 8


Address: 00000482H TBIF TBIE TBC2 TBC1 TBC0 - SYNCR SYNCS

Initial value (RST) 0 0 x x x x x xInitial value (INIT) 0 0 x x x x 0 0

Clear source An instruction writes 0.

Set sourceThe specified interval time elapses (the trailing edge of the time base counter is detected).

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[bit14] TBIE (TimeBasetimer Interrupt Enable)

This bit is the time base timer interrupt request output enable bit.

It controls output of an interrupt request when the interval time of the time base counter haselapsed. A time-base timer interrupt request is generated if bit15 (TBIF bit) is set to 1 whenthis bit is set to 1.



[bit13 to bit11] TBC2, TBC1, TBC0 (TimeBasetimer Counting time select)

These bits set the interval time of the time base counter that is used for the time base timer.

The values written to these bits determine the interval time, which can be selected from theeight types shown in Table 3.11-1.

• The initial value is undefined. Be sure to set a value before enabling an interrupt.


[bit10] (reserved bit)

This bit is reserved. The read value is undefined. Writing to this bit has no effect onoperation.

0 Time base timer interrupt request output disabled (initial value)

1 Time base timer interrupt request output enabled

Table 3.11-1 Interval Settings

TBC2 TBC1 TBC0 Timer interval timeIf the source oscillation is 10 MHz

and PLL is multiplied by 4

0 0 0 φ × 211 51.2 [µs]

0 0 1 φ × 212 102 [µs]

0 1 0 φ × 213 205 [µs]

0 1 1 φ × 222 105 [ms]

1 0 0 φ × 223 210 [ms]

1 0 1 φ × 224 419 [ms]

1 1 0 φ × 225 839 [ms]

1 1 1 φ × 226 1678 [ms]


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[bit9] SYNCR (SYNChronous Reset enable)

This bit is the synchronous reset enable bit.

This bit specifies whether normal reset operation or synchronous reset operation is executedwhen an operation initialization reset (RST) request occurs. Normal reset operation performsa reset (RST) immediately. Synchronous reset operation performs an operation initializationreset (RST) after all bus access has stopped.



Note:

To use the software reset of synchronous mode, be sure to meet the following 2 conditions.

• Set interrupt enable flag (I-Flag) to "disabled" (I-Flag= 0)

• Do not use NMl

[bit8] SYNCS (SYNChronous Standby enable)

This bit is the synchronous standby enable bit.

It is used to select one of the following operations, which is to be used if an standby request(either sleep or stop mode request) occurs: (1) Performing a normal standby operation onlyby writing to the control bit in the STCR register or (2) performing a synchronous standbyoperation by reading the STCR register after writing to the control bit in the STCR register.



Note:

Be sure to set "1" to set synchronous standby operation when changing to standby mode.

0 Normal reset operation (initial value)

1 Synchronous reset operation

0 Normal standby operation (initial value)

1 Synchronous standby operation

90


Time Base Counter Clear Register (CTBR)

Figure 3.11-5 shows the configuration of the time base counter clear register (CTBR) bits.

Figure 3.11-5 Configuration of Time Base Counter Clear Register (CTBR) Bits

The time base counter clear register initializes the time base counter.

If A5H and 5AH are written successively to this register, all the bits in the time base counter arecleared to 0 as soon as 5AH is written. There is no time limit between writing of A5H and5AH. However, if data other than 5AH is written after A5H is written, A5H must be writtenagain before 5AH is written. Otherwise, a clear operation will not occur.

Clearing occurs automatically while the CPU is not running, such as in the stop, sleep, or DMAtransfer state. If one of these conditions occurs, a watchdog reset is automatically postponed.However, a watchdog reset is not postponed when an external bus hold request (BRQ) has beenaccepted. To hold the external bus for a long time, enter sleep mode and then input a holdrequest (BRQ).

The value read from this register is undefined.

Note:

If the time base counter is cleared using this register, the oscillation stabilization wait interval,watchdog timer interval, and time base timer interval temporarily vary.

bit 7 6 5 4 3 2 1 0

W W W W W W W W

Address: 00000483H D7 D6 D5 D4 D3 D2 D1 D0

Initial value (RST) x x x x x x x x Initial value (INIT) x x x x x x x x

91


Clock Source Control Register (CLKR)

Figure 3.11-6 shows the configuration of the clock source control register (CLKR) bits.

Figure 3.11-6 Configuration of Clock Source Control Register (CLKR) Bits

The clock source control register is used to select the clock source that will be used as the baseclock of the system and controls the PLL. Use this register to select one of three clock sources(the MB91319 supports only two of these). This register also enables the main PLL and each ofthe sub-PLLs and selects the multiply-by rate for them.

[bit15] PLL2S0 (PLL2 ratio Select 0)

This bit is the multiply-by rate selection bit for the subclock.

Select one of the two multiply-by rates for the subclock.

Always write 0 to this bit for the MB91319.



[bit14 to bit12] PLL1S2, PLL1S1, PLL1S0 (PLL1 ratio Select 2-0)

These bits are the multiply-by selection bits for the main PLL. Select one of the eight multiply-by rates (the MB91319 supports only four of these) shown in Table 3.11-2.

Note:

Rewriting of this bit is disabled while the main PLL is selected as the clock source. The upper-limitfrequency for operation is 40 MHz. Do not set a multiply-by rate that results in a frequencyexceeding this limit.

bit 15 14 13 12 11 10 9 8

Address: 00000484H PLL2S0 PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1 CLKS0

Initial value (RST) x x x x x x x xInitial value (INIT) 0 0 0 0 0 0 0 0


0 Multiply-by rate setting 1 (initial value)

1 Multiply-by rate setting 1

92


• These bits are initialized to 000 by a reset (INIT).


[bit11] PLL2EN (PLL2 ENable)

This is the operation enable bit for the subclock.

Rewriting of this bit is disabled while the subclock is selected as the clock source. Selection ofthe subclock as the clock source is disabled while this bit is set to 0 (because of the settings ofbit9 and bit8 [bits CLKS1 and CLKS0]).

The subclock stops in stop mode even when this bit is set to 1 as long as STCR bit1 (OSCD2)is set to 1. After the device returns from the stop mode, the subclock is enabled again.



[bit10] PLL1EN (PLL1 ENable)

This bit is the enable bit of the main PLL.

Rewriting of this bit is disabled while the main PLL is selected as the clock source. Selectionof the main PLL as the clock source is disabled while this bit is set to 0 (because of thesettings of bit9 and bit8 [bits CLKS1 and CLKS0]).

The main PLL stops in stop mode even when this bit is set to 1 as long as STCR bit1(OSCD2) is set to 1. After the device returns from the stop mode, the main PLL is enabledagain.



Table 3.11-2 Main PLL Multiply-By Rate Settings

PLL1S2 PLL1S1 PLL1S0Main PLL multiply-

by rateIf the source oscillation is 16.5 MHz

0 0 0 × 1 (equal) For source oscillator 10 (MHz), φ = 100[ns] (10 (MHz))

0 0 1 × 2 (multiplied by 2) For source oscillator 10 (MHz), φ = 50[ns] (20 (MHz))



1 0 0 × 5 (multiplied by 5) Not supported by the MB91319.





0 Subclock stopped (initial value)

1 Subclock enabled

0 Main PLL stopped (initial value)

1 Main PLL enabled

93


[bit9, bit8] CLKS1, CLKS0 (CLocK source Select)

These bits set the clock source that will be used by the FRex core.

The values written to these bits determine the clock source, which can be selected from thethree types shown in Table 3.11-3.

While bit9 (CLKS1) is set to 1, the value of bit8 (CLKS0) cannot be changed. Table 3.11-4 liststhe combinations of bits CLKS1 and CLKS0 that cannot be changed and those that can.

To select the subclock in the post-INIT state, first write 01 and then write 11.



Note:

From subclock source X0A/X1A, the source oscillation input with the frequency divided by 2 cannotbe selected.

Table 3.11-3 Clock Source Settings

CLKS1 CLKS0 Clock source setting

0 0 Source oscillation input from X0/X1 divided by 2 (initial value)

0 1 Source oscillation input from X0/X1 divided by 2

1 0 Main PLL

1 1 Subclock

Table 3.11-4 Combinations of CLKS1 and CLKS0 Bits that Can and Cannot Be Changed

Cannot be changed Can be changed

"00" → "11" "00" → "01" or "10"

"01" → "10" "01" → "11" or "00"

"10" → "01" or "11" "10" → "00"

"11" → "00" or "10" "11" → "01"

94


Base Clock Division Setting Register 0 (DIVR0)

Figure 3.11-7 shows the configuration of the Base Clock Division Setting Register 0 (DIVR0) bits.

Figure 3.11-7 Configuration of Base Clock Division Setting Register 0 (DIVR0) Bits

Base Clock Division Setting Register 0 (DIVR0) controls the divide-by rate of an internal clock inrelation to the base clock. This register sets the divide-by rates of the CPU clock, the clocks of aninternal bus (CLKB) and a peripheral circuit, and the peripheral bus clock (CLKP).

An upper-limit frequency for the operation is prescribed for each clock. If the combination ofsource clock selected, PLL multiply-by rate setting, and divide-by rate setting results in afrequency exceeding this upper-limit frequency, operation is unpredictable. Be extremely carefulof the order in which you change the settings when selecting the source clock.

If the setting in this register is changed, the new frequency-divide-by rate takes effect for the clockrate following the one during which the setting was made.

[bit15 to bit12] B3, B2, B1, B0 (clkB divide select 3-0)

These bits are the clock divide-by rate setting bits of the CPU clock (CLKB). Set the clockdivide-by rate of the CPU, internal memory, and internal bus clock (CLKB). The values writtento these bits determine the divide-by rate (clock frequency) of the CPU and internal bus clockin relation to the base clock, which can be selected from the 16 types shown in Table 3.11-5.

The upper-limit frequency for operation is 50 MHz. Do not set a divide-by rate that results in afrequency exceeding this limit.



bit 15 14 13 12 11 10 9 8

Address: 00000486H B3 B2 B1 B0 P3 P2 P1 P0



Table 3.11-5 Clock Divide-By Rate (CPU Clock ) Settings

B3 B2 B1 B0 Clock divide-by rateClock frequency: if the source oscillation is

10 [MHz] and the PLL is multiplied by 4

0 0 0 0 φ 40 [MHz] (initial value)

0 0 0 1 φ × 2 (divided by 2) 20 [MHz]

0 0 1 0 φ × 3 (divided by 3) 13.3 [MHz]

0 0 1 1 φ × 4 (divided by 4) 10 [MHz]

0 1 0 0 φ × 5 (divided by 5) 8 [MHz]

0 1 0 1 φ × 6 (divided by 6) 6.67 [MHz]

0 1 1 0 φ × 7 (divided by 7) 5.71 [MHz]

0 1 1 1 φ × 8 (divided by 8) 5 [MHz]

... ... ... ... ... ...

1 1 1 1 φ × 16 (divided by 16) 2.5 [MHz]


95


[bit11 to bit8] P3, P2, P1, P0 (clkP divide select 3-0)

These bits are the clock divide-by rate setting bits of the peripheral clock (CLKP). Set theclock divide-by rate of the peripheral circuit and the peripheral bus clock (CLKP). The valueswritten to these bits determine the divide-by rate (clock frequency) of the peripheral circuit andthe peripheral bus clock in relation to the base clock, which can be selected from the 16 typesshown in Table 3.11-6.

The upper-limit frequency for operation is 20 MHz. Do not set a divide-by rate that results in afrequency exceeding this limit.



Base Clock Division Setting Register 1 (DIVR1)

Figure 3.11-8 shows the configuration of the Base Clock Division Setting Register 1 (DIVR1) bits.

Figure 3.11-8 Configuration of Base Clock Division Setting Register 1 (DIVR1) Bits

Base clock division setting register 1 controls the divide-by rate of an internal clock in relation tothe base clock.

This register sets the divide-by rate for the external extended bus interface clock (CLKT).

An upper-limit frequency for the operation is set for each clock. If the combination of source clockselected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency exceedingthis upper-limit frequency, operation is unpredictable. (Be extremely careful of the order in whichyou change the settings when selecting the source clock.)

Table 3.11-6 Clock Divide-by Rate (Peripheral Clock ) Settings

P3 P2 P1 P0 Clock divide-by rateClock frequency: if the source oscillation is 10 [MHz] and the PLL is multiplied by 4

0 0 0 0 φ 40 [MHz]

0 0 0 1 φ × 2 (divided by 2) 20 [MHz]

0 0 1 0 φ × 3 (divided by 3) 13.3 [MHz]

0 0 1 1 φ × 4 (divided by 4) 10 [MHz] (initial value)

0 1 0 0 φ × 5 (divided by 5) 8 [MHz]

0 1 0 1 φ × 6 (divided by 6) 6.67 [MHz]

0 1 1 0 φ × 7 (divided by 7) 5.71 [MHz]

0 1 1 1 φ × 8 (divided by 8) 5 [MHz]

... ... ... ... ... ...

1 1 1 1 φ × 16 (divided by 16) 2.5 [MHz]


bit 7 6 5 4 3 2 1 0

Address: 00000487H T3 T2 T1 T0 - - - -



96


If the setting in this register is changed, the new divide-by rate takes effect for the clock ratefollowing the one during which the setting was made.

[bit7 to bit4] T3, T2, T1, T0 (clkT divide select 3-0)

These bits are the clock divide-by rate setting bits of the external bus clock (CLKT). Set theclock divide-by rate of the external extended bus interface clock (CLKT). The values written tothese bits determine the divide-by rate (clock frequency) of the external extended businterface clock in relation to the base clock, which can be selected from the 16 types shown inTable 3.11-7.

The upper-limit frequency for operation 20 MHz. Do not set adivide-by rate that results in afrequency exceeding this limit.

97




[bit3 to bit0] (reserved bits)


Oscillation Control Register (OSCCR)

Figure 3.11-9 shows the bit configuration of the oscillation control register (OSCCR).

Figure 3.11-9 Bit Configuration of Oscillation Control Register (OSCCR)

The oscillation control register controls the main clock oscillation during operation of the subclock.

[bit8] OSCDS1 (OSCillation Disable on Subclock for XIN1)

This bit is the stop bit for main clock oscillation while the subclock is selected.

Writing 1 to this bit stops main clock oscillation while the subclock is selected as the clocksource.

Writing 1 to this bit is disabled while the main clock is selected.

Selection of the main clock is disabled while this bit is set to 1. Set this bit to 0, and wait forstabilization of the main clock oscillation. Then, switch to the main clock. Use the mainoscillation stabilization wait timer to secure the oscillation stabilization wait time.

Table 3.11-7 Clock Divide-By Rate (External Bus Clock) Settings

T3 T2 T1 T0 Clock divide-by rateClock frequency: if the source oscillation is

10 [MHz] and the PLL is multiplied by 4

0 0 0 0 φ 40 [MHz] (initial value)

0 0 0 1 φ × 2 (divided by 2) 20 [MHz]

0 0 1 0 φ × 3 (divided by 3) 13.3 [MHz]

0 0 1 1 φ × 4 (divided by 4) 10 [MHz]

0 1 0 0 φ × 5 (divided by 5) 8 [MHz]

0 1 0 1 φ × 6 (divided by 6) 6.67 [MHz]

0 1 1 0 φ × 7 (divided by 7) 5.71 [MHz]

0 1 1 1 φ × 8 (divided by 8) 5 [MHz]

... ... ... ... ... ...

1 1 1 1 φ × 16 (divided by 16) 2.5 [MHz]


bit 15 14 13 12 11 10 9 8

Address: 0000048AH - - - - - - - OSCDS1

Initial value (RST) x x x x x x x xInitial value (INIT) x x x x x x x 0


98


If INIT switches the clock source to the main clock when this bit stops main clock oscillation,the main oscillation stabilization wait time is also required. If the settings of bit3 and bit2 (OS1and OS0) of the standby control register (STCR) do not satisfy the main oscillationstabilization wait time, the operation after return is unpredictable. In this case, set values thatsatisfy both the subclock oscillation stabilization wait time and the main clock oscillationstabilization wait time in the STCR (OS1 and OS0) bits. For INIT from the INIT pin, an L levelsignal must continue to be input to the INIT pin until main clock oscillation is stabilized.

For details about the oscillation stabilization wait, see "3.11.2 Oscillation Stabilization WaitTime and PLL Lock Wait Time".

• This bit is initialized to 0 after a reset (INIT).

• This bit can be read and written.

0Main clock oscillation is not stopped during execution of subclock (default value).

1 Main clock oscillation is stopped during execution of subclock.

99


3.11.7 Peripheral Circuits of Clock Controller

This section describes the peripheral circuit functions of the clock controller.

Time Base Counter

The clock controller has a 26-bit time base counter that runs on the system base clock.

The time base counter is used to measure the oscillation stabilization wait time in addition tohaving the uses listed below (For more information about the oscillation stabilization wait time,see "3.10.4 Oscillation Stabilization Wait Time").

• Watchdog timer

The watchdog timer, which is used to detect a system runaway, measures time using the bitoutput of the time base counter.

• Time base timer

The time base timer generates an interval interrupt using output from the time base counter.

The following describes these functions.

Watchdog timer

The watchdog timer detects a runaway using output from the time base counter. If a programrunaway results in a watchdog reset no longer being postponed for a specified interval, a settingsinitialization reset (INIT) request is generated as a watchdog reset.

[Startup and interval setting of the watchdog timer]

The watchdog timer is started when the reset source register and the watchdog timer controlregister (RSRR) are written to for the first time after a reset (RST). At this time, the intervaltime of the watchdog timer is set in bit09 and bit08 (WT1 and WT0 bits). Only the time definedin this first write is valid as the interval time setting. Any further writing is ignored.

[Postponing a watchdog reset]

Once the watchdog timer is started, the program must write A5H and 5AH in this order tothe time base counter clear register (CTBR). This operation initializes the watchdog resetgeneration flag.

[Generation of a watchdog reset]

The watchdog reset generation flag is set at the trailing edge of the time base counter outputof the specified interval. If the flag has already been set when a trailing edge is detected asecond time, a settings initialization reset (INIT) request is generated as a watchdog reset.

[Stopping the watchdog timer]

The watchdog timer, once started, cannot be stopped until an operation initialization reset(RST) occurs.

In the following states, when an operation initialization reset (RST) occurs, the watchdog timeris stopped and remains inoperative until a program starts it.

• Operation initialization reset (RST) state

• Settings initialization reset (INIT) state

• Oscillation stabilization wait reset (RST) state

100


[Suspending the watchdog timer (automatic postponement)]

If program operation stops on the CPU, the watchdog reset generation flag is initialized andgeneration of a watchdog reset is postponed. Stopping of program operation specificallyrefers to the following statuses:

• Sleep state

• Stop state

• Oscillation stabilization wait RUN state

• DMA transfer in progress on the data bus (D-bus)

• Emulation mode

If the time base counter is cleared, the watchdog reset generation flag is initialized at the sametime, postponing generation of a watchdog reset.

Time base timer

The time base timer generates an interval using output from the time base counter. This timer isappropriate for measurements that require a relatively long time (for example, a maximum interval

of base clock × 227 cycles such as for the PLL lock wait time or a subblock).

If the trailing edge of the time base counter output for the specified interval is detected, a timebase timer interrupt request is generated.

[Startup and interval settings of the time base timer]

For the time base timer, the interval time is set in bit13 to bit11 (TBC2, TBC1, and TBC0 bits)of the time base counter control register (TBCR). The trailing edge of the time base counteroutput for the specified interval is always detected. Thus, after setting the interval time, clearbit15 (TBIF bit) and then set bit14 (TBIE bit) to 1 to enable output of an interrupt request.

Before changing the interval time, set bit14 (TBIE bit ) to 0 to disable interrupt request output.

Since the time base counter always counts regardless of these settings, before enablinginterrupts, clear the time base counter to obtain an accurate interval interrupt time. Otherwise,an interrupt request may be generated immediately after an interrupt is enabled.

[Clearing of the time base counter due to a program]

If A5H and 5AH are written in this order to the time base counter clear register (CTBR), allbits of the time base counter are cleared to 0 immediately after 5AH is written. There is notime limit between writing of A5H and 5AH. However, if data other than 5AH is writtenafter A5H is written, A5H must be written again before 5AH is written. Otherwise, no clearoperation occurs.

If the time base counter is cleared, the watchdog reset generation flag is initialized at thesame time, postponing generation of a watchdog reset.

101


[Clearing of the time base counter due to the device state]

All bits of the time base counter are cleared to 0 at the same time if the device enters one ofthe following states:

• Stop state

• Settings initialization reset (INIT) state

Especially in the stop state, an interval interrupt of the time base timer may unintentionally begenerated because the time base counter is used to measure the oscillation stabilization waittime. Before setting stop mode, therefore, disable time base timer interrupts to prevent the timebase timer from being used.

In any other state, time base timer interrupts are automatically disabled because an operationinitialization reset (RST) occurs.

Watch Timer

The watch timer is a 15-bit free-run timer that performs incremental counting in synchronizationwith the 32 kHz subclock. The operation of this timer is not affected by the clock source selectionor the clock divide-by rate.

The watch timer is used to measure the subclock stabilization wait time and perform processingat fixed intervals using the subclock.

The watch timer performs incremental counting while the subclock is operating and is stoppedwhen bit1 (OSCD2 bit) of the standby control register (STCR) is set to1 so that the watch timerenters stop mode. To prevent the watch timer from being stopped in stop mode, set the OSCD2bit to 0 before the watch timer enters stop mode so that the subclock is not stopped.

Follow the procedure below for switching the clock source from the main clock to subclock usingthe watch timer:

1. Set the watch timer for the oscillation stabilization wait time. If necessary, clear all bits of thewatch timer to 0.

2. Set bit11 (PLL2EN bit) of the clock source register (CLKR) to 1 to start subclock oscillation.

3. Use the watch timer to wait until the subclock is stabilized. At this time, use a watch interruptto secure the oscillation stabilization wait time.

4. After the subclock has been stabilized, use bit9 and bit8 (CLKS1 and CLKS0 bits) of the clocksource register (CLKR) to switch the clock source from the main clock to subclock. If the clocksource is switched to the subclock before the subclock is stabilized, an unstable clock issupplied and subsequent operation is unpredictable. Be sure to switch to the subclock afterthe subclock has been stabilized.

For more information on the watch timer, see "3.13 Watch Timer".

102


Main Clock Oscillation Stabilization Wait Timer (for the Subclock Select)

The main clock oscillation stabilization wait timer is a 26-bit free-run timer that performsincremental counting in synchronization with the main clock. The operation of this timer is notaffected by the clock source selection or the clock divide-by rate.

The main clock oscillation stabilization wait timer is used to measure the main clock oscillationstabilization wait time.

Main clock oscillation can be controlled by bit0 (OSCDS1 bit) of the oscillation control register(OSCCR) while the device is operating on the subclock. This timer is used to measure theoscillation stabilization wait time when main clock oscillation is restarted after it has beenstopped.

Follow the procedure below for switching the clock source to the main clock when the device isoperating on the subclock with the main clock stopped.

1. Clear the main clock oscillation stabilization wait timer.

2. Set bit0 (OSCDS1 bit) of the oscillation control register (OSCCR) to 0 to start main clockoscillation.

3. Use the main clock oscillation stabilization wait timer to wait until the main clock oscillation isstabilized.

4. After the main clock has been stabilized, use bit9 and bit8 (CLKS1 and CLKS0 bits) of theclock source register (CLKR) to switch the clock source from the main clock to subclock. If theclock source is switched to the main clock before the main clock is stabilized, an unstableclock is supplied and subsequent operation is unpredictable. Be sure to switch to the mainclock after the main clock has been stabilized.

For more information on the main clock oscillation stabilization wait timer, see "3.14 Main ClockOscillation Stabilization Wait Timer".

Peripheral Stop Control

Peripheral stop control is used to control the clock supply to peripheral resources.

Power saving can be implemented by stopping the clock supply to peripheral resources not beingused.

For details, refer to Peripheral stop control.

103


3.12 Device State Control

This section describes the states of the MB91319 and their control.

Device State Control

3.12.1 Device States and State Transitions

3.12.2 Low-power Modes

104


3.12.1 Device States and State Transitions

This section describes device operating states and the transition between operating states.

Transition of Device States

Figure 3.12-1 shows the transition of device states.

105


Figure 3.12-1 Transition of Device States

Notes:

• To switch the clock source between the main clock and subclock, change the status of bit1 andbit0 (CLKS1 and CLKS0 bits) of the clock source register (CLKR) in the RUN state after oscillationof the switch-destination clock has been stabilized.

• To stop a circuit other than the watch timer in the watch state, set bit1 (OSCD2 bit) of the standbycontrol register (STCR) to 0 in the subclock RUN state then change to stop mode.

Main clock oscillation stabilization wait reset

Power-on

Setting initialization reset (INIT)

Program reset (RST)

Main clock RUNMain clock sleep

Main clock stop

Subclock RUNSubclock sleep

Subclock stop (watch state)

1

2

3

4

4

5

5

7

7

8

8

9

9

3

3

11

1

1

1

1

1

1

1

1

1

1

1

Main clock mode

Subclock mode

12

12345678910

11

1213

INTX pin = 0 (INIT)INTX pin = 1 (clearance of INIT state)End of oscillation stabilization wait timeRelease from reset (RST) stateSoftware reset (RST)Entry to sleep state (writing of instruction)Entry to stop state (writing of instruction)InterruptExternal interrupt not requiring a clockSwitching from main clock to subclock (writing of instruction)Switching from subclock to main clock (writing of instruction)Watchdog timer reset (INT)Entry to subclock sleep state (writing of instruction)

Highest

Lowest

Priority of state transition requestsSettings initialization reset (INIT) requestEnd of oscillation stabilization wait timeOperation initialization reset (RST) requestInterrupt requestStop mode requestSleep mode request

Oscillation stabilization wait RUN

Program reset (RST)Main clock sleep

12

13

10

6

106


RUN State (Normal Operation)

In the RUN state, a program is being executed. All internal clocks are supplied and all circuits areenabled.

For the 16-bit peripheral bus, however, only the bus clock is stopped, when it is not beingaccessed.

State transition request is accepted. If synchronous reset mode is selected, however, statetransition operations different from normal reset mode are used for some requests. For moreinformation, see "Synchronous Reset Operation" in "3.10.5 Reset Operation Modes".

Sleep State

In the sleep state, a program is stopped. Program operation causes a transition to this state.

Only execution of the program on the CPU is stopped; peripheral circuits are enabled. Theinstruction cache is stopped and the built-in memory modules and the internal and external busesare stopped unless the DMA controller issues a request.

If a valid interrupt request occurs, the state is cleared and the RUN state (normal operation) isentered.

If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)state is entered.

If an operation initialization reset (RST) request occurs, the operation initialization reset (RST)state is entered.

Stop State

In the stop state, the device is stopped. Program operation causes a transition to this state.

All internal circuits are stopped. All internal clocks are stopped and the oscillation circuit and PLLcan be stopped if set to do so.

In addition, the external pins (except some) can be set to high impedance via settings.

If a specific valid interrupt request (no clock required) occurs, the oscillation stabilization waitRUN state is entered.

If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)state is entered.

If an operation initialization reset (RST) request occurs, the oscillation stabilization wait reset(RST) state is entered.

107


Oscillation Stabilization Wait RUN State

In the oscillation stabilization wait RUN state, the device is stopped. This state occurs after areturn from the stop state.

All internal circuits except the clock generation controller (time base counter and device statecontroller) are stopped. All internal clocks are stopped, but the oscillation circuit and the PLL thathas been enabled are running.

High impedance control of external pins in the stop or other state is cleared.

If the specified oscillation stabilization wait time elapses, the RUN state (normal operation) isentered.

If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) stateis entered.

If an operation initialization reset (RST) request occurs, the oscillation stabilization wait reset(RST) state is entered.

Oscillation Stabilization Wait Reset (RST) Status

In the oscillation stabilization wait reset (RST) state, the device is stopped. This state occursafter a return from the stop state or the settings initialization reset (INIT) state. All internal circuitsexcept the clock generation controller (time base counter and device state controller) arestopped. All internal clocks are stopped, but the oscillation circuit and the PLL that has beenenabled are running.

• High impedance control of external pins in the stop state, etc., is cleared.

• An operation initialization reset (RST) is output to the internal circuits.

• If the specified oscillation stabilization wait time elapses, the oscillation stabilization wait reset(RST) state is entered.

• If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) stateis entered.

Operation Initialization Reset (RST) State

In the operation initialization reset (RST) state, a program is initialized. This state occurs if anoperation initialization reset (RST) request is accepted or the oscillation stabilization wait reset(RST) state is ended.

Execution of a program on the CPU is stopped and the program counter is initialized. Mostperipheral circuits are initialized. All internal clocks are stopped, but the oscillation circuit and thePLL that has been enabled are running.

• An operation initialization reset (RST) is output to the internal circuits.

• If an operation initialization reset (RST) no longer exists, the RUN state (normal operation) isentered and the operation initialization reset sequence is executed. After a return from thesettings initialization reset (INIT), the settings initialization reset sequence is executed.

• If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) stateis entered.

108


Settings Initialization Reset (INIT) State

In the settings initialization reset (INIT) state, all settings are initialized. This state occurs if asettings initialization reset (INIT) is accepted or the hardware standby state is ended.

Execution of a program on the CPU is stopped and the program counter is initialized. Allperipheral circuits are initialized. The oscillation circuit runs, but the PLL stops running. Allinternal clocks are stopped while the L level is input to the external INIT pin; otherwise, they run.

• A settings initialization reset (INIT) and an operation initialization reset (RST) are output to theinternal circuits.

• If a settings initialization reset (INIT) no longer exists, the state is cleared and the oscillationstabilization wait reset (RST) state is entered. Then, the operation initialization reset (RST)state is entered and the settings initialization reset sequence is executed.

Priority of State Transition Requests

In any state, state transition requests conform to the priority listed below. However, somerequests that occur only in a specific state are valid only in that state.

[Highest] Settings initialization reset (INIT) request

Hardware standby request

End of oscillation stabilization wait time (occurs only in the oscillation stabilization wait reset state and the oscillation stabilization wait RUN state)

Operation initialization reset (RST) request

Valid interrupt request (occurs only in the RUN, sleep, and stop states)

[Lowest] Stop mode request (writing to a register) (occurs only in the RUN state)

109


3.12.2 Low-power Modes

This section describes the low-power modes, some MB91319 states, and how to use the low-power modes.

Low-power Modes

The MB91319 has the following two low-power modes:

• Sleep mode: The device enters the sleep state due to writing to a register.

• Stop mode: The device enters the stop state due to writing to a register.

These modes are described below.

Sleep mode

If 1 is set for bit6 (SLEEP bit) of the standby control register (STCR), sleep mode is initiated andthe device enters the sleep state. The sleep state is maintained until a source for return from thesleep state is generated.

If 1 is set for both bit7 (STOP bit) and bit6 of the standby control register (STCR), bit7 (STOP bit)has precedence and the device enters the stop state.

For more information about the sleep state, see "Sleep State" in "3.12.1 Device States andState Transitions".

[Circus that stop in the sleep state]

• Program execution on the CPU

• Data cache

• Bit search module (enabled if DMA transfer occurs)

• Various built-in memory (enabled if DMA transfer occurs)

• Internal types of and external buses (enabled if DMA transfer occurs)

[Circuits that do not stop in the sleep state]

• Oscillation circuit

• PLL that has been enabled

• Clock generation controller

• Interrupt controller

• Peripheral circuit

• DMA controller

• DSU

110


[Sources of return from the sleep state]

• Generation of a valid interrupt request

If an interrupt request with an interrupt level other than interrupt disabled (1FH) occurs, sleepmode is cleared and the RUN state (normal operation state) is entered.

To prevent sleep mode from being cleared even when an interrupt request occurs, setinterrupt disabled (1FH) as the interrupt level in the corresponding ICR.

• Generation of a settings initialization reset (INIT) request

If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) stateis unconditionally entered.

• Generation of an operation initialization reset (RST)

If an operation initialization reset (RST) occurs, the operation initialization reset (RST) state isunconditionally entered.

For information about the priority of sources, see "Priority of State Transition Requests" in"3.12.1 Device States and State Transitions".

Stop mode

If 1 is set for bit7 (STOP bit) of the standby control register (STCR), stop mode is initiated and thedevice enters the stop state. The stop state is maintained until a source for return from the stopstate occurs.

If 1 is set for both bit6 (SLEEP bit) and bit7 bit of the standby control register (STCR), bit7 (STOPbit) has precedence and the device enters the stop state.

For more information about the stop state, see "Stop State" in "3.12.1 Device States and StateTransitions".

[Circuits that stop in the stop state]

• Oscillation circuits set to stop

If 1 is set for bit1 (OSCD2 bit) of the standby control register (STCR), the subclock oscillationcircuit in the stop state is stopped. If 1 is set for bit0 (OSCD1 bit) of the standby controlregister (STCR), the main clock oscillation circuit in the stop state is stopped.

• PLL connected to the oscillation circuit that is either disabled or set to stop

If 1 is set for bit1 (OSCD2 bit) of the standby control register (STCR) and 1 is set for bit11(PLL2EN bit) of the clock source control register (CLKR), the subclock PLL in the stop state isstopped. If 1 is set for bit0 (OSCD1 bit) of the standby control register (STCR) and 1 is set forbit10 (PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stopstate is stopped.

• All internal circuits except those, described below, that do not stop in the stop state

111


[Circuits that do not stop in the stop state]

• Oscillation circuits that are set not to stop

• If 0 is set for bit1 (OSCD2 bit) of the standby control register (STCR), the subclockoscillation circuit in the stop state is not stopped.

• If 0 is set for bit0 (OSCD1 bit) of the standby control register (STCR), the main clockoscillation circuit in the stop state is not stopped.

• PLL connected to the oscillation circuit that is enabled and is not set to stop

• If 0 is set for bit1 (OSCD2 bit) of the standby control register (STCR) and 1 is set for bit11(PLL2EN bit) of the clock source control register (CLKR), the subclock PLL in the stop stateis not stopped.

• If 0 is set for bit0 (OSCD1 bit) of the standby control register (STCR) and 1 is set for bit10(PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stopstate is not stopped.

[High impedance control of a pin in the stop state]

If 1 is set for bit5 (HIZ bit) of the standby control register (STCR), the output of a pin in the stopstate is set to the high impedance state.

See "APPENDIX H Pin State List" for the pins subject this type of control.

If bit5 (HIZ bit) of the standby control register (STCR) is set to 0, the pin outputs in the stop statemaintain the values set before transition to the stop state.

For details see "APPENDIX H Pin State List".

[Sources of return from the stop state]

• Generation of a specific valid interrupt request (not requiring a clock)

Only the external interrupt input pins (INTn pins), main clock oscillation stabilization wait timerinterrupt during main clock oscillation, and watch interrupt during subclock oscillation areenabled.

If an interrupt request with an interrupt level other than interrupt disabled (1FH) occurs, stopmode is cleared and the RUN state (normal operation state) is entered.

To prevent stop mode from being cleared even when an interrupt request occurs, set interruptdisabled (1FH) as the interrupt level in the corresponding ICR.

• Generation of a settings initialization reset (INIT) request

If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) isunconditionally entered.

• Generation of an operation initialization reset (RST)

If an operation initialization reset (RST) occurs, the operation initialization reset (RST) isunconditionally entered.

For information about the priority of sources, see "Priority of State Transition Requests"" in"3.12.1 Device States and State Transitions".

[Selecting a clock source in stop mode]

Select the main clock divided by 2 as the source clock before setting stop mode. For moreinformation, see "3.11 Clock Generation Control" especially Section "3.11.1 PLL Controls".

The same limitations as in the normal operation apply to the setting of a divide-by rate.

112


[Normal and synchronous standby operations]

If 1 is set for bit8 (SYNCS bit) of the time base counter control register (TBCR), synchronousstandby operation is enabled. In this case, simply writing to the STOP bit does not cause atransition to the stop state. Instead, writing to the STOP bit and then reading the STCR registercauses a transition to the stop state. If 0 is set for the SYNCS bit, normal standby operation isselected. In this case, simply writing to the STOP bit causes a transition to the stop state.

If, in normal standby operation, the value set for the divide-by rate of the peripheral clock (CLKP)is larger than the CPU clock (CLKB), many instructions are executed before writing to the STOPbit actually occurs. Thus, after the write instruction to the STOP bit, the same number of NOPinstructions as 5 + (CPU clock divide-by rate/peripheral clock divide-by rate) instructions ormore must be inserted. Otherwise, subsequent instructions are executed before the transition tothe stop state.

In synchronous standby operation, the stop state occurs only after writing to the STOP bit actuallyoccurs and the reading of STCR register are completed. This is because the CPU uses the busuntil the value read from the STCR register is stored into the CPU. Thus, in any setting ofrelationship between divide-by rates of the CPU clock (CLKB) and the peripheral clock (CLKP),insert only two NOP instructions after the write instruction for the STOP bit and the readinstruction for the STCR register to prevent any subsequent instructions from being executedbefore transition to the stop state.

113


3.13 Watch Timer

The watch timer is a 15-bit free-run timer that performs incremental counting in synchronization with the subclock. The watch timer has an interval timer function to generate interrupts repeatedly at fixed time intervals.The internal time can be selected from four types as follow.

Low-power Modes

Subclock cycle Interval time

1/FCL (about 30.5 µs)• FCL indicates the subclock oscillation frequency.

210FCL (31.25ms)

213FCL (0.25s)

214FCL (0.50s)

215FCL (1.00s)

114


Block Diagram

Figure 3.13-1 shows the block diagram of the watch timer.

Figure 3.13-1 Block Diagram of the Watch Timer

Watch timer

The watch timer is a 15-bit incremental counter that uses the subclock source oscillation as thecount clock.

Counter clear circuit

The counter clear circuit clears the counter not only when the WCL bit of the WPCR register is setto 0 but also when a reset (INIT) request is generated.

Interval timer selector

The interval timer selector selects one of the four frequency-divide outputs of the watch timercounter for the interval timer. The trailing edge of the selected frequency-divide output becomesan interrupt source.

Watch timer control register (WPCR)

The watch timer control register is used to select the interval time, clear the counter, controlinterrupts, and check the counter status.

215 214 213 212 211 210 29 28 27 26 25 24 23 22 21

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


(31.25ms)

(0.25s)

(0.50s)

(1.00s)

WIF WIE WS1 WS0 WCL


FCL

Watch timer control register (WPCR)

Reset (INIT)

Watch timer counter

Watch timer interrupt

FCL: Subclock source oscillationThe numbers in parentheses indicate the intervals when the subclock source oscillation frequency is 32.768 kHz.

115


Watch Timer Control Register

Figure 3.13-2 shows the bit configuration of the watch timer control register.

Figure 3.13-2 Bit Configuration of Watch Timer Control Register

[bit15] WIF (watch timer interrupt flag)

This bit is the watch timer interrupt flag.

This bit is set to 1 at the trailing edge of the selected frequency-divide output for the intervaltimer.

If this bit and the watch timer interrupt enable bit are 1, a watch timer interrupt request isoutput.

• This bit is cleared to 0 by a reset (INIT) request.

• Data can be written to and read from this bit. However, only 0 can be written. If an attempt ismade to write 1 to this bit, its value is not changed.

• If a read modify write instruction is issued, 1 is always read from this bit.

[bit14] WIE (watch timer interrupt enable)

This bit enables or disables the interrupt request output to the CPU. If this bit and the watchtimer interrupt flag bit are 1, a watch timer interrupt request is output.


• Data can be written to and read from this bit.


These bits are reserved. When writing data to these bits, be sure to write 0. (Writing of 1 tothese bits is prohibited.)

Data read from these bits is undefined.

Initial value WPCR 15 14 13 12 11 10 9 8 At INIT At RST Access0000 048C H WIF WIE WS1 WS0 WCL 00 xx R/W

R/W R/W R/W R/W W H

H

0 Watch timer interrupt not requested (default value)

1 Watch timer interrupt requested

0 Output of watch timer interrupt request disabled (default value)

1 Output of watch timer interrupt request disabled

116


[bit10, bit9] WS1, WS0 (watch timer interval select 1, 0)

These bits select the interval of the interval timer.

One of the following four intervals is selected according to the output bits of the watch timercounter:

• These bits are cleared to 00 by a reset (INIT) request.

• Data can be written to and read from these bits.

[bit8] WCL (watch timer clear)

Writing 0 to this bit clears the watch timer to 0.

• Only 0 can be written to this bit. Writing 1 to this bit does not affect timer operation.

• The value read from this bit is always 1.

Watch Timer Interrupt

If the set interval time elapses while the watch timer counter is counting with the subclock, thewatch timer interrupt flag (WIF) is set to 1. Then, if the watch timer interrupt enable bit (WIE) hasbeen set to 1 (interrupt output enabled), an interrupt request is output to the CPU. Note thatwatch interrupts do not occur when subclock oscillation is stopped (see the next Item,"Operation of Interval Timer Function") because counting is stopped when the subclock isstopped.

To clear an interrupt request, write 0 to the WIF bit using the interrupt processing routine. Notethat the WIF bit is set to 1 at the trailing edge of the selected frequency-divide output regardlessof the value of the WIE bit.

Note:

The WIF and WCL bits must be cleared to 0 (WIF=WCL=0) at the same time if watch timer interruptrequest output is to be enabled (WIE = 1) or the value of the WS1 and WS0 bits are to be changedafter release from the reset state.

Reference:

• If the WIE bit is changed from 0 to 1 to enable interrupt output when the WIF bit is 1, an interruptrequest is output immediately.

• If a counter clear (WCL bit of WPCR is 1) and overflow of selected bits occur at the same time,the WIF bit is not set to 1.

WS1 WS0 Interval timer interval (at FCL = 32.768 kHz)

0 0 210/FCL (31.25 ms) (default value)

0 1 213/FCL (0.25s)

1 0 214/FCL (0.50s)

1 1 215/FCL (1.00s)

117


Operation of Interval Timer Function

The watch timer counter continues incremental counting while the subclock is running. Whensubclock oscillation stops, counting stops in the following cases:

• Counting stops when bit11 (PLL2EN) of the clock source register (CLKR) is 0.

On the MB31319, the PLL2EN is cleared to 0 at reset by an INIT request. To use the watchtimer, write 1 to the PLL2IN bit to start subclock oscillation.

• Counting is stopped throughout stop mode if the MB31319 is put into stop mode by stoppingsubclock oscillation with bit1 [OSCD2 bit] of the standby control register [STCR] set to 1. Tomake the watch timer operate in stop mode, set the OSCD2 bit to 0 before entry to thestandby state, because the OSCD2 bit is initialized to 1 at reset by an INIT request.

If the counter is cleared (WCL bit is cleared to 0), the counter starts counting from 0000H.When the count reaches 7FFFH, the counter restarts counting from 0000H. When the trailingedge of the frequency-divide output selected for the interval timer is detected, the watch timerinterrupt flag (WIF) bit is set to 1. In other words, a watch timer interrupt request is generatedat the selected intervals on the basis of the selected interval time.

Operation of Clock Supply Function

The MB91319 uses a time base counter to secure the oscillation stabilization wait time after INITor stop mode. On the other hand, the MB91319 uses the watch timer to secure the subclockoscillation stabilization wait time while the main clock is selected as the clock source. This isbecause the watch timer operates with the subclock regardless of clock source selection.

Follow the procedure below to perform subclock oscillation stabilization wait operation while theMB91319 is operating on the main clock:

1. Set the interval time for the watch timer to 1 second (when FCL = 32.768 kHz), and clear thecounter to 0 (by writing 11 to the WS1 and WS0 bits and 0 to the WCL bit).If it is necessary to perform processing after the end of the oscillation stabilization wait with aninterrupt, initialize the interrupt flag (by writing 0 to the WIF bit and 1 to WIE bit).

2. Start subclock oscillation (by writing 1 to bit11 [PLL2EN bit] of CLKR).

3. In the program, wait until the WIF bit is set to 1.

4. Make sure that the WIF bit has been set to 1, then perform the processing to be done after theend of the oscillation stabilization wait. If interrupts are enabled, an interrupt is generatedwhen the WIF bit is set to 1. Then, perform the processing to be done after the end of theoscillation stabilization wait by an interrupt routine. If it is necessary to switch the clock sourcefrom the main clock to subclock, switch the clock source after making sure that the WIF bit hasbeen set to 1 as described above. (If the clock source is switched to the subclock beforesubclock oscillation is stabilized, unstable clock is supplied to the entire device andsubsequent operation is unpredictable.)

118


Operation of The Watch Timer

Figure 3.13-3 shows the counter states at start of watch timer, switching to the subclock, andtransition to stop mode during operation with the subclock.

Figure 3.13-3 Counter States at Transition to Stop Mode

Precautions for Using the Watch Timer

• Use the oscillation stabilization wait time as a reference value because the oscillation cycle isunstable immediately after oscillation is started.

• No timer interrupt is generated while subclock oscillation is stopped because the watch timeris stopped when subclock oscillation is stopped. Do not stop subclock oscillation if it isnecessary to use the watch timer for processing.

• If a WIF setting request occurs at the same time as a zero-clearance request from the CPU,the WIF setting request has priority and the zero-clearance request is ignored.

Main clock Subclock

- Timer clearance (WCL bit = 1) (other than 0)- Timer interval selection (WS1 and WS0 bits = 11B)- Start of subclock oscillation (PLL2EN bit of CLKR = 1)

Cleared by interrupt routine

Subclock oscillation stabilization wait time

Interval time

7FFF H

4000 H

WIF

Clock source

Clock modeRUN RUN

Stop *

- Change of interval time (WS1 and WS0 bits = 10B)- Switching from main clock to subclock

* When the OSCD2 bit of STCR is set to 0 (oscillation is not stopped in stop mode)

Value of counter

Instruction to enter stop mode

119


3.14 Main Clock Oscillation Stabilization Wait Timer

The main clock oscillation stabilization wait timer is a 23-bit free-run timer that performs incremental counting in synchronization with the main clock. The main clock oscillation stabilization wait timer has an interval timer function to generate interrupts repeatedly at fixed time intervals. This timer is used to secure main clock oscillation stabilization wait time when main clock oscillation is restarted after it has been stopped by setting bit0 (OSCDS1) of the oscillation control register (OSCCR) during operation with the subclock.The interval time can be selected from three types as follow.

Main Clock Oscillation Stabilization Wait Timer

Table 3.14-1 Time Intervals for Main Clock Oscillation Stabilization Wate Timer

Main clock interval Interval time

1/FCL (about 80 ns)• FCL indicates the main clock oscillation frequency.

212/FCL (470 µs)

217/FCL (13.1 ms)

223/FCL (839 ms)

120


Block Diagram

Figure 3.14-1 Block Diagram of the Main Clock Oscillation Stabilization Wait Timer

Main clock oscillation stabilization wait timer

The main clock oscillation stabilization wait timer is a 32-bit incremental counter that uses themain clock source oscillation as the count clock.


The counter clear circuit clears the counter not only when the WCL bit of the OSCR register is setto 0 but also when a reset (INIT) request is generated.


The interval timer selector selects one of the three frequency-divide outputs of the main clockoscillation stabilization wait timer counter for the interval timer. The trailing edge of the selectedfrequency-divide output becomes an interrupt source.

Main clock oscillation stabilization wait timer control register (OSCR)

The main clock oscillation stabilization wait timer control register is used to select the intervaltime, clear the counter, control interrupts, and check counter status.

223217 21229 28 27 26 25 24 23 22 21

22 16 11 8 7 6 5 4 3 2 1 0


(410µs)

(13.1ms) (839ms)

WIF WIE WS1 WS0 WCL


FCL

Main clock oscillation stabilization wait timer interrupt request

Main clock oscillation stabilization wait timer control register (OSCR)

FCL: Main clock source oscillationThe numbers in parentheses indicate the intervalswhen the main clock source oscillation frequency is 10 MHz.

Reset (INIT)

Main clock oscillation stabilization wait timer counter

121


Main Clock Oscillation Stabilization Wait Timer Control Register

Figure 3.14-2 shows the bit configuration of the main clock oscillation stabilization wait timercontrol register.

Figure 3.14-2 Bit Configuration of Main Clock Oscillation Stabilization Wait Timer Control Register

[bit15] WIF (watch timer interrupt flag)

This bit is the main clock oscillation stabilization wait timer interrupt flag.

This bit is set to 1 at the trailing edge of the selected divided output for the interval timer.

If this bit and the main clock oscillation stabilization wait timer interrupt enable bit are 1, a mainclock oscillation stabilization wait timer interrupt request is output.


• Data can be written to and read from this bit. However, only 0 can be written. If an attempt ismade to write 1 to this bit, its value is not changed.

• If a read modify write instruction is issued, 1 is always read from this bit.

[bit14] WIE (watch timer interrupt enable)

This bit enables or disables the interrupt request output to the CPU. If this bit and main clockoscillation stabilization wait timer interrupt flag bit are 1, a main clock oscillation stabilizationwait timer interrupt request is output.


• Data can be written to and read from this bit.


These bits are reserved. When writing data to these bits, be sure to write 0 to these bits.(Writing of 1 to these bits is prohibited.)

Data read from these bits are undefined.

Initial value OSCR 15 14 13 12 11 10 9 8 At INIT At RST Access0000 0490H WIF WIE WS1 WS0 WCL 00 xx R/W

R/W R/W R/W R/W W H H

0Main clock oscillation stabilization wait timer interrupt not requested (default value)

1Main clock oscillation stabilization wait timer interrupt requested

0Output of main clock oscillation stabilization wait timer interrupt request disabled (default value)

1Output of main clock oscillation stabilization wait timer interrupt request disabled

122


[bit10, bit9] WS1, WS0 (watch timer interval select 1, 0)

These bits select the interval of the interval timer.

One of the following three intervals is selected according to the output bits of the main clockoscillation stabilization wait timer counter:

• These bits are cleared to 00 by a reset (INIT) request.

• Data can be written to and read from these bits.

[bit8] WCL (watch timer clear)

Writing 0 to this bit clears the main clock oscillation stabilization wait timer to 0.

• Only 0 can be written to this bit. Writing 1 to this bit does not affect timer operation.

• The value read from this bit is always 1.

Main Clock Oscillation Stabilization Wait Timer Interrupt

If the set interval time elapses while the main clock oscillation stabilization wait timer counter iscounting with the main clock, the main clock oscillation stabilization wait timer interrupt flag (WIF)is set to 1. Then, if the main clock oscillation stabilization wait timer interrupt enable bit (WIE) isset to 1 (interrupt output is enabled), an interrupt request is output to the CPU. Note that watchinterrupts do not occur when main clock oscillation is stopped (see the next Item, "Operation ofInterval Timer Function") because counting is stopped when the main clock is stopped.

To clear an interrupt request, write 0 to the WIF bit by the interrupt processing routine. Note thatthe WIF bit is set to 1 at the trailing edge of the selected frequency-divide output regardless of thevalue of the WIE bit.

Note:

The WIF and WCL bits must be cleared to 0 (WIF=WCL=0) at the same time if main clock oscillationstabilization wait timer interrupt output is to be enabled (WIE = 1) or the value of the WS1 and WS0bits are to be changed after release from the reset state.

Reference:

• If the WIE bit is changed from 0 to 1 to enable interrupt output when the WIF bit is 1, an interruptrequest is output immediately.

• If a counter clear (WCL bit of WPCR is 1) and overflow of selected bits occur at the same time,the WIF bit is not set to 1.

WS1 WS0 Interval timer interval (at FCL = 10 MHz)

0 0 Setting prohibited

0 1 212/FCL (410 µs) (default value)

1 0 217/FCL (13.1 ms)

1 1 223/FCL (839 ms)

123


Operation of Interval Timer Function

The main clock oscillation stabilization wait timer counter continues incremental counting whilethe main clock is oscillated. When main clock oscillation stops, counting stops in the followingcase:

• Counting is stopped throughout stop mode if the MB31319 is put into stop mode by stoppingsubclock oscillation with bit0 [OSCD1 bit] of the standby control register [STCR] set to 1. Tomake the main clock oscillation stabilization wait timer operate in stop mode, set the OSCD2bit to 0 before entry into the standby state because the OSCD1 bit is initialized to 1 at reset byan INIT request.

If the counter is cleared (WCL bit is cleared to 0), the counter starts counting from 0000H. Whenthe count reaches 7FFFH, the counter restarts counting from 0000H. If the trailing edge of thefrequency-divide output selected for the interval timer is detected, the main clock oscillationstabilization wait timer interrupt flag (WIF) bit is set to 1. In other words, a main clock oscillationstabilization wait timer interrupt request is generated at the selected intervals on the basis of theselected interval time.

Operation of Clock Supply Function

The MB91319 uses a time base counter to secure the oscillation stabilization wait time after INITor stop mode. On the other hand, the MB91319 uses the main clock oscillation stabilization waittimer to secure the main clock oscillation stabilization wait time while the subclock is selected asthe clock source. This is because the main clock oscillation stabilization wait timer operates onthe main clock regardless of the clock source selection.

Follow the procedure below to perform main clock oscillation stabilization wait operation while theMB91319 is operating on the subclock:

1. Set the time required for main clock oscillation stabilization with the WT1 and WT0 bits, andclear the counter to 0 (by writing the oscillation stabilization wait time to the WS1 and WS0 bitsand 0 to the WCL bit).If it is necessary to perform processing after the end of oscillation stabilization wait with aninterrupt, initialize the interrupt flag (by writing 0 to the WIF and WIE bits).

2. Start main clock oscillation (by writing 1 to bit0 [OCSDS1 bit] of OSCR).

3. In the program, wait until the WIF bit is set to 1.

4. Make sure that the WIF bit has been set to 1, then perform the processing to be done after theend of oscillation stabilization wait. If interrupts are enabled, an interrupt is generated whenthe WIF bit is set to 1. Then, perform the processing to be done after the end of oscillationstabilization wait by an interrupt routine. If it is necessary to switch the clock source from thesubclock to main clock, switch the clock source after making sure that the "4." WIF bit has been set to 1 as described above. (If the clock source is switched to the mainclock before main clock oscillation is stabilized, an unstable clock is supplied to the entiredevice and subsequent operation is unpredictable.)

124


Operation of the Main Clock Oscillation Stabilization Wait Timer

Figure 3.14-3 shows the counter states at the start of the main clock oscillation stabilization waittime and switching to the main clock.

Figure 3.14-3 Counter States at Switching to the Main Clock

Precautions on Using the Main Clock Oscillation Stabilization Wait Timer

• Use the oscillation stabilization wait time as a reference value, because the oscillation cycle isunstable immediately after oscillation is started.

• No timer interrupt is generated while main clock oscillation is stopped, because the main clockoscillation stabilization wait timer is stopped when main clock oscillation is stopped. Do notstop main clock oscillation if it is necessary to use the main clock oscillation stabilization waittimer for processing.

• If a WIF setting request occurs at the same time as a zero-clearance request from the CPU,the WIF setting request has priority and the zero-clearance request is ignored.

Subclock Main clock

- Timer clearance (WCL bit = 1) (other than 0)- Timer interval selection (WS1 and WS0 bits = 11B)

- Start of main clock oscillation

(OSCDS1 bit of OSCR = 0)

Cleared by interrupt routine

Main clock oscillation stabilization wait time

H

WIF (interrupt request)

WIE (interrupt mask)

Clock mode

- Switching from subclock to main clock

7 FFFFF

Value of counter

125


126

CHAPTER 4I/O PORT

This chapter describes the I/O ports and the configuration and functions of registers.

4.1 Overview of the I/O Port

4.2 I/O Port Registers

127

CHAPTER 4 I/O PORT

4.1 Overview of the I/O Port

This section provides an overview of the I/O port.

Basic Block Diagram of the I/O Port

The pins of this LSI device can be used as I/O ports if settings are made so that thecorresponding pins are not used for the inputs and outputs of the peripheral circuits.

Figure 4.1-1 shows the basic configuration of the port.

Figure 4.1-1 Basic Block Diagram of the I/O Port

The I/O port consists of PDRs (Port Data Registers), DDRs (Data Direction Registers), and PFRs(Port Function Registers).

0

1

1

0

PDR: Port Data RegisterDDR: Data Drection RegisterPFR: Port Function Register

Pin

PDR

Peripheral output

Peripheral output

PFR

DDR

Port Bus

128

CHAPTER 4 I/O PORT

I/O Port Modes

The I/O port has the following four modes:

Port input mode (PFR=0 & DDR=0)

• PDR read: Reads the level of the corresponding external pin.

• PDR write: Writes a setting value to the PDR.

Port output mode (PFR= 0 & DDR=1)

• PDR read: Reads the value of the PDR.

• PDR write: Outputs the value of the PDR to the corresponding external pin.

Peripheral output mode (PFR=1 & DDR=1)



Peripheral input mode (PFR=1 & DDR=0)



Note:

Port-related registers must be accessed in units of bytes.

The value of DDR becomes valid when the value of PFR is changed to switch the pin to a general-purpose pin.

129

CHAPTER 4 I/O PORT

4.2 I/O Port Registers

This section describes the configuration and functions of the I/O port registers.

Configuration of the Port Data Registers (PDR)

Figure 4.2-1 shows the configuration of the port data registers (PDRs).

Figure 4.2-1 Configuration of the Port Data Registers (PDR)

PDR0 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000010H P07 P06 P05 P04 P03 P02 P01 P00 XXXXXXXXB R/W


PDR2 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000012H P27

P37

P26 P25 P24 P23 P22 P21 P20 XXXXXXXXB R/W

PDR3 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000013H P36 P35 P34 P33 P32 P31 P30 XXXXXXXXB R/W


PDR5 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000015H P57 P56

P87

P97

P86

P55 P54 P53 P52 P51 P50 XXXXXXXXB R/W

PDR7 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000017H - - -

- - - - -

P74 P73 P72 P71 P70 --XXXXXXB R/W

PDR8 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000018H P85 P84 P83 P82 P81 P80 XXXXXXXXB R/W

PDR9 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000019H P96 P95 P94 P93 P92 P91 P90 XXXXXXXXB R/W

PDRA 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000001AH PA2 PA1 PA0 -----XXXB R/W

PDRB 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000001BH PB7 PB6

PC7 PC6

PB5 PB4 PB3 PB2 PB1 PB0 XXXXXXXXB R/W

PDRC 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000001CH PC5 PC4 PC3 PC2 PC1 PC0 XXXXXXXXB R/W

PDR0 to PDR7 is input/output data register of the I/O prot.Input/output control is performed using the corresponding DDR0 to DDR7 and PFR0 to PFR4.

130

CHAPTER 4 I/O PORT

Configuration of the Data Direction Registers (DDR)

Figure 4.2-2 shows the configuration of the data direction registers (DDRs).

Figure 4.2-2 Configuration of the Data Direction Registers (DDR)

DDR0 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000400H P07 P06 P05 P04 P03 P02 P01 P00 00000000B R/W


DDR2 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000402H P27

P37

P26 P25 P24 P23 P22 P21 P20 00000000B R/W

DDR3 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000403H P36 P35 P34 P33 P32 P31 P30 00000000B R/W


DDR5 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000405H P57 P56

P87

P97

P86

P55 P54 P53 P52 P51 P50 00000000B R/W

DDR7 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000407H - - -

- - - - -

P74 P73 P72 P71 P70 ---00000B R/W

DDR8 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000408H P85 P84 P83 P82 P81 P80 00000000B R/W

DDR9 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000409H P96 P95 P94 P93 P92 P91 P90 00000000B R/W

DDRA 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000040AH PA2 PA1 PA0 -----000B R/W

DDRB 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000040BH PB7 PB6

PC7 PC6

PB5 PB4 PB3 PB2 PB1 PB0 00000000B R/W

DDRC 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000040CH PC5 PC4 PC3 PC2 PC1 PC0 00000000B R/W

For DDR0 to DDR7, input-output direction of the corresponding I/O port is controlled bit-wise.When PFR=0 DDR=0: Port input

DDR=1: Port outputWhen PFR=1 DDR=0: Peripheral input

DDR=1: Peripheral output

131

CHAPTER 4 I/O PORT

Configuration of the Port Function Registers (PFR)

Figure 4.2-3 shows the configuration of the port function registers (PFRs).

Figure 4.2-3 Configuration of the Data Direction Registers (PFR)PFR0 7 6 5 4 3 2 1 0 Initial value Access

Address: 00000410H I2CTST - - I2CE4 I2CE3 I2CE2 I2CE1 I2CE0

UART3SCKE3UART2SCKE2 UART1SCKE1UART0SCKE0

TME3 TME2 TME1 TME0 PPGE3

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

ReservedReservedReservedReserved

PPGE2PPGE1PPGE0

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

- - - I2CBRG

TOE2 TOE1 TOE0 - - - UART4SCKE4

0--00000B R/W

PFR1 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000411H 00000000B R/W

PFR2 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000412H 000---00B R/W


PFR4 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000414H 0000--00B R/W


R/WPFR6 7 6 5 4 3 2 1 0 Initial value Access

Address: 00000416H 11111111B




PFRA 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000041AH 11111111B R/W

PFRB 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000041BH 11111111B R/W

PFRC 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000041CH 1111---1B R/W

PFRD 7 6 5 4 3 2 1 0 Initial value AccessAddress: 0000041DH

During reset, port function is selected.For PFR0 to PFR3, the corresponding peripheral output is controlled by function.Port for peripheral input should be configured as an input port by DDR register.*Set 0 to PFR0 bit 7 [I2CTST]*Set 00H to PFR4 [Reserved]

When both I2CE3 and I2CE4 are 1, SCL3/SDA3 is bridged to SCL4/SDA4.When I2CBRG is 1, SCL2/SDA2 is bridged to SCL3/SDA3.

---10111B R/W

ADE9 ADE8

132

CHAPTER 4 I/O PORT

Initial Values and Functions of the Port Function Registers (PFRs)

Table 4.2-1 lists the initial values and functions of the port function registers (PFRs).

Table 4.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (1 / 4)

Register name Bit name Bit value Function

PFR0I2CTST

0 I2C test bit

1 Setting prohibited

I2CE40 General-purpose port

1 SCL4 or SDA4 port (connected to I2C channel 3)









133

CHAPTER 4 I/O PORT

PFR1UART3

0 General-purpose port

1 S03 output

SCKE30 General-purpose port

1 SCK3 output

UART2 0 General-purpose port

1 S02 output

SCKE2 0 General-purpose port

1 SCK2 output


1 S01 output


1 SCK1 output


1 S00 output


1 SCK0 output


1 S04 output


1 SCK4 output

PFR2 UART4 0 General-purpose port

1 S04 output


1 SCK4 output

TOE2 0 General-purpose port

1 T02 output


1 T01 output


1 T00 output



134

CHAPTER 4 I/O PORT

PFR3 TME3 0 General-purpose port

1 TMO2 output

TME2 0 General-purpose port

1 TMO2 output


1 TMO1 output


1 TMO0 output

PPGE3 0 General-purpose port

1 PPG3 output


1 PPG2 output


1 PPG1 output


1 PPG0 output

PFR4 ADE9 0 General-purpose port

1 Function as AN9 input

ADE8 0 General-purpose port

1 Function as AN8 input



135

CHAPTER 4 I/O PORT

PFR5 ADE7 0 Function as general-purpose port.

1 Function as AN7 input.

ADE6 0 Function as general-purpose port.














PFRD I2CBRG 0 2ch and 3ch of I2C is not connected.

1 2ch and 3ch of I2C is connected.



136

CHAPTER 516-BIT RELOAD TIMER

This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation.

5.1 Overview of the 16-bit Reload Timer

5.2 16-bit Reload Timer Registers

5.3 16-bit Reload Timer Operation

137

CHAPTER 5 16-BIT RELOAD TIMER

5.1 Overview of the 16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating an internal count clock, and a control register.

Overview of the 16-bit Reload TimerThe MB91319 series has three built-in channels, numbered 0 to 2, for the 16-bit reload timer.

Channels 0 and 1 support the activation of DMA transfers resulting from interrupts.

The input clock can be selected from three internal clocks (machine clock divided by 2, 8, and 32)and an external clock.

The output pin (TOUT) outputs a toggle output waveform whenever an underflow occurs in reloadmode and outputs a square wave that indicates that counting is in progress in one-shot mode.

The input pin (TIN) can be used as the event input in external event count mode and as thetrigger or gate input in internal clock mode.

The external event count function, when used in reload mode, can be used as a divider forexternal clock mode.

Block DiagramFigure 5.1-1 is a block diagram of the 16-bit reload timer.

Figure 5.1-1 Block Diagram of the 16-bit Reload Timer

3

3

2 2

2

16

8

16

R-

bus

16-bit down counter UF

16-bit reload register

ReloadRELD

GATE IRQ

EXCK

CSL0CSL1

MOD0MOD1

TRGCNTEUFINTEOUTLOUTE

OUTCTL.

MOD2Internal clock

Prescaler clear

Clock selector

IN CTL.

Port (TOUT)

Port (TIN)

21 23 25

Re-trigger

φ φ φ

138


5.2 16-bit Reload Timer Registers

This section describes the configuration and functions of the registers used by the 16-bit reload timer.

16-bit Reload Timer Registers

Figure 5.2-1 16-bit Reload Timer Registers

15 14 13 12 11 10 9 8

Control status register

15 0 16-bit timer register

7 6 5 4 3 2 1 0

(TMR)

15 0 16-bit reload register

(TMRLR)

CSL1 CSL0 MOD2 MOD1

MOD0 OUTL RELD INTE UF CNTE TRG(TMCSR)

139


5.2.1 Control Status Register (TMCSR)

The control status register (TMCSR) controls the operating modes and interrupts of the 16-bit timer.

Bit Configuration of the Control Status Register (TMCSR)

Figure 5.2-2 Bit Configuration of the Control Status Register (TMCSR)

Rewrite bits other than the UF, CNTE, and TRG bits only when CNTE=0.

The control status register (TMCSR) supports simultaneous writing.

Bit Functions of the Control Status Register (TMCSR)The following describes the bit functions of the control status register (TMCSR).

[bit11, bit10] CSL1, CSL0 (Count clock SLect)

These bits are the count clock select bits. Table 5.2-1 shows the clock sources that can beselected using these bits. Countable edges used when external event count mode are setusing the MOD1 and MOD0 bits.

TMCSR bitAddress: 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

0000004EH

00000056H

0000005EH

CSL1 CSL0 MOD2 MOD1 MOD0 "0" OUTLRELD INTE UF CNTE TRG000000

000000B

R/W R/W R/W R/W R/W R R/WR/W R/W R/W R/W R/W

Table 5.2-1 Clock Sources Set Using the CSL Bits

CSL1 CSL0 Clock source (φ: Machine clock)

0 0 φ/21

0 1 φ/23

1 0 φ/25

1 1 External clock (event)

Note: The minimum pulse width required for an external clock is 2T (T: Peripheral clock machine cycle).

140


[bit9, bit8, bit7] MOD2, MOD1, MOD0 (MODe)

These bits set the operating modes and the functions of the input-output pins.

The MOD2 bit selects the function of an input pin. If it is set to "0", the input pin becomes thetrigger input pin. When a valid edge is then input, the contents of the reload register areloaded into the counter and the count operation is continued. If it is set to "1", gate count modeis entered and the input pin provides the gate input. While a valid level is input, the countoperation is performed.

The MOD1 and 0 bits set the functions of pins in various modes. Table 5.2-2 and Table 5.2-3describes the settings of the MOD2, MOD1, and MOD0 bits.

[bit6] (reserved)


The read value is always "0".

Table 5.2-2 Bit MOD2, 1, and 0 Setting Method 1 (in Internal Clock Mode (CSL0, CSL1=00, 01, 10))

MOD2 MOD1 MOD0 Input pin function Valid edge or level

0 0 0 Trigger disabled -

0 0 1

Trigger input

Rising edge

0 1 0 Falling edge

0 1 1 Both edges

1 x 0Gate input

"L" level

1 x 1 "H" level

Table 5.2-3 Bit MOD2, 1, and 0 Setting Method 2 (in Event Count Mode (CSL0, CSL1=11))

MOD2 MOD1 MOD0 Input pin function Valid edge or level

x

0 0 - -

0 1

Event input

Rising edge

1 0 Falling edge

1 1 Both edges

Note: x in this table represents any value.

141


[bit5] OUTL

This bit sets the output level of the TOUT pin. The pin levels are reversed while this bit is setto "0" and "1". Specify an output waveform using a combination of this bit, bit4 (RELD bit), andthe corresponding bit of the PFR register of the I/O port. Table 5.2-4 shows the settings whenthese bits are combined.

[bit4] RELD

This bit is the reload enable bit. If it is set to "1", reload mode is entered. As soon as thecounter value underflows from 0000H to FFFFH, the contents of the reload register are loaded

into the counter and the count operation is continued.

If this bit is set to "0", the count operation is stopped when the counter value underflows from0000H to FFFFH.

[bit3] INTE

This bit is the interrupt request enable bit. If the INTE bit is set to "1", an interrupt request isgenerated when the UF bit is set to "1". If it is set to "0", no interrupt request is generated.

[bit2] UF

This bit is the timer interrupt request flag. This bit is set to "1" when the counter valueunderflows from 0000H to FFFFH. Write "0" to this bit to clear it.

Writing "1" to this bit is meaningless. When this bit is read by a read modify write instruction,"1" is always read.

[bit1] CNTE

This bit is the count enable bit of the timer. Write "1" to this bit to enter the start trigger waitstate. Write "0" to this bit to stop the count operation.

[bit0] TRG

This bit is the software trigger bit. Write "1" to this bit to generate a software trigger, load thecontents of the reload register into the counter, and start the count operation.

Writing "0" to this bit is meaningless. The read value is always "0".

The trigger input to this register is valid only if CNTE=1. No operation occurs if CNTE=0.

Table 5.2-4 Settings of TOEx, OUTL, and RELD

TOEx OUTL RELD Output waveform

0 × × Output prohibited

1 0 0 "H" level square wave while counting is in progress

1 1 0 "L" level square wave while counting is in progress

1 0 1 "L" level toggle output while the counting is started

1 1 1 "H" level toggle output while the counting is started

× in the table indicates an arbitrary value.TOEx indicates TOE0 to TOE3 in PFR (Port Function Register).

142


5.2.2 16-bit Timer Register (TMR)

The 16-bit timer register (TMR) is a register to which the count value of the 16-bit timer can be read. The initial value is undefined.Be sure to read this register using a 16-bit data transfer instruction.

Bit Configuration of the 16-bit Timer Register (TMR)Figure 5.2-3 shows the bit configuration of the 16-bit timer register (TMR).

Figure 5.2-3 Bit Configuration of the 16-bit Timer Register (TMR)

15 0TMR

R R R R R R R R R x x x x x x x x x

Address: 00004AH

Initial value

000052H

00005AH

143


5.2.3 16-bit Reload Register (TMRLR)

The 16-bit reload register (TMRLR) holds the initial value of a counter. The initial value is undefined.Be sure to read this register using a 16-bit data transfer instruction.

Bit Configuration of the 16-bit Reload Register (TMRLR)Figure 5.2-4 shows the bit configuration of the 16-bit reload register (TMRLR).

Figure 5.2-4 Bit Configuration of the 16-bit Reload Register (TMRLR)

15 0TMRLR

W W W W W W W W W x x x x x x x x x

Address: 000048H

Initial value

000050H

000058H

144


5.3 16-bit Reload Timer Operation

This section describes the following operations of the 16-bit reload timer:• Internal clock operation• Underflow operation• Operation of the input pin function• Operation of the output pin function

Internal Clock OperationIf the timer operates with a divide-by clock of the internal clock, one of the clocks created bydividing the machine clock by 2, 8, or 32 can be selected as the clock source.

The external input pin can be used as the trigger or gate input depending on the register setting.

To start the count operation as soon as counting is enabled, write "1" to the CNTE and TRG bitsof the control status register. Trigger input occurring due to the TRG bit is always valid regardlessof the operating mode while the timer is running (CNTE=1).

Figure 5.3-1 shows the startup and operations of the counter.

Time as long as T (T: peripheral clock machine cycle) is required after the counter start trigger isinput and before the data of the reload register is actually loaded into the counter.

Figure 5.3-1 Startup and Operations of the Counter

Count clock

Counter Reload data -1 -1 -1

Data load

CNTE (register)

TRG (register)

T

145


Underflow Operation

An underflow is an event in which the counter value changes from 0000H to FFFFH. Thus, an

underflow occurs at the count of [Reload register setting value + 1].

If the RELD bit of the control status register (TMCSR) is set to "1" when an underflow occurs, thecontents of the 16-bit reload register (TMRLR) are loaded and the count operation is continued. Ifthe RELD bit is set to "0", the counter stops at FFFFH.

An underflow sets the UF bit of the control status register (TMCSR) and, if the INTE bit is set to"1", generates an interrupt request.

Figure 5.3-2 shows the timing chart of the underflow operation.

Figure 5.3-2 Timing Chart of the Underflow Operation

Reload data0000H -1 -1 -1

Count clock

Counter

Data load

Underflow set

0000H FFFFH

Count clock

Counter

Underflow set

[RELD=1]

[RELD=0]

146


Operation of the Input Pin Function (in Internal Clock Mode)

If the internal clock is selected as the clock source, the TIN pin can be used as the trigger or gateinput.

Trigger input operation

If the TIN pin is used as the trigger input, the input of a valid edge loads the contents of the 16-bitreload register (TMRLR) into the counter, clears the internal prescaler, and then starts the countoperation. Input to TIN a pulse longer than 2T (where T is the peripheral clock machine cycle).

Figure 5.3-3 shows the timing chart of the trigger input operation.

Figure 5.3-3 Timing Chart of the Trigger Input Operation

Gate input operation

If the TIN pin is used as gate input, the count operation continues only while the TIN pin acceptsthe input of a valid level defined by the MOD0 bit of the control status register (TMCSR). At thistime, the count clock continues without stopping. In gate mode, a software trigger is enabledregardless of the gate level. The pulse width of the TIN pin must be 2T (where T is a peripheralclock machine cycle) or more.

Figure 5.3-4 shows the timing chart of gate input operation.

Figure 5.3-4 Timing Chart of Gate Input Operation

Count clock

Counter

Load

Prescaler clear

TIN

Reload data -1-1 -1 -1

2T to2.5T

Rising edge detected

Counter -1 -1 -1

Count clock

TIN If MOD0=1 (counts while H is input)

147


External Event Count Operation

If the external clock is selected, the TIN pin becomes the external event input pin and valid edgesdefined in the register are counted. The pulse width of the TIN pin must be 2T (where T is aperipheral clock machine cycle) or more.

Operation of the Output Pin FunctionThe TOUT pin provides toggle input that is reversed upon an underflow in reload mode or pulseoutput that indicates that counting is in progress in one-shot mode. The output polarity can be setin the OUTL bit of the control status register (TMCSR). If OUTL=0, toggle output is "0" for theinitial value and the one-shot pulse output is "1" while the count operation is in progress. IfOUTL=1, the output waveform is reversed.

Figure 5.3-5 shows the timing chart of output pin function operation.

Figure 5.3-5 Timing Chart of Output Pin Function Operation

Reversed if OUTL=1

Startup trigger

CNTE

TOUT

Underflow


Count started

Startup trigger

Startup trigger wait status

CNTE

Underflow

Reversed if OUTL=1

TOUT


[RELD=1, OUT=0]

[RELD=0, OUT=0]

148


Other Operation

Channels 0 and 1 of the 16-bit reload timer support the start of DMA transfer occurring due tointerrupt request signals.

The DMA controller clears the interrupt flag of the reload timer as soon as a transfer request isaccepted.

Operating States of the Counter

The counter state is determined by the CNTE bit of the control status register (TMCSR) and theWAIT signal, which is an internal signal. The states that can be set include the stop state, whenCNTE=0 and WAIT=1 (STOP state); the startup trigger wait state, when CNTE=1 and WAIT=1(WAIT status); and the operation state, when CNTE=1 and WAIT=0 (RUN state).

Figure 5.3-6 shows the state transitions.

Figure 5.3-6 Status Transitions of Counter

State transition due to hardware

State transition due to register access

CNTE="0"

CNTE=1, WAIT=0 T1: Serves as T1 T0: Serves as T0

Counter: Running

Load completed

RELD UF TRG="1" TRG="1"

CNTE=1, WAIT=0 Loads contents of reload register into counter.Trigger from TIN

RELD UF Counter: Holds the value when it stops; undefined just after reset and until data is loaded

T0: Initial value outputT1: Only trigger input enabled

CNTE=1, WAIT=1

CNTE="0"

CNTE="1" TRG="0"

CNTE="1"TRG="1"

Counter: Holds the value when it stops; undefined just after reset

T0: General-purpose portT1: Input disabled

CNTE=0, WAIT=1 Reset

RUN

LOAD

WAIT

STOP

149


Precautions on Using the 16-bit Reload Timer

Internal prescaler

The internal prescaler is enabled if a trigger (software or external trigger) is applied while bit1(timer enable: CNTE) of the control status register (TMCSR) is set to "1".

Even when only gate count mode is to be used, be sure to apply a trigger one time before a validgate level is input.

When you set CNTE, it is recommended that you write "1" to bit0 (TRG) of the TMCSR register.

Timing of setting and clearing the interrupt request flag

If the device attempts to set and clear the interrupt request flag at the same time, the flag is setand the clear operation becomes ineffective.

16-bit timer register (TMR)/16-bit reload register (TMRLR)

If the device attempts to write to the 16-bit timer register and reload the data into the 16-bit reloadregister at the same time, old data is loaded into the counter. New data is loaded into the counteronly in the next reload timing.

16-bit timer register (TMR)

If the device attempts to load and count the 16-bit timer register at the same time, the load(reload) operation takes precedence.

150

CHAPTER 6PROGRAMMABLE PULSE

GENERATOR (PPG) TIMER

This chapter gives an outline of the PPG (Programmable Pulse Generator) timer and explains the register configuration and functions and the timer operations.

6.1 Outline

6.2 Block Diagram of the PPG Timer

6.3 Registers of the PPG Timer

6.4 PWM Mode

6.5 One-shot Mode

6.6 Interrupts

6.7 PPG Output of ALL-L and ALL-H

6.8 Precautions on Using the PPG Timer

151

CHAPTER 6 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER

6.1 Outline

The PPG timer can efficiently output highly accurate PWM waveforms.The MB91319 has four channels of the PPG timer.

Characteristics of PPG Timer

• Each channel consists of a 16-bit down counter, 16-bit data register with a cycle setting buffer,16-bit compare register with a duty setting buffer, and pin control block.

• One of the four count clocks can be selected for the 16-bit down counter:

• Internal clocks: φ, φ/4, φ/16, and φ/64

• A reset or counter borrow can initialize the counter value to "FFFFH".

• Each channel has PPG output (PPG0 to PPG3).

• Registers

• Cycle setting register: Data register for reload with bufferData is transferred from the buffer when an activation trigger signal is detected and acounter borrow occurs.The PPG output is inverted when a counter borrow occurs.

• Duty setting register: Compare register with bufferPPG output is inverted when the value of this register and the counter value match.

• Pin control

• Set to "1" when the duty matches (priority)

• Reset to "0" when a counter borrow occurs.

• Output-value fixed mode is available to facilitate output of all-L (or H).

• The polarity can be specified.

• An interrupt request can be generated as one of the following combinations:

• Activation of PPG timer (software trigger or trigger input)

• Generation of counter borrow (cycle match)

• Generation of duty match

• Generation of counter borrow (cycle match) or duty match

• Multiple channels can be activated at one time by using software or other interval timers.

Restart during operation can also be set.

152


6.2 Block Diagram of the PPG Timer

Figure 6.2-1 shows an overall block diagram of the PPG timer. Figure 6.2-2 shows the block diagram for one channel of the PPG timer.

Overall Block Diagram of PPG Timer

Figure 6.2-1 Overall Block Diagram of PPG Timer

PPG0

TRG inputPPG timer ch3




PPG1

PPG2

PPG3

External TRG1

External TRG0

External TRG3

External TRG2

153


Block Diagram for One Channel of PPG Timer

Figure 6.2-2 Block Diagram for One Channel of PPG Timer

cmp

Peripheral clock

Prescaler

PCRS

IRQ

PPG output

Enable

Software trigger

TRG input Edge detection

Reverse bit

PPG mask

S Q R

1/1

1/4

1/16

1/64

CK Load 16-bitdown counter

Start Borrow

PDUT

Mountingselect

154


6.3 Registers of the PPG Timer

This section explains the registers of the PPG timer.

Registers of the PPG Timer

Figure 6.3-1 shows the registers of the PPG timer.

Figure 6.3-1 Registers of the PPG TimerAddress Access 15 0

00000120 H PTMR0 R ch0 PPG Timer regiser

00000122 H PCSR0 W ch0 PPG Cycle Setting Register

00000124 H PDUT0 W ch0 PPG Duty Setting Register

00000126 H PCNH0 PCNL0 R/W ch0 Control/Status Register

00000128 H PTMR1 R ch1 PPG Timer register

0000012A H PCSR1 W ch1 PPG Cycle Setting Register

0000012C H PDUT1 W ch1 PPG Duty Setting Register

0000012E H PCNH1 PCNL1 R/W ch1 Control/Status Register

00000130 H PTMR2 R ch2 PPG Time register

00000132 H PCSR2 W ch2 PPG Cycle Setting Register

00000134 H PDUT2 W ch2 PPG Duty Setting Register

00000136 H PCNH2 PCNL2 R/W ch2 Control/Status Register

00000138 H PTMR3 R ch3 PPG Timer register

0000013A H PCSR3 W ch3 PPG Cycle Setting Register

0000013C H PDUT3 W ch3 PPG Duty Setting Register

0000013E H PCNH3 PCNL3 R/W ch3 Control/Status Register

155


6.3.1 Control Status Register (PCNH, PCNL)

The control status registers (PCNH and PCNL) are used to control and display the status of the PPG timer.

Register Configurations of Control Status Registers (PCNH and PCNL)

Figure 6.3-2 shows the register configuration of the control status registers (PCNH and PCNL).

Figure 6.3-2 Register Configurations of PCNH and PCNL

[bit15] CNTE (Timer Enable)

This bit enables operation of the 16-bit down counter.

[bit14] STGR (Software Trigger)

Writing 1 into this bit applies software trigger.

The read value is always 0.

[bit13] MDSE (Mode Select)

This bit is used to select either the PWM mode in which continuous pulses are output or theone-shot mode in which a single pulse is output.

PCNH bit 15 14 13 12 11 10 9 8 ch0 000126

ch1 00012Ech2 000136ch3 00013E

CNTE STGR MDSE RTRG CKS1 CKS0 PGMS R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0

PCNL bit 7 6 5 4 3 2 1 0 ch0 000127

ch1 00012Fch2 000137ch3 00013F

Address

Address

R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0

H

H

H

H

H

H

H

H

EGS1 EGS0 IREN IRQF IRS1 IRS0 OSEL

AttributeInitial valueRewrite during operation

AttributeInitial valueRewrite during operation

0 Disabled (initial value)

1 Enabled

0 PWM mode (initial value)

1 One-shot mode

156


[bit12] RTRG (Retrigger Select)

This bit enables a restart resulting from a software trigger or trigger input.[

[bit11, bit10] CKS1 and CKS0 (Counter Clock Select)

These bits are used to select the count clock of the 16-bit down counter.

[bit9] PGMS (PPG Output Mask Select)

Writing 0 into this bit allows PPG output to be masked to 0 or 1, regardless of mode, cycle,and duty settings.

For all-H output in ordinary polarity mode and all-L output in reverse polarity mode, specify thesame value in the cycle setting register and duty setting register in order to output the abovemask value with the polarity reversed.

[bit8] (reserved)


[bit7, bit6] EGS1 and EGS0 (Trigger Input Edge Select Bit)

These bits are used to select an effective edge for trigger input.

Regardless of the mode that is selected, writing "1" to the bit of a software trigger enables thesoftware trigger.

0 Restart disabled (initial value)

1 Restart enabled

CKS1 CKS0 Cycle

0 0 φ/2 (initial value)

0 1 φ/4

1 0 φ/16

1 1 φ/64

φ: Peripheral machine clock

Table 6.3-1 PPG Output when Write "1" to PGMS

Polarity PPG output

Ordinary polarity L output

Reverse polarity H output

EGS1 EGS0 Edge selection

0 0 Not effective

0 1 Rising edge

1 0 Falling edge

1 1 Both edges

157


[bit5] IREN (PPG Interrupt Request Enable)

This bit enables an interrupt request.

[bit4] IRQF (PPG Interrupt Request Flag)

If bit5, IREN, is enabled and an interrupt source selected in bit3 and bit2, the IRS1 and IRS0,occurs then this bit is set and an interrupt request is generated and issued to the CPU.

This bit is cleared if 0 is written to it.

This bit remains unchanged if "1" is written to it.

The read value by a read-modify-write instruction is always 1, regardless of the bit value.

[bit3, bit2] IRS1, IRS0 (Interrupt Resource Select)

These bits are used to select a source that sets bit4, the IRQF.

[bit1] (reserved)

This bit is unused.

[bit0] OSEL: PPG Output Polarity Specification Bit

This bit sets the polarity of the PPG output.

Table 6.3-2 and Table 6.3-3 show the combination results for this bit and bit9 (PGMS).

0 Disabled (initial value)

1 Enabled

IRS1 IRS0 Interrupt resource

0 0 Software trigger or trigger input (initial value)

0 1 Occurrence of a counter borrow (cycle match)

1 0 Occurrence of a duty match

1 1Occurrence of a counter borrow (cycle match) or duty match

Table 6.3-2 Combination of PPG Output Polarity Specifications

PGMS OSEL PPG output

0 0 Ordinary polarity (initial value)

0 1 Reverse polarity

1 0 Output fixed to L

1 1 Output fixed to H

Table 6.3-3 PPG Output Polarity Specification

Polarity After reset Duty match Counter borrow

Ordinary polarity L output Rising edge Falling edge

Reverse polarity H output Falling edge Rising edge

158


6.3.2 PPG Cycle Setting Register (PCSR)

The PPG cycle setting register (PCSR) is a register with a buffer for setting a cycle.Transfers from the buffer are performed with counter borrow.

Bit Configuration of PPG Cycle Setting Register (PCSR)

Figure 6.3-3 shows the bit configuration of the PPG cycle setting register (PCSR).

Figure 6.3-3 Bit Configuration of PPG Cycle Setting Register (PCSR)

When initializing or rewriting the cycle setting register, be sure to write to the duty setting registerafter the writing of the cycle setting register.

This register must be accessed using 16-bit data.

PCSR bit 15 14 13 12 11 10 9 8 Address: ch0 000122H

ch1 00012AH

ch2 000132H

ch3 00013AH

7 6 5 4 3 2 1 0

Attribute Initial value

Write onlyXXXXXXXX XXXXXXXX

159


6.3.3 PPG Duty Setting Register (PDUT)

The PPG duty setting register (PDUT) is a register with buffer for setting a duty.Transfers from the buffer are performed with counter borrow.

Bit Configuration of PPG Duty Setting Register (PDUT)

Figure 6.3-4 shows the bit configuration of the PPG duty setting register (PDUT).

Figure 6.3-4 Bit Configuration of PPG Duty Setting Register (PDUT)

When the same value is set in the cycle setting register and the duty setting register, all-H isoutput in ordinary polarity mode and all-L is output in reverse polarity mode.

Do not specify a smaller value in PCSR than that in PDUT. Otherwise, PPG output becomesundefined.


PDUT bit 15 14 13 12 11 10 9 8 Address: ch0 000124H

ch1 00012CH

ch2 000134H

ch3 00013CH

7 6 5 4 3 2 1 0


Write onlyXXXXXXXX XXXXXXXX

160


6.3.4 PPG Timer Register (PTMR)

The PPG timer register (PTMR) is a register used to read the value of the 16-bit down counter.

Bit Configuration of PPG Timer Register (PTMR)

Figure 6.3-5 shows the bit configuration of the PPG timer register (PTMR).

Figure 6.3-5 Bit Configuration of PPG Timer Register (PTMR)


PDMR bit 15 14 13 12 11 10 9 8 Address: ch0 000120H

ch1 000128H

ch2 000130H

ch3 000138H

7 6 5 4 3 2 1 0


Read only11111111 11111111

161


6.4 PWM Mode

In PWM mode, pulses are continuously output after an activation trigger is detected.

PWM Mode

In PWM mode, the PPG timer can output pulses continuously after an activation trigger signal isdetected.

The output pulse cycle can be controlled with the PCSR value, and the duty ratio can becontrolled with the PDUT value.

Note:

After data is written to PSCR, be sure to write data to PDUT.

PWM Mode Timing Chart

Figure 6.4-1 shows the PWM mode timing chart when trigger reactivation is disabled, and Figure6.4-2 shows the PWM mode timing chart when trigger reactivation is enabled.

When reactivation is disabled

Figure 6.4-1 PWM Mode Timing Chart (Trigger Reactivation Disabled)

Rising edge detection Trigger ignored

Trigger

m

n

0

PPG (1)

(2)

(1) = T (n+1) ms(2) = T (m+1) ms

T: Count clock cyclem : PCSR valuen : PDUT value

162


When reactivation is enabled

Figure 6.4-2 PWM Mode Timing Chart (Retrigger Enabled)

m

n

0

PPG

Rising edge detection Trigger restarted

Trigger

(1)

(2)

163


6.5 One-shot Mode

In one-shot mode, a single pulse of an arbitrary width is output by a trigger.

One-shot Mode

In one-shot mode, the PPG timer can output a single pulse of an arbitrary width when triggered.When reactivation is enabled, the PPG timer reloads the counter value after an edge is detectedduring operation.

One-shot Mode Timing Charts

Figure 6.5-1 show the one-shot mode timing chart when trigger reactivation is disabled. Figure6.5-2 shows the one-shot mode timing chart when trigger reactivation is enabled.

When reactivation is disabled

Figure 6.5-1 One-shot Mode Timing Chart (Trigger Reactivation Disabled)

m

n

0

PPG


Trigger

(1)

(2)

164


When reactivation is enabled

Figure 6.5-2 One-shot Mode Timing Chart (Trigger Restarted)

m

n

0

PPG


Trigger

(1)

(2)

165


6.6 Interrupts

Figure 6.6-1 shows the interrupt resources and timing chart.

Interrupt Resources and Timing Chart

Figure 6.6-1 Interrupt Resources and Timing Chart (PPG Output: Ordinary Polarity)

Trigger

Load

Clock

Count value 0003 0002 0001 0000 0003

PPG

Interrupt

Effective edge compare match Borrow

2.5Tmaximum

166


6.7 PPG Output of ALL-L and ALL-H

This section describes PPG output of all-L and all-H.

PPG Output All-L and All-H

Figure 6.7-1 shows an example of the output method that sets the PPG output to all-L, and Figure6.7-2 shows an example of the output method that sets the PPG output to all-H.

Figure 6.7-1 Example of the Output Method that Sets PPG Output to All-L

Figure 6.7-2 Example of the Output Method that Sets PPG Output to All-H

PPG

Reduce the duty.

Using an interrupt by borrow, set the PGMS (mask bit)to "1". If the PGMS (mask bit) is set to "0" during useof an interrupt by borrow, the PWM waveform can beoutput without generating glitches.

PPG

Increase the duty.

Using an interrupt by compare match, write to theduty setting register the same values as that in the cycle setting register.

167


6.8 Precautions on Using the PPG Timer

This section gives notes on using the PPG timer.

Precautions on Using the PPG Timer

• If the device attempts to set and clear the interrupt request flag at the same time, the flag isset and the clear operation becomes ineffective.

• The settings of bit11 and bit10 (count clock select bits CKS1 and CKS0) of the PPG controlregister are reflected immediately after data is written to the bits. Change the settings of thebits when counting stops.

• If the device attempts to load and count the PPG down counter (PPGC: 16-bit down counter)at the same time, the load operation takes precedence.

168

CHAPTER 7MULTIFUNCTION TIMER

This chapter gives an overview of the multifunction timer and explains the register configuration and functions and the timer operation.

7.1 Overview of the Multifunction Timer

7.2 Registers of the Multifunction Timer

7.3 Multifunction Timer Operation

169

CHAPTER 7 MULTIFUNCTION TIMER

7.1 Overview of the Multifunction Timer

The multifunction timer consists of four channels for a 16-bit up counter. This section gives an overview of the multifunction timer.

Features of the Multifunction Timer

The multifunction timer has the following features:

• A low-pass filter reduces noise that is below the amplitude of the set clock.

• The pulse width can be measured according to settings using seven types of clock signals.

• An event count from pin input is available.

• An interval timer that uses seven types of clocks and external input clocks is available.

Block Diagram

Figure 7.1-1 shows the block diagram of the multifunction timer.

Figure 7.1-1 Block Diagram of the Multifunction Timer (Simple)

16-bit Counter

CK

CNT

CCLKP CKITO

Divider

Event counter

Interrupt

Interval register

CPIB

CLR

Edg

e de

tect

ion

EN

CPIA

Division

Synchronization

CLKP

LPF

OUT

Synchronization

Capture register

170


Figure 7.1-2 Block Diagram of the Multifunction Timer (Universal)

TOCK1

CPIAch. 0

CPIBOUT

TOCK1

CPIAch. 1

CPIB

TOTMI2CK1

CPIAch. 2

CPIB

TOCK1

CPIAch. 3

CPIB

TMI1

TMI0

HCNTMD

TMI3

TMO2

TMO1

TMO0

TMO3

171


7.2 Registers of the Multifunction Timer

This section explains the configuration and functions of the registers used by the multifunction timer.

Registers of the Multifunction Timer

Figure 7.2-1 shows the registers of the multifunction timer.

Figure 7.2-1 Registers of the Multifunction Timer

150000F0H T0LPCR T0CCR (R/W)0000F2H T0TCR T0R (R/W)0000F4H (R/W)0000F6H (R/W)0000F8H T1LPCR T1CCR (R/W)0000FAH T1TCR T1R (R/W)0000FCH (R/W)0000FEH (R/W)000100H T2LPCR T2CCR (R/W)000102H T2TCR T2R (R/W)000104H (R/W)000106H (R/W)000108H T3LPCR T3CCR (R/W)00010AH T3TCR T3R (R/W)00010CH (R/W)00010EH (R/W)

T2DRRT2CRR

T3DRRT3CRR

T0DRRT0CRR

T1DRRT1CRR

8 7 0

000110H (R/W)TMODE

172


7.2.1 Low-Pass Filter Control Register (TxLPCR)

The low-pass filter control register (TxLPCR) sets the low-pass filter for input pins.

Low-Pass Filter Control Register (TxLPCR)

The low-pass filter control register (TxLPCR) can be 8-bit accessed. Because this filter reducesnoise logically, the delay between the output waveform and the input waveform is the noisereduction width plus two cycles.

Figure 7.2-2 shows the bit configuration of the low-pass filter control register (TxLPCR).

Figure 7.2-2 Bit Configuration of the Low-Pass Filter Control Register (TxLPCR)

[bit15 to bit11] (reserved)

These bits are unused.

Writing to these bits is ignored, and the read value is always 0.

[bit10, bit9] FCx1, FCx0 (filter clock select flag)

These bits are used to select the operating clock for the LPF.

Table 7.2-1 shows the operating clock selection.

[bit8] FxEN (filter enable flag)

This bit specifies whether the filter is used.

15 14 13 12 11 10 9 8TxLPCR address

0000F0H

0000F8H

000100H

000108H

FCx1 FCx0 FxEN -----000B

R/W R/W R/W

Initial value

Table 7.2-1 Operating Clock Selection

FCx1 FCx0 Noise reduction width (@20 MHz)

0 0 0.2 µs [initial value]

0 1 0.4 µs

1 0 0.8 µs

1 1 1.6 µs

0 The filter is not used [initial value].

1 The filter is used.

173


7.2.2 Capture Control Register (TxCCR)

The capture control register (TxCCR) sets the count, edge, and interrupt in capture mode.

Capture Control Register (TxCCR)

The capture control register can be 8-bit accessed. If this register is written to during operation(entire register ST = 1), the timer operation is unpredictable. Be sure to rewrite this register whenit is stopped (ST = 0).

Figure 7.2-3 shows the bit configuration of the capture control register (TxCCR).

Figure 7.2-3 Bit Configuration of the Capture Control Register (TxCCR)

[bit7] CPF (capture edge detection flag)

This bit indicates that the capture end edge has been detected.

Writing 1 to this bit has no effect.

If data is written to this flag from the hardware and the CPU at the same time, writing from thehardware has priority.

[bit6] (reserved)

This bit is unused.

Writing to this bit is ignored, and the read value is always 0.

[bit5] CPST (capture start edge select flag)

This bit sets the polarity of the capture start edge.

When you specify the same edge as the polarity of capture end edge for a value of this bit,capture is restart after the next edge from the end edge.

7 6 5 4 3 2 1 0TxCCR address

0000F1H

0000F9H

000101H

000109H

CPOVCPF CPST CPED CPIE CPMD CPIST0CCR: 0-010000B

T1CCR: 0-000000B

T2CCR: 0-000000B

T3CCR: 0-000000B R/W R/W R/W R/W R/W R/W R/W

Initial value

0 No capture edge [initial value]

1 Capture edge

0 Rising edge [initial value]

1 Falling edge

174


[bit4] CPED (capture end edge select flag)

This bit sets the polarity of the capture end edge.

When the setting of the capture start edge and capture end edge are the same, the captureend edge is prioritized. The capture start is recognized by next edge.

[bit3] CPIE (capture interrupt enable flag)

This bit enables capture interrupt at capture end.

When this bit and CPF are both set to 1, an interrupt is sent to the CPU.

[bit2] CPOV (capture overflow detection flag)

This bit indicates that the counter has detected an overflow from FFFFH to 0000H in the free-run mode of capture mode.


If data is written to this bit from the hardware and the CPU at the same time, writing from thehardware has priority.

[bit1] CPMD (capture count mode flag)

This bit sets the count mode of the capture counter.

[bit0] CPIS (capture input select flag)

This bit is used to select the input signal for capture.


1 Falling edge

0 Capture interrupts are disabled [initial value].

1 Capture interrupts are enabled

0 No capture overflow [initial value]

1 Capture overflow

0 Free-run mode [initial value]

1 Upper-limit compare mode

0 CPIA input is used [initial value].

1 CPIB input is used.

175


7.2.3 Timer Setting Register (TxTCR)

The timer setting register (TxTCR) controls the timer operation.

Timer Setting Register (TxTCR)

The timer setting register (TxTCR) can be 8-bit accessed. If this register is rewritten duringoperation (entire register ST = 1), the timer operation is unpredictable. Be sure to rewrite thisregister when it is stopped (ST = 0).

Figure 7.2-4 shows the bit configuration of the timer setting register (TxTCR).

Figure 7.2-4 Bit Configuration of the Timer Setting Register (TxTCR)

[bit15] TCF (timer compare match detection flag)

This bit indicates that a timer compare match has been detected.


If data is written to this bit from the hardware and the CPU at the same time, writing data fromthe hardware has priority.

[bit14] TSES (timer start edge select flag)

This bit sets the start edge of the timer.

[bit13] TCC (timer count clear setting flag)

This bit specifies that the counter is cleared when a timer compare match is detected.

15 14 13 12 11 10 9 8TxTCR address

0000F2H

0000FAH

000102H

00010AH

TCS2TCF TSES TCC TIE CINV TCS1 TCS0 00000000B


Initial value

0 No compare match [initial value]

1 Compare match


1 Falling edge

0 Count clear [initial value]

1 No count clear

176


[bit12] TIE (timer interrupt enable flag)

This bit enables timer interrupts.

When this bit and TCF are both set to 1, an interrupt is sent to the CPU.

[bit11] CINV (timer clock invert flag)

This bit inverts the timer input clock signal from the external pin.

[bit10 to bit8] TCS2 to TCS0 (timer clock select flag)

These bits are used to select the timer clock.

To use the event count mode, set these bits to 111.

Table 7.2-2 shows the clocks to be selected.

0 Timer interrupts are disabled [initial value].

1 Timer interrupts are enabled.

0The count increments at the rising edge of the clock [initial value].

1 The count increments at the falling edge of the clock.

Table 7.2-2 Clocks to be Selected

TCS bit Clock and source to be selected

TCS2 TCS1 TCS0 Division ratio Cycle (@20 MHz)

0 0 0 φ × 23 0.4 µs

0 0 1 φ × 25 1.6 µs

0 1 0 φ × 27 6.4 µs

0 1 1 φ × 29 25.6 µs

1 0 0 φ × 210 51.2 µs

1 0 1 φ × 212 204.8 µs

1 1 0 φ × 214 819.2 µs

1 1 1 External clock

177


7.2.4 Entire Timer Control Register (TxR)

The entire timer control register (TxR) controls the entire timer operation.

Enter Timer Control Register (TxR)

The entire timer control register (TxR) can be 8-bit accessed.

Figure 7.2-5 shows the bit configuration of the entire timer control register (TxR).

Figure 7.2-5 Bit Configuration of the Entire Timer Control Register (TxR)

[bit7 to bit5] (reserved)


Writing to these bits is ignored, and the read value is always 0.

[bit4, bit3] TST2, TST1 (test bits)

These bits are test bits.

Always write 0 to these bits.

[bit2, bit1] MD1, MD0 (timer select flag)

These bits are used to select the timer operation.

[bit0] ST (timer operation start flag)

This bit is the timer operation start flag.

Set CPIE or TIE to "0" before ST=0.

When ST=0 and the interrupt factor occurs at the same time, even though ST=0, the interruptoccurs.

7 6 5 4 3 2 1 0TxR address

0000F3H

0000FBH

000103H

00010BH

MD1TST2 TST1 MD0 ST ---00000B

R/W R/W R/W R/W R/W

Initial value

MD1 MD0 Selection mode

0 0 Interval timer [initial value]

0 1 Event count

1 0 Capture


0 Timer operation is disabled [initial value].

1 Timer operation is enabled.

178


7.2.5 Timer Compare Data Register (TxDRR)

The timer compare data register (TxDRR) stores timer compare data.

Timer Compare Data Register (TxDRR)

The timer compare data register (TxDRR) compares data in this register and the value of thetimer counter and then indicates whether there is a compare match. To use this register, set theinterval time in the timer mode and the event count in the external event mode. Enter the uppercount limit in capture mode. This register cannot be 8-bit accessed. Setting 0 in this registerresults in 216 counts.

Figure 7.2-6 shows the bit configuration of the timer compare data register (TxDRR)

Figure 7.2-6 Bit Configuration of the Timer Compare Data Register (TxDRR)

15 14 13 12 11 10 9 8TxDRR address

0000F4H

0000FCH

000104H

00010CH

D11D12 D11D13D15 D14 D9 D8 XXXXXXXX

R/W R/W R/W R/W R/W

Initial value

7 6 5 4 3 2 1 0


R/W R/W R/W R/W

R/W R/W R/W

R/W R/W R/W R/W

Initial value

179


7.2.6 Capture Data Register (TxCRR)

The capture data register (TxCRR) is used to read the captured value.

Capture Data Register (TxCRR)

This register cannot be 8-bit accessed.

Figure 7.2-7 shows the bit configuration of the capture data register (TxCRR).

Figure 7.2-7 Bit Configuration of the Capture Data Register (TxCRR)

15 14 13 12 11 10 9 8TxCRR address

0000F6H

0000FEH

000106H

00010EH


R/W R/W R/W R/W R/W

Initial value

7 6 5 4 3 2 1 0


R/W R/W R/W R/W

R/W R/W R/W

R/W R/W R/W R/W

Initial value

180


7.2.7 Test Mode Register (TMODE)

TMODE is a register to set the HSYNC counter mode.

TMODE

Figure 7.2-8 Bit Configuration of the Test Mode Register (TMODE)

[bit2] HCNTMD...This bit sets the HSYNC counter mode.

0: Normal mode

1: HSYNC counter mode

The counter ch.0 is used in the HSYNC counter mode. When input HSYNC to TMI0 andVSYNC to TMI1, the counter is used to set to the capture mode.

Be sure to specify different edge for capture start and end edges.

[bit15 to bit3, bit1 to bit0] (reserved)

This bits are reserved. Write "0" to these bits.

Initial value

Initial value

15 14 13 12 11 10 9 8TMODE Address

TMODE is a register to set the HSYNC counter mode.This register is allowed an access with 16-bit.

000110H

B

7 6 5 4 3 2 1 0

HCNTMD B

R/W

181


7.2.8 Used Bit Description for Each Mode

This section explains the used bit on each mode.

Interval Timer Mode

• TxR (Timer total control register)

MD: Set to "00"

• TxTCR (Timer setting register)

TCC: Counter clear enable/disable by compare match

TIE: Interrupt output enable/disable by compare match

TCS: Set the count-up cycle

CINV: Select the external clock edge (Only if the external clock is selected by TCS)

• TxDRR (Timer compare data register)

D15-0: Set the pulse width

Event Count Mode


MD: Set to "01"


TCC: Counter clear enable/disable by compare match

TSES: Select the count-up edge for the external input

TIE: Interrupt output enable/disable by compare match


D15-0: Set the event count number

• TxCCR (Capture control register)

CPIS: Select CPIA, CPIB

• TxLPCR (Low-pass filter control register)

FxEN: Select using of the filter circuit or not (Only if CPIA is selected)

FCx1, 0: Set the bit width of digital filter (Only if CPIA is selected and FEN =1)

182


Capture Mode


MD: Set to "10"


TCS: Set the count-up cycle

CINV: Select the external clock edge (Only if the external clock is selected by TCS)


D15-0: Set the upper limit value of the capture (Only if CPMD = 1)

• TxCCR (Capture control register)

CPIE: Interrupt output enable/disable by compare match

CPIS: Select CPIA, CPIB

CPST: Select the capture start factor edge

CPED: Select the capture end factor edge

CPMD: Set the capture mode (Free-run, upper compare mode)

• TxLPCR (Low-pass filter control register)

FxEN: Select using of the filter circuit or not (Only if CPIA is selected)

FCx1, 0: Set the bit width of digital filter (Only if CPIA is selected and FEN =1)

183


7.3 Multifunction Timer Operation

The multifunction timer has the following operating modes:• Interval timer• Event count• Capture modeThis section gives an overview of operation in each mode.The initial value of the toggle output of this module is 0 in all modes.

Interval Timer Mode

In the interval timer mode, the multifunction timer has functions that use the clock selected fromthe seven types of clock sources for the timer count and toggle output and generate an interrupt ifthe counter value and the compare register value match.

Figure 7.3-1 shows the multifunction timer operating state in interval timer mode.

Figure 7.3-1 Multifunction Timer Operating State in Interval Timer Mode

Compare register value

0xFFFFH

Counter value

Interrupt

Pin output

0x0000H

An interrupt is generated at the pin output edge.

184


Event Count Mode

In the event count mode, the multifunction timer detects the pin input edge and counts the edgesthe specified number of times.

When the counter value and the compare register value match, TCF is set to 1. If TIE is set to 1at this time, an interrupt is generated. When a compare match is detected, the counter can becleared.

Figure 7.3-2 shows the multifunction timer operating state in event count mode.

Figure 7.3-2 Multifunction Timer Operating State in Event Count Mode

Clock

Pin input

Edge detection

Counter

Toggle output

Compare register

This signal enables an interrupt to be generated and the counter to be cleared.

An output signal is output when a compare match is detected.

0 1 32 4

34

185


Capture Mode

In the capture mode, the width between the rising or falling edges of an external pin input can bemeasured. The clock for measurement can be selected from the seven types of clock sources.The start and end edges can be selected from either the rising or falling edge. In free-run mode,the count value is captured when the end edge is reached. In the upper-limit compare mode, anupper limit is input if the count value and the upper-limit compare value match before the endedge is reached. Otherwise, the captured value at the end edge is input.

Figure 7.3-3 shows an example of starting the count at the rising edge and ending it at the fallingedge in free-run mode.

Figure 7.3-3 Example of Rising and Falling Edges in Capture Mode

0xFFFFH

Counter value

0x0000H

External input

The value at this point is captured.

Capture register 7777xxxx

186


Low-Pass Filter

This module contains a low-pass filter for each external pin input.

This filter enables logical reduction of noise in four types of widths.

Figure 7.3-4 shows noise reduction using the low-pass filter.

Figure 7.3-4 Noise Reduction Using the Low-Pass Filter

Filter clock

Input signal

Capture signal

State 0 1 0 0 01 1 1 1 1222

Output signal

2

This noise is reduced.

Filter clock

Input signal

Capture signal

State

Output signal

This noise is reduced.

All noise except signals that continue for at least two cycles of the filter clock is reduced.

000 1

187


188

CHAPTER 816-BIT PULSE WIDTH

COUNTER

This chapter gives an overview of the 16-bit pulse width counter and explains the register configuration and functions and the counter operation.

8.1 Overview of the 16-Bit Pulse Width Counter

8.2 Registers of the 16-Bit Pulse Width Counter

8.3 Operation of the 16-Bit Pulse Width Counter

189

CHAPTER 8 16-BIT PULSE WIDTH COUNTER

8.1 Overview of the 16-Bit Pulse Width Counter

The 16-bit pulse width counter uses a 16-bit up counter to measure the pulse width of externally input signals.

16-Bit Pulse Width Counter

The 16-bit pulse width counter consists of a 16-bit up counter, three 8-bit control registers, a PWCdata register, PWC upper data register, and a low-pass filter (LPF). This counter has the followingfunction:

• Interrupt request generation during data register transfer

Block Diagram

Figure 8.1-1 shows the block diagram of the 16-bit pulse width counter.

Figure 8.1-1 16-bit Pulse Width Counter

Capture Register

PWCCL

16 bit CounterRIN input

Internal bus

PWCCH

Control circuit

LPF

Control bit

Flag setSampling interval selectionCount clock selection

5

4Sampling interval

Count clockCount clear

IRQ

Overflow

Count clock

PWCD

Upper value register

Upper value

190


8.2 Registers of the 16-Bit Pulse Width Counter

This section explains the configuration and functions of the registers of the 16-bit pulse width counter.

Registers of the 16-Bit Pulse Width Counter

Figure 8.2-1 shows the register configuration of the 16-bit pulse width counter.

Figure 8.2-1 Register Configuration of the 16-bit Pulse Width Counter

Address000090H

000094H

000098H

00009CH

15 8 7 0PWC control registerPWC data registerPWC control registerPWC upper value setting register

PWCCL PWCCHPWCD

PWCUDReservePWCC2

191


8.2.1 PWC Control Register (PWCCL)

This section explains the configuration and functions of the PWC control register (PWCCL).

PWC Control Register (PWCCL)

Figure 8.2-2 shows the bit configuration of the PWC control register (PWCCL).

Figure 8.2-2 Bit Configuration of the PWC Control Register (PWCCL)

[bit7] INT

This bit is a flag that indicates that capture data has been transferred to the PWC dataregister. When a capture data transfer interrupt request is enabled (bit6: INTE = 1) and this bitis set, an interrupt request is generated.

The read modify write instruction is read "1".

[bit6] INTE

This bit is the capture data transfer request interrupt enable bit.

[bit5] OVFL

This bit is a flag that indicates that the 16-bit up counter has overflowed from FFFFH to 0000H.When an overflow interrupt request is enabled (bit4: OVFLE = 1) and this bit is set, aninterrupt request is generated.


7 6 5 4 3 2 1 0 Initial value PWCCL INT INTE OVFL OVFLE ST 0000--00B

( R/W ) ( R/W ) ( R/W ) ( R/W ) (R/W) Reserved

0 Interrupt source is cleared.

1 Capture data is available.

0 Interrupt request is disabled.

1 Interrupt request is enabled.

0 Interrupt source is cleared.

1 An overflow occurs.

192


[bit4] OVFLE

This bit is the overflow interrupt request enable bit.

[bit3, bit2] Unused bits


[bit1] Reserved

This bit is a reserved bit. Be sure to write 0 at writing.

[bit0] ST

This bit is the PWC start bit.

0 Interrupt request is disabled.


0 PWC stops.

1 PWC operates.

193


8.2.2 PWC Control Register (PWCCH)

This section explains the configuration and functions of the PWC control register (PWCCH).

PWC Control Register (PWCCH)

Figure 8.2-3 shows the bit configuration of the PWC control register (PWCCH).

Figure 8.2-3 Bit Configuration of the PWC Control Register (PWCCH)

[bit7, bit6] TEST1, TEST0

These bits are test bits.

[bit5] Unused bit

This bit is unused.

[bit4, bit3] CSLF1, CSFL0

These bits are used to select the LPF sampling interval from the ones listed in Table 8.2-1.

7 6 5 4 3 2 1 0 Initial value PWCCH TEST1 TEST0 CSLF1 CS1 CS0 00-00000B

CSLF0

(R/W)CS2

(R/W)(R/W)(R/W)(R/W) ( )(R/W) (R/W)

Writing a value of 1 is prohibited.

Table 8.2-1 LPF Sampling Interval

CSLF1 CSLF0 Sampling interval

0 0 φ × 26

0 1 φ × 28

1 0 φ × 210

1 1 φ × 212

(φ is the cycle of the system base clock.)

194


[bit2, bit1, bit0] CS2, CS1, CS0

These bits are used to select the internal count clock as shown in Table 8.2-2.

Table 8.2-2 Internal Count Clock

CKS2 CKS1 CKS0 Count clock selection

0 0 0 φ

0 0 1 φ divided by 26





195


8.2.3 PWC Data Register (PWCD)

The PWC data register (PWCD) stores the measured value of the pulse width.

PWC Data Register (PWCD)

Only the edge of input signal is captured the capture value. When the overflow is performed andthe upper value is exceeded, this register does not capture.

Figure 8.2-4 shows the bit configuration of the PWC data register (PWCD).

Figure 8.2-4 Bit Configuration of the PWC Data Register (PWCD)

( R/W ) ( R/W ) ( R/W ) - - - - -

7 6 5 4 3 2 1 0 Initial value PWCC2 000- ----BUPINT UPINTE LOW

196


8.2.4 PWC Control Register 2 (PWCC2)

This section explains the configuration and functions of the PWC control register 2 (PWCC2).

PWC Control Register 2 (PWCC2)

Figure 8.2-5 Bit Configuration of the PWC Control Register 2 (PWCC2)

[bit7] UPINT

This bit is a flag that indicates that the setting value of upper register has counted. When theupper value interrupt request is enabled (bit6: UPINTE=1) and this bit is set, an interruptrequest is generated.


[bit6] UPINTE

This bit is a upper value interrupt request enable bit. Set to this bit to 1 and compare thecounter value and the upper setting register.

[bit5] LOW

The bit represents that the capture value in the data register is indicated LOW width.

A read modify write instruction is read "1".

7 6 5 4 3 2 1 0 Initial value PWCC2 UPINT UPINTE LOW 000-----B

( R/W ) ( R/W ) ( R/W )

0 Interrupt source is cleared. (Initial value)

1 Upper value over count is available.

0 Interrupt request is disabled. (Initial value)


0 HIGH width measurement is completed (Initial value)

1 LOW width measurement is completed.

197


8.2.5 Upper Value Setting Register (PWCUD)

This register stores the upper value of a pulse width measurement.

Upper Value Setting Register (PWCUD)

Figure 8.2-6 Bit Configuration of the Upper Value Setting Register (PWCUD)

This register is corresponding to each width regardless of H and L width, the pulse which exceedsthe upper value is measured and the UPINT bit of PWCC2 register is set. When this registerexceeds the counter value, the count is continued and is not stopped. Therefore the initial valueof this register is undefined, writing 1 to the UPINTE bit of PWCC2 register, and write the uppervalue before compare it.

15 14 13 12 11 10 9 8 Initial valuePWCUD XXXX XXXXB

( R )

7 6 5 4 3 2 1 0 Initial valuePWCUD XXXX XXXXB

( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )

( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )

198


8.3 Operation of the 16-Bit Pulse Width Counter

The 16-bit pulse width counter consists of a 16-bit up counter, three 8-bit control registers, a PWC data register, PWC upper data register, and an LPF. This counter measures the pulse width. One of five count clocks can be selected.

Basic Operation of the 16-Bit Width Pulse Counter

Pulse width count operation

The PWC captures the counter value and clears the counter at the rising and falling edge of thePMI signal. The cleared counter continues counting unchanged. When the count value iscaptured, the PWC generates an interrupt.

When the counter value changes from FFFFH to 0000H, the PWC generates an overflowinterrupt.

Figure 8.3-1 shows the basic operation of the 16-bit pulse width counter.

Figure 8.3-1 Basic Operation of the 16-bit Pulse Width Counter

Note:

The first edge (ST=1) is not captured after the operation enables.

PMI input

FFFFH

Upper value mmmH

0000H

PWCD

INT

OVFL

Rising edge

ST (operation enable)

xxxxH aaaaH bbbbH ccccH ddddH eeeeH

Falling edge

Count value

UPINT

LOW

The upper value interrupt is set, but not captured.

199


Count Clock Selection

One of five count clocks can be selected.

Selectable count clock is shown as follow.

LPF Sampling Intervals

The LPF sampling intervals can be selected as follow.

*: Caution of setting

The PWC operation clock is CLKP. The count clock and the LFP sampling clock operatesusing φ.

Therefore, it does not operate correctly when the PWC operation clock is not faster than thecount clock and the LFP sampling clock.

Cycle: PWC operation clock × 4 < count clock

PWC opeariont clock × 4 < keep the LFP sampling clock condition.

Example: at CLKP : 20 MHz => 50 ns × 4 < count clock (φ × 26 : 1.6 µs)

at CLKP : 10 MHz => 100 ns × 4 < count clock (φ × 26 : 1.6 µs)

at CLKP : 5 MHz => 200 ns × 4 < count clock (φ × 26 : 1.6 µs)

at CLKP : 0.3 MHz => 3300 ns × 4 < count clock (φ × 26 : 1.6 µs) setting prohibited

Table 8.3-1 Count Clock Selection

CS2 CS1 CS0Count clock

selection

PLL frequency multiply by 4

(40.5 MHz)

PLL (Source oscillation

10 MHz)

0 0 0 CLKP 50 ns 200 ns

0 0 1 φ × 26 1.6 µs 6.3 µs

0 1 0 φ × 28 6.3 µs 25.3 µs

0 1 1 φ × 210 25.3 µs 101.0 µs

1 0 0 φ × 212 101.0 µs 404.1 µs

(CLKP is the peripheral clock. φ is the cycle of the system base clock.)

Table 8.3-2 LPF Sampling Intervals

CSLF1 CSLF0 Sampling intervalPLL frequency multiply by 4

(40.5 MHz)

PLL (Source oscillation 10.1 MHz)

0 0 φ × 26 * 1.6 µs 12.8 µs

0 1 φ × 28 * 6.3µs 51.2 µs

1 0 φ × 210 * 25.3 µs 204.8 µs

1 1 φ × 212 * 101.0 µs 819.2 µs


200


Figure 8.3-2 LFP Operation

Interrupt Request Generation

The 16-bit pulse width counter can generate the following three interrupt requests:

• Capture data transfer interrupt request

When capture data is transferred to the PWC data register, the interrupt flag is set. Wheninterrupt requests are enabled, an interrupt request is generated.

• Counter overflow interrupt request

When the counter value overflows from FFFFH to 0000H during measurement, the overflowflag is set. When interrupt requests are enabled, an interrupt request is generated.

Capture is not performed in overflow.

• Interrupt request which counts exceeding the value of upper register during counting

When the counter value is larger than the upper setting register during measurement, the flagis set. When interrupt requests are enabled, an interrupt request is generated.

Sampling clock

LFP output

Input signal

"L" is eliminated.

"H" is eliminated. "L" is eliminated.

"H" is eliminated.

Sampling clock

LFP output

Input signal

LFP operation

201


202

CHAPTER 9INTERRUPT CONTROLLER

This chapter describes the interrupt controller, the configuration and functions of registers, and interrupt controller operation. It also presents an example of using the hold request cancellation request function.

9.1 Overview of the Interrupt Controller

9.2 Interrupt Controller Registers

9.3 Interrupt Controller Operation

9.4 Example of Using the Hold Request Cancellation Request Function (HRCR)

203

CHAPTER 9 INTERRUPT CONTROLLER

9.1 Overview of the Interrupt Controller

The interrupt controller controls interrupt acceptance and arbitration processing.

Hardware Configuration of the Interrupt Controller

The interrupt controller consists of the following components:

• ICR register

• Interrupt priority decision circuit

• Interrupt level and interrupt number (vector) generator

• HOLD request cancellation request generator

Major Functions

The interrupt controller has the following major functions:

• Detecting NMI requests and interrupt requests

• Deciding priority (using a level or number)

• Passing to the CPU an interrupt level based on the decision result to provide informationabout the interrupt source

• Passing to the CPU an interrupt number based on the decision result to provide informationabout the interrupt source

• Instruction for return from stop mode due to the occurrence of an interrupt with an NMI/interrupt level other than 11111B (to CPU)

• Generating a HOLD request cancellation request for the bus master

204


Block Diagram

Figure 9.1-1 is a block diagram of the interrupt controller.

Figure 9.1-1 Block Diagram of the Interrupt Controller

6

5

WAKEUP (LEVEL 11111: '1')

LEVEL4-0

MHALTIHLDREQcancellation

requestLEVELand

VECTORgeneration

VECTORdecision

NMIprocessing

R-bus

UNMI

Priority decision

VCT5-0

LEVEL decision

ICR00 . . .ICR47

RI00...

RI47(DLYIRQ)

205


9.2 Interrupt Controller Registers

This section describes the configuration and functions of the registers used by the interrupt controller.

Interrupt Controller Registers

Figure 9.2-1 shows the registers used by the interrupt controller.

Figure 9.2-1 Interrupt Controller Registers (Continued on Next Page)

(Contnued)

bit 7 6 5 4 3 2 1 0

Address: 00000440H -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR00










Address: 0000044AH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR10

Address: 0000044BH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR11

Address: 0000044CH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR12

Address: 0000044DH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR13

Address: 0000044EH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR14

Address: 0000044FH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR15

















R R/W R/W R/W R/W

206


(Contnued)

bit 7 6 5 4 3 2 1 0

















R R/W R/W R/W R/W

Address: 0000045H MHALTI -- -- LVL4 LVL3 LVL2 LVL1 LVL0 HRCL

R/W R R/W R/W R/W R/W

207


9.2.1 Interrupt Control Register (ICR)

An interrupt control register (ICR) is provided for each of the interrupt input and sets the interrupt level of the corresponding interrupt request.

Bit Configuration of the Interrupt Control Register (ICR)

Figure 9.2-2 shows the bit configuration of the interrupt control register (ICR).

Figure 9.2-2 Bit Configuration of the Interrupt Control Register (ICR)

[bit4 to bit0] ICR4 to 0

These bits, which are the interrupt level setting bits, specify the interrupt level of thecorresponding interrupt request.

If an interrupt request has an interrupt level defined in this register that exceeds the level maskvalue defined in the ILM register of the CPU, it is masked by the CPU.

These bits are initialized to 11111B by a reset.

Table 9.2-1 shows the correspondence between possible interrupt level setting bits andinterrupt levels.

bit 7 6 5 4 3 2 1 0 Initial value

-- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ---11111B

R R/W R/W R/W R/W

208


Table 9.2-1 Correspondence Between Possible Interrupt Level Setting Bits and Interrupt Levels

ICR4* ICR3 ICR2 ICR1 ICR0 Interrupt level

0 0 0 0 0 0

0 1 1 1 0 14

0 1 1 1 1 15 NMI

1 0 0 0 0 16 Maximum level that can be set

1 0 0 0 1 17

1 0 0 1 0 18

1 0 0 1 1 19

1 0 1 0 0 20

1 0 1 0 1 21

1 0 1 1 0 22

1 0 1 1 1 23

1 1 0 0 0 24

1 1 0 0 1 25

1 1 0 1 0 26

1 1 0 1 1 27

1 1 1 0 0 28

1 1 1 0 1 29

1 1 1 1 0 30

1 1 1 1 1 31 Interrupt disabled

*: ICR4 is always 1; 0 cannot be written to this bit.

Reserved for system

(High)

(Low)

209


9.2.2 Hold Request Cancellation Request Level Setting Register (HRCL)

The hold request cancellation request level setting register (HRCL) is a level setting register used to generate a hold request cancellation request.

Hold Request Cancellation Request Level Setting Register (HRCL)

Figure 9.2-3 shows the bit configuration of the hold request cancellation request level settingregister (HRCL).

Figure 9.2-3 Bit Configuration of the Hold Request Cancellation Request Level Setting Register (HRCL)

[bit7] MHALTI

This bit is the DMA transfer disable bit controlled by an NMI request. An NMI request sets thisbit to 1. Write 0 to this bit to clear it. At the end of an NMI routine, clear this bit the same way itwould be cleared in a normal interrupt routine.

[bit4 to bit0] LVL4 to LVL0

This bit sets the interrupt level used to issue a hold request cancellation request to the busmaster.

If an interrupt request with a higher level than the level defined in the HRCL register occurs, ahold request cancellation request is issued to the bus master.

The LVL4 bit is always 1; 0 cannot be written to this bit.


MHALTI -- -- LVL4 LVL3 LVL2 LVL1 LVL0

R/W R R/W R/W R/W R/W 0--11111B

Address: 00000045H

210


9.3 Interrupt Controller Operation

This section describes the following items regarding operation of the interrupt controller:• Priority decision• NMI• Hold request cancellation request• Return from standby mode (stop/sleep)

Priority Decision

The interrupt controller selects the interrupt source with the highest priority from among those thatexist simultaneously and outputs the interrupt level and the interrupt number of this source to theCPU.

The following shows the priority decision criteria for interrupt sources:

• NMI

• Source that meets the following conditions:

• Source with a value other than 31 as the interrupt level (31 means interrupts disabled)

• Source with the smallest value for the interrupt level

• Source with the smallest interrupt number that satisfies the both conditions above

If no interrupt source is selected according to the above decision criteria, 31 (11111B) is output asthe interrupt level. The interrupt number at this time is undefined.

NMI

An NMI (Non Maskable Interrupt) has the highest priority among the interrupt sources handled bythis module. Thus, an NMI is always selected if it occurs at the same time as other interruptsources.

• If an NMI occurs, the following information is reported to the CPU:

• Interrupt level: 15 (01111B)

• Interrupt number: 15 (0001111B)

• Detecting an NMI

The external interrupt and NMI module sets and detects an NMI. This module only generatesan interrupt level, interrupt number, and MHALTI in response to an NMI request.

• Preventing a DMA transfer occurring due to an NMI

If an NMI request occurs, the MHALTI bit of the HRCL register is set to 1 to prevent DMAtransfer. To clear the state preventing DMA transfer, clear the MHALTI bit to 0 at the end ofthe NMI routine.

211


Hold Request Cancellation Request (HRLC: Hold Request Cancel Request)

For an interrupt with a higher priority to be processed during CPU hold, the device that hasgenerated the hold request must cancel the request. Set in the HRCL register the interrupt levelto be used as the criterion of generating a cancellation request.

Generation criteria

If an interrupt source with a higher interrupt level than the level defined in the HRCL registeroccurs, a hold request cancellation request is generated.

• If the interrupt level of the HRCL register is greater than the interrupt level after a prioritydecision, a cancellation request occurs.

• If the interrupt level of the HRCL register is equal to or less than the interrupt level after apriority decision, no cancellation request occurs.

Because the cancellation request remains valid, no DMA transfer occurs unless the interruptsource that has caused the cancellation request is cleared. Be sure to clear the correspondinginterrupt source.

If an NMI is used, the cancellation request is valid because the MHALTI bit of the HRCL registeris set to 1.

Possible levels

Values that can be set in the HRCL register range from 10000B to 11111B, which is the samerange as for the ICR.

If this register is set to 11111B, an interrupt request is issued for all the interrupt levels. If thisregister is set to 10000B, an interrupt request is issued only for an NMI.

Table 9.3-1 shows the settings of interrupt levels at which a hold request cancellation requestoccurs.

After a reset, since DMA transfer is not allowed at any interrupt level, no DMA transfer isperformed if an interrupt has occurred. Be sure to set the HRCL register to the necessary value.

Table 9.3-1 Settings of Interrupt Levels at which Hold Request Cancellation Request Occurs

HRCL register Interrupt levels at which a cancellation request occurs

16 NMI only

17 Interrupt level 16

18 Interrupt levels 16 and 17

− −

31 Interrupt levels 16 to 30 [initial value]

212


Return from Standby Mode (Sleep/Stop)

This module implements a function that causes a return from stop mode if an interrupt requestoccurs. If at least one interrupt request that includes Nmi occurs (with an interrupt level other than11111B), a return request from stop mode is generated for the clock controller.

Since the priority decision unit restarts operation when a clock is supplied after returning fromstop, the CPU executes instructions until the result of the priority decision unit is obtained.

The same operation occurs after a return from the sleep state.

Registers in this module can be accessed even in the sleep state.

Notes:

• The device returns from stop mode if an NMI request is issued. However, set an NMI so that validinput can be detected in the stop state.

• Provide an interrupt level of 11111B in the corresponding peripheral control register for aninterrupt source that you do not want to cause return from stop or sleep.

213


9.4 Example of Using the Hold Request Cancellation Request Function (HRCR)

To allow the CPU to perform high-priority processing during DMA transfer, cancel a hold request for DMA and clear the hold state. In this example, an interrupt is used to cancel a hold request to the DMA, allowing the CPU to perform priority operations.

Control Registers

Hold request cancellation level setting register (HRCL): This module

If an interrupt with a higher interrupt level than the level defined in this register occurs, a holdrequest cancellation request is issued to DMA. This register sets the level to be used as thecriterion for this purpose.

ICR: This module

This register sets a higher level than the level in the HRCL register for the ICR corresponding tothe interrupt source that will be used.

Hardware Configuration

Figure 9.4-1 shows the flow of signals.

Figure 9.4-1 Flow of Signals

IRQ MHALTI DHREQ I-UNIT DMA B-UNIT CPU

(ICR)

(HRCL) DHACK

DHREQ: D bus hold requestDHACK: D bus hold acknowledgeIRQ: Interrupt request

MHALTI: Hold request cancellation request

This module Bus access request

214


Hold Request Cancellation Request Sequence

Figure 9.4-2 Interrupt Level HRCL < ICR (LEVEL)

If an interrupt request occurs, the interrupt level changes. If the interrupt level is higher than thelevel defined in the HRCL register, MHALT1 becomes active for DMA. This causes DMA tocancel an access request and the CPU to return from the hold state to perform the interruptprocessing.

Figure 9.4-3 shows an example of the timing chart for multiple interrupts.

Figure 9.4-3 Example of Interrupt Level HRCL < ICR (Interrupt I) < ICR (Interrupt II)

Example of Interrupt Routine

(1), (3) Interrupt source clear

to

(2), (4) RETI

In the above example, while Interrupt Routine I is being executed, an interrupt with a higherpriority occurs. While the interrupt with a higher level than the level in the HRCL register remains,DHREQ is low.

Note:

Be especially careful about the relationship between interrupt levels defined in the HRCL registerand ICR.

CPU Bus access request

DHREQ

DHACK

IRQ

LEVEL

MHALTI

RUN Bus hold Interrupt processingBus hold

(DMA transfer)Example of interrupt routine(1) Interrupt source clear

(2) RETI|

(1) (2)

CPU

Bus access request

DHREQ

DHACK

IRQ1

IRQ2

LEVEL

MHALTI

RUN Bus hold

(4) (2)(1)(3)

Interrupt IInterrupt

processing IInterrupt

processing IIBus hold

(DMA transfer)

215


216

CHAPTER 10EXTERNAL INTERRUPT AND

NMI CONTROLLER

This chapter describes the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller.

10.1 Overview of the External Interrupt and NMI Controller

10.2 External Interrupt and NMI Controller Registers

10.3 Operation of the External Interrupt and NMI Controller

217

CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER

10.1 Overview of the External Interrupt and NMI Controller

The external interrupt controller is a block that controls external interrupt requests input to NMI and INT0 to INT7.H level, L level, rising edge, or falling edge can be selected as the level of a request to be detected (except for NMI).INT4 to INT6 are connected to the USB function, OSDC (main, cc), and memory stick interrupt requests inside the LSI chip. Also, INT7 is reserved, so it cannot be used.

Block Diagram of the External Interrupt and NMI Controller

Figure 10.1-1 is a block diagram of the external interrupt and NMI controller.

Figure 10.1-1 Block Diagram of the External Interrupt and NMI Controller

8

16

8

3 3

Interrupt enable register

GateInterrupt request INT0-3

NMIEdge detection circuitSource F/F

Interrupt source register

Request level setting register

R-bus

218


10.2 External Interrupt and NMI Controller Registers

This section describes the configuration and functions of the registers used by the external interrupt and NMI controller.

External Interrupt and NMI Controller Registers

Figure 10.2-1 shows the registers used by the external interrupt and NMI controller.

Figure 10.2-1 External Interrupt and NMI Controller Registers

• External interrupt enable register

• External interrupt source register

• Request level setting register

bit 7 6 5 4 3 2 1 0

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (ENIR)

bit 15 14 13 12 11 10 9 8

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (EIRR)

bit 15 14 13 12 11 10 9 8

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (ELVR)

bit 7 6 5 4 3 2 1 0

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

219


10.2.1 Interrupt Enable Register (ENIR)

The enable interrupt request register (ENIR) controls the masking of external interrupt request output.

Interrupt Enable Register (ENIR)

Figure 10.2-2 shows the bit configuration of the interrupt enable register (ENIR)

Figure 10.2-2 Bit Configuration of the Interrupt Enable Register (ENIR)

Output for an interrupt request is enabled based on the bit in this register to which 1 has beenwritten (INT0 enable is controlled by EN0), after which the interrupt request is output to theinterrupt controller. The pin corresponding to the bit to which 0 is written holds the interruptsource but does not generate a request to the interrupt controller.

Note:

No mask bit exists for NMI.


ENIR Address: 000041H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B

[R/W]

220


10.2.2 External Interrupt Source Register (EIRR)

The external interrupt request register (EIRR) indicates the presence or absence of a corresponding external interrupt request when reading from this register and the contents of the flip-flop (NMI flag) that indicates this interrupt request are cleared when writing to this register.

External Interrupt Source Register (EIRR)

Figure 10.2-3 shows the bit configuration of the external interrupt source register (EIRR).

Figure 10.2-3 Bit Configuration of the External Interrupt Source Register (EIRR)

If the read value of this EIRR register is 1, there is an external interrupt request at the pincorresponding to this bit.

Write 0 to this register to clear the request flip-flop of the corresponding bit.

Writing 1 to this has no effect.

For a read by a read modify write instruction, 1 is read.

Note:

The NMI flag cannot be read or written to by a user.

For details about the NMI flag, see Figure 10.3-4.


EIRR Address: 000040H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000B

[R/W]

221


10.2.3 External Interrupt Request Level Setting Register (ELVR)

The external level register (ELVR) specifies how a request is detected.

External Interrupt Request Level Setting Register (ELVR)

Figure 10.2-4 shows the bit configuration of the external interrupt request level setting register(ELVR).

Figure 10.2-4 Bit Configuration of the External Interrupt Request Level Setting Register (ELVR)

In ELVR, two bits each are assigned to INT0 to INT15, which results in the settings shown inTable 10.2-1. Even though the bits of the EIRR are cleared while the request input is level-baseoperation, the pertinent bits are set again as long as the input is at the level that is active.

A falling edge is detected at NMI except stoppage.

Note: In the stop state, the level is detected. (edge is disabled)



ELVR Address: 000042H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 00000000B

ELVR Address: 000043H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B

[R/W]

Table 10.2-1 Assignment of ELVR

LBx LAx Operation

0 0 L level indicates the existence of a request.

0 1 H level indicates the existence of a request.

1 0 A rising edge indicates the existence of a request.

1 1 A falling edge indicates the existence of a request.

222


10.3 Operation of the External Interrupt and NMI Controller

If, after a request level and an enable register are defined, a request defined in the ELVR register is input to the corresponding pin, this module generates an interrupt request signal to the interrupt controller.

Operation of an External Interrupt

For simultaneous interrupt requests from resources, the interrupt controller determines theinterrupt request with the highest priority and generates an interrupt for it.

Figure 10.3-1 shows external interrupt operation.

Figure 10.3-1 External Interrupt Operation

Return from Standby

To use an external interrupt to return from the standby state in the clock stop mode, use a levelrequest as the input request.

If you use an edge request, the device does not return from the stop state in clock stop mode.

Operating Procedure for an External Interrupt

Set up a register located inside the external interrupt controller as follows:

1. Disable the target bit in the enable register.

2. Set the target bit in the request level setting register.

3. Clear the target bit in the interrupt source register.

4. Enable the target bit in the enable register.

Simultaneous writing of 16-bit data is supported for steps "3." and "4.".

Before setting a register in this module, you must disable the enable register. In addition, beforeenabling the enable register, you must clear the interrupt source register. This procedure isrequired to prevent an interrupt source from occurring by mistake while a register is being set oran interrupt is enabled.

External interrupt

ELVR

EIRR

ENIR

Source

Resource request

ICR y y

ICR x x

CMP CMP

IL

ILM

Interrupt controller CPU

223


External Interrupt Request Level

• If the request level is an edge request, a pulse width of at least three machine cycles(peripheral clock machine cycles) is required to detect an edge.

• If the request level is "H" or "L" level setting and request input arrives from outside and is thencancelled, the request to the interrupt controller remains active because a source holdingcircuit exists internally.

The interrupt source register must be cleared to cancel a request to the interrupt controller.

Figure 10.3-2 shows clearing of the source holding circuit when a level is set. Figure 10.3-3shows an interrupt source and an interrupt request to the interrupt controller when interrupts areenabled.

Figure 10.3-2 Clearing the Source Holding Circuit when a Level is Set

Figure 10.3-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled

NMI

An NMI has the highest level among the user interrupts and cannot be masked. However, as anexception, an NMI can be masked from the moment a reset occurs until ILM is set.

An NMI is accepted under the following conditions:

• Normal: Rising edge

• STOP mode: L level

An NMI can be used to clear stop mode. Inputting the L level in the stop state clears the stopstate and causes the oscillation stabilization wait time to start. Returning the NMI pin to the Hlevel during the oscillation stabilization wait time eliminates the NMI source and performs no NMIprocessing after operation is restarted. To perform NMI processing after clearing the stop state,maintain the NMI pin at the L level and return it to the H level in the NMI processing routine.

The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if aninterrupt for the NMI itself is accepted or a reset occurs. Note that this bit is not readable orwritable.

Figure 10.3-4 shows the NMI request detector.

Holds a source while it is not cleared

Interrupt input Level detection Source F/F(Source holding circuit) Enable gate Interrupt controller

Interrupt input"H" level

Interrupt request to interrupt controller Becomes inactive when source F/F is cleared

224


Figure 10.3-4 NMI Request Detector

(NMI flag)

NMI request(Stop clearing)

NMIQ SX

R

STOP

Falling edgedetection

clear (RST, interrupt acknowledge)

1

0

φ

225


226

CHAPTER 11REALOS-RELATED

HARDWARE

This chapter explains the delayed interrupt module and bit search module that are REALOS-related hardware.REALOS-related hardware is used by the real-time OS. When REALOS is used, the hardware cannot be used with the user program.

11.1 Delayed Interrupt Module

11.2 Delayed Interrupt Module Registers

11.3 Operation of the Delayed Interrupt Module

11.4 Bit Search Module

11.5 Bit Search Module Registers

11.6 Bit Search Module Operation

227

CHAPTER 11 REALOS-RELATED HARDWARE

11.1 Delayed Interrupt Module

The delayed interrupt module generates an interrupt for switching tasks. Use this module to allow a software program to generate or an interrupt request for the CPU or to clear an interrupt request.

Block Diagram of the Delayed Interrupt Module

Figure 11.1-1 is a block diagram of the delayed interrupt module.

Figure 11.1-1 Block Diagram of the Delayed Interrupt Module

Interrupt requestDLYI

R-bus

228


11.2 Delayed Interrupt Module Registers

This section describes the configuration and functions of the registers used by the delayed interrupt module.

Delayed Interrupt Module Registers

Figure 11.2-1 shows the registers of the delayed interrupt module.

Figure 11.2-1 Registers of the Delayed Interrupt Module

Delayed Interrupt Control Register (DICR: Delayed Interrupt Control Register)

The delayed interrupt control register (DICR) controls delayed interrupts.

Figure 11.2-2 shows the bit configuration of the delayed interrupt control register (DICR).

Figure 11.2-2 Bit Configuration of the Delayed Interrupt Control Register (DICR)

[bit0] DLYI

Bit 7 6 5 4 3 2 1 0

Address: 00000044H DICR

[R/W]

DLYI

7 6 5 4 3 2 1 0

[R/W]

DLYI - - - - - - - 0B (Initial value)

Bit

DLYI Description

0 A delayed interrupt source is cleared or no request exists. [initial value]

1 A delayed interrupt source is generated.

229


11.3 Operation of the Delayed Interrupt Module

A delayed interrupt refers to an interrupt generated for switching tasks. Use this function to allow a software program to generate an interrupt request for the CPU or to clear an interrupt request.

Interrupt Number

A delayed interrupt is assigned to the interrupt source corresponding to the largest interruptnumber.

On the MB91319, a delayed interrupt is assigned to interrupt number 63 (3FH).

DLYI Bit of DICR

Write 1 to this bit to generate a delayed interrupt source. Write 0 to it to clear a delayed interruptsource.

This bit is the same as the interrupt source flag for a normal interrupt. Therefore, clear this bit andswitch tasks in the interrupt routine.

230


11.4 Bit Search Module

The bit search module searches for 0, 1, or any points of change for data written to the input register and then returns the detected bit locations.

Block Diagram of the Bit Search Module

Figure 11.4-1 shows a block diagram of the bit search module.

Figure 11.4-1 Block Diagram of the Bit Search Module

Input latch

Addressdecoder

Detection mode

1 detection data coding

Bit search circuit

Detection result

D-bus

231


11.5 Bit Search Module Registers

This section explains the configuration and functions of the registers used by the bit search module.

Bit Search Module Registers

Figure 11.5-1 shows bit search module registers

Figure 11.5-1 Bit Search Module Register

0 Detection Data Register (BSD0)

Figure 11.5-2 shows the bit configuration of the 0 detection data register (BSD0).

Figure 11.5-2 Bit Configuration of the 0 Detection Data Register (BSD0)

• 0 detection is performed for the written data.

• The initial value after a reset is undefined.

• The read value is undefined.

• Use a 32-bit length data transfer instruction for data transfer. Do not use 8-bit or 16-bit lengthdata transfer instructions.

31 0

Address: 000003F0H BSD0

Address: 000003F4H BSD1

Address: 000003F8H BSDC

Address: 000003FCH BSRR

0 detection data register

1 detection data register

Change point detection data register

Detection result register

31 0000003F0H

Read/writeInitial value

WXXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB

BSD0

232


1 Detection Data Register (BSD1)

Figure 11.5-3 shows the bit configuration of the 1 detection data register (BSD1).

Figure 11.5-3 Bit Configuration of the 1 Detection Data Register (BSD1)

Use a 32-bit length data transfer instruction for data transfer.

Do not use 8-bit or 16-bit length data transfer instructions.

Writing

1 detection is performed for the written data.

Reading

Save data of the internal state of the bit search module is read. This register is used to save andrestore the original state when the bit search module is used by, for example, an interrupthandler.

Even though data is written to the 0 detection or change point detection data register, data can besaved and restored only by using the 1 detection data register.

The initial value after a reset is undefined.

Change Point Detection Data Register (BSDC)

Figure 11.5-4 shows the bit configuration of the change point detection data register (BSDC).

Figure 11.5-4 Bit Configuration of the Change Point Detection Data Register (BSDC)

Point of change are detected in the written value.

The initial value after a reset is undefined.

The read value is undefined.

Use a 32-bit length data transfer instruction for data transfer. Do not use 8-bit or 16-bit lengthdata transfer instructions.

31 0000003F4H


R/WXXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB

BSD1

31 0000003F8H


WXXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB

BSDC

233


Detection Result Register (BSRR)

Figure 11.5-5 shows the bit configuration of the detection result register (BSRR).

Figure 11.5-5 Bit Configuration of the Detection Result Register (BSRR)

The 0, 1, or change point detection result is read from this register.

The detection result to be read is determined by the last written data register.

31 0000003FCH


RXXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXB

BSRR

234


11.6 Bit Search Module Operation

The bit search module performs the following three operations:• 0 detection• 1 detection• Change point detection

0 Detection

The bit search module scans data written to the 0 detection data register from the MSB to LSBand returns the location where the first 0 is detected. The detection result can be obtained byreading the detection result register. The relationship between the detected location and thereturn value is given in Table 11.6-1.

If a 0 is not found (that is, the value is FFFFFFFFH), 32 is returned as the search result.

[Execution example]

1 Detection

The bit search module scans data written to the 1 detection data register from the MSB to LSBand returns the location where the first 1 is detected. The detection result can be obtained byreading the detection result register. The relationship between the detected location and thereturn value is given in Table 11.6-1.

If a 1 is not found (that is, the value is 00000000H), 32 is returned as the search result.

[Execution example]

Write data Read value (decimal)

11111111111111111111000000000000B11111000010010011110000010101010B10000000000000101010101010101010B11111111111111111111111111111111B

(FFFFF000H)(F849E0AAH)(8002AAAAH)(FFFFFFFFH)

→ 20→ 5→ 1→ 32


00100000000000000000000000000000B00000001001000110100010101100111B00000000000000111111111111111111B00000000000000000000000000000001B00000000000000000000000000000000B

(20000000H)(01234567H)(0003FFFFH)(00000001H)(00000000H)

→ 2→ 7→ 14→ 31→ 32

235


Change Point Detection

The bit search module scans data written to the change point detection data register from bit30 tothe LSB for comparison with the MSB value. The first location where a value that is different fromthat of the MSB is detected is returned. The detection result can be obtained by reading thedetection result register.

The relationship between the detected location and the return value is given in Table 11.6-1. If achange point is not detected, 32 is returned. In change point detection, 0 is never returned as aresult.

[Execution example]


00100000000000000000000000000000B00000001001000110100010101100111B00000000000000111111111111111111B00000000000000000000000000000001B00000000000000000000000000000000B11111111111111111111000000000000B11111000010010011110000010101010B10000000000000101010101010101010B11111111111111111111111111111111B

(20000000H)(01234567H)(0003FFFFH)(00000001H)(00000000H)(FFFFF000H)(F849E0AAH)(8002AAAAH)(FFFFFFFFH)

→ 2→ 7→ 14→ 31→ 32→ 20→ 5→ 1→ 32

Table 11.6-1 Bit Locations and Return Values (Decimal)

Detected bit

location

Return value

Detected bit

location

Return value

Detected bit

location

Return value

Detected bit

location

Return value

31 0 23 8 15 16 7 24

30 1 22 9 14 17 6 25

29 2 21 10 13 18 5 26

28 3 20 11 12 19 4 27

27 4 19 12 11 20 3 28

26 5 18 13 10 21 2 29

25 6 17 14 9 22 1 30

24 7 16 15 8 23 0 31

Not found 32

236


Save/Restore Processing

If it is necessary to save and restore the internal state of the bit search module, such as when thebit search module is used in an interrupt handler, use the following procedure:

1. Read the 1 detection data register and save its contents (save).

2. Use the bit search module.

3. Write the data saved in "1." to the 1 detection data register (restore).

With the above operation, the value obtained when the detection result register is read the nexttime corresponds to the value written to the bit search module before "1.".

If the data register written to last is the 0 detection or change point detection register, the value isrestored correctly with the above procedure.

237


238

CHAPTER 1210-BIT A/D CONVERTER

This chapter gives an overview of the 10-bit A/D converter, register configuration and functions, and 10-bit A/D converter operation.

12.1 Overview of the 10-Bit A/D Converter

12.2 Registers of the 10-Bit A/D Converter

12.3 Operation of the 10-Bit A/D Converter

239

CHAPTER 12 10-BIT A/D CONVERTER

12.1 Overview of the 10-Bit A/D Converter

The 10-bit successive approximation A/D converter has two operation modes: conversion start by software and conversion start by external trigger.

Features of the 10-Bit A/D Converter

• Conversion time: 8.5 µs (sampling: 6.4 µs, conversion: 2.1 µs) when fch is @20 MHz

• A/D conversion result register available for each channel

• Channel scan function

Block Diagram

Figure 12.1-1 shows the configuration diagram of the 10-bit A/D converter, and Figure 12.1-2shows its block diagram.

Figure 12.1-1 Configuration Diagram of the 10-Bit A/D Converter

Figure 12.1-2 Block Diagram of the 10-Bit A/D Converter

A/DAN0 to AN9

From pin ATRG

IRQ

Control Logic

A/D

ch & StatusControl Logic

BUFFER x 10

D/A Converter

Comparator

S/H

AN7AN6AN5AN4AN3AN2AN1AN0

IRQExternal pin ATRG

Inte

rnal

dat

a bu

s

MP

X

AN9AN8

240


12.2 Registers of the 10-Bit A/D Converter

This section explains the configuration and functions of the registers of the 10-bit A/D converter.

Registers of the 10-Bit A/D Converter

Figure 12.2-1 shows the register configuration of the 10-bit A/D converter.

Figure 12.2-1 Register Configuration of the 10-Bit A/D Converter

Address 15 000020H

00022H

00024H

00026H

00028H

0002AH

0002CH

0002EH

00030H

00032H

00034H

00036H

ADCTH ADCTL A/DC control registerADCH Software conversion analog input select registerADAT0 A/D conversion data channel 0ADAT1 A/D conversion data channel 1ADAT2 A/D conversion data channel 2ADAT3 A/D conversion data channel 3ADAT4 A/D conversion data channel 4ADAT5 A/D conversion data channel 5ADAT6 A/D conversion data channel 6ADAT7 A/D conversion data channel 7

00038H Reserved

ADAT8 A/D conversion data channel 8ADAT9 A/D conversion data channel 9

241


12.2.1 A/DC Control Register (ADCTH, ADCTL)

This section explains the configuration and functions of the A/DC control register (ADCTH, ADCTL).

A/DC Control Register (ADCTH, ADCTL)

Figure 12.2-2 shows the bit configuration of the A/DC control register (ADCTH, ADCTL).

Figure 12.2-2 Bit Configuration of the A/DC Control Register (ADCTH, ADCTL)

[bit15 to bit10] Don't Care

The read value of these bits is always 0.

[bit9] TRG

When this bit is set to 1, A/D conversion is started when a rising edge is detected at externalpin ATGX.

This bit is ignored if an edge is detected during A/D conversion.

[bit8] STR

This bit is the A/D conversion start bit.

The read value of this bit is always 0.

[bit7 to bit4] ASS3 to ASS0

These bits enable reading of the selected analog channel.

This bit enables reading of effective data when [bit3] BUSY = 1.

ADCTH

ADCTL

15 14 13 12 11 10 9 8 Initial value 0000 0000B

(R) (R) (R) (R) (R) (R) (R/W) (R/W)

(R) (R) (R) (R) (R) (R) (R/W) (R/W)

"0" "0" "0" "0" "0" "0" TRG STR

ASS3 ASS2 ASS1 ASS0 BUSY "0" INT INTE

7 6 5 4 3 2 1 0 Initial value 0000 0000B

0 Start by external pin trigger is prohibited.

1 Start by external pin trigger

0 No effect

1 Software start/stop (write during conversion)

0 to 7 Selected channel

242


[bit3] BUSY

This bit is a flag that indicates A/D conversion is in progress.

[bit2] Don' Care


[bit1] INT

This bit is the A/D conversion end flag.

[bit0] INTE

This bit is the A/D conversion interrupt enable bit.

When INT and INTE are both set to 1, an interrupt request is generated.

0 A/D conversion is not in progress.

1 A/D conversion is in progress.

0 No conversion, or conversion is in progress.

1 Conversion is completed.

0 Interrupt is disabled.

1 Interrupt is enabled.

243


12.2.2 Software Conversion Analog Input Select Register

This section explains the configuration and functions of the software conversion analog input select register.

Software Conversion Analog Input Select Register

Figure 12.2-3 shows the bit configuration of the software conversion analog input select register.

Figure 12.2-3 Bit Configuration of the Software Conversion Analog Input Select Register



[bit9 to bit0] i9 to i0

These bits are the software conversion analog input select bits.

If multiple inputs are selected, data is sequentially converted for all selected inputs.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

ADCH "0" "0" "0" "0" "0" "0" i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 00000000 00000000B

(R/W)

0 Input is not selected.

1 Input is selected.

244


12.2.3 A/D Conversion Result Register (Channels 0 to 9)

This section explains the configuration and functions of the A/D conversion result register (channels 0 to 9).

A/D Conversion Result Register (Channels 0 to 9)

Figure 12.2-4 shows the bit configuration of the A/D conversion result register (channels 0 to 9).

Figure 12.2-4 Bit Configuration of the A/D Conversion Result Register (Channels 0 to 9)



[bit9 to bit0] d9 to d0

These bits indicate the A/D conversion result for the channels.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

ADAT0-7 d7 d6 d5 d4 d3 d2 d1 d0 00000000 00000000B

(R) "0" "0" "0" "0" "0" "0" d9 d8

245


12.2.4 A/D Converter Test Register

This section explains the configuration and functions of the A/D converter test register.

A/D Converter Test Register

Figure 12.2-5 shows the bit configuration of the A/D converter test register.

Figure 12.2-5 Bit Configuration of the A/D Converter Test Register

[bit15 to bit0] TEST

These are the A/D converter test register bits.

Note:

Do not access this register.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

TEST TEST 00 00H

(R/W)

246


12.3 Operation of the 10-Bit A/D Converter

This section explains A/D conversion started by software and an external trigger.

A/D Conversion Started by Software

To perform A/D conversion started by software, select the required channel from analog inputpins AN0 to AN9. Write 1 to the corresponding bit of the ADCH register to enable A/D conversion.

Single channel

If only one channel is selected as the analog input pin for conversion, writing 1 to the STR bit ofthe ADCTH register starts software-started conversion and sets the BUSY bit of the ADCTLregister to 1.

Writing 1 to the STR bit again during conversion initializes the converter and restarts conversion.

After A/D conversion ends, the BUSY bit of the ADCTL register is reset to 0 and the INT bit of theADCTL register is set to 1. These status bits can be read to determine whether conversion hasended. To generate an interrupt to complete conversion, set the INTE bit of the ADCTL register to1 beforehand.

Multiple channels (scan conversion)

If multiple channels are selected as the analog input pins for conversion, the converter performsA/D conversion for the first selected channel and then stores the conversion result in the registercorresponding to the channel. The converter then repeats this process for the remaining selectedchannels.

Writing 1 to the corresponding bit of the ADCTH register to select the channel for conversion andwriting 1 to the STR bit of the ADCTH register starts conversion and sets the BUSY bit of theADCTL register to 1. The channels are converted sequentially from 0 to 9. If a channel is notselected in the ADCTH register, the converter skips that channel and starts conversion for thenext selected channel.

Writing 1 to the STR bit again during conversion initializes the converter and restarts conversionfor the selected channels in the order of 0 to 9.

When A/D conversion for all selected channels ends, the BUSY bit of the ADCTL register is resetto 0 and the INT bit of the ADCTL register is set to 1. To generate an interrupt to completeconversion, set the INTE bit of the ADCTL register to 1 beforehand.

The results of A/D conversion are stored in the registers of individual channels.

A/D Conversion Started by External Trigger

If external trigger start is enabled (ADCTH: TRG = 1), detection of a rising edge at external pinATRG starts A/D conversion. If the signal for A/D conversion by software is received when theexternal trigger is enabled, conversion is also started. If a rising edge is detected again atexternal pin ATRG during A/D conversion, conversion is continued and the edge is ignored.

247


248

CHAPTER 13U-TIMER

This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER operation.

13.1 Overview

13.2 U-TIMER Registers

13.3 U-TIMER Operation

249

CHAPTER 13 U-TIMER

13.1 Overview

This section provides an overview and a block diagram of the U-TIMER (16 bit timer for UART baud rate generation).

Overview of the U-TIMER

The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Use a combinationof a chip operating frequency and a reload value of the U-TIMER to specify a baud rate.

The MB91319 has five built-in channels for this timer.

Block Diagram

Figure 13.1-1 shows the block diagram of the U-TIMER.

Figure 13.1-1 Block Diagram of the U-TIMER

0

0

15

15

UTIMR (reload register)

load

UTIM (timer)

clockunderflow

control

to UARTf.f.

(Peripheral Clock)φ

250

CHAPTER 13 U-TIMER

13.2 U-TIMER Registers

This section describes the configuration and functions of the registers used by the U-TIMER.

U-TIMER Registers

Figure 13.2-1 shows the registers used by the U-TIMER.

Figure 13.2-1 U-TIMER Registers

U-TIMER (UTIM)

Figure 13.2-2 shows the bit configuration of the U-TIMER (UTIM).

Figure 13.2-2 Bit Configuration of the U-TIMER (UTIM)

UTIM is a register that indicates the timer value. Use a 16-bit transfer instruction to access thisregister.

Reload Register (UTIMR)

Figure 13.2-3 shows the bit configuration of the reload register (UTIMR).

Figure 13.2-3 Bit Configuration of the Reload Register (UTIMR)

UTIMR is a register that stores the value to be reloaded into UTIM if UTIM underflows.

Be sure to use a 16-bit transfer instruction to access this register.

15 8 7 0UTIM (R)

UTIMR (W)UTIMC (R/W)

15 14 12 0

ch0ch1ch2

Address: 000064H b15 b14 b2 b1 b0Address: 00006CH

Address: 000074H

ch3 Address: 00007CH

ch4 Address: 000084H

R Access 0 Initial value

UTIM

15 14 12 0

ch0ch1ch2

Address: 000064H b15 b14 b2 b1 b0Address: 00006CH

Address: 000074H

ch3ch4

Address: 00007CH

Address: 000084H

W Access 0 Initial value

UTIMER

251

CHAPTER 13 U-TIMER

U-TIMER Control Register (UTIMC)

Figure 13.2-4 shows the bit configuration of the U-TIMER control register (UTIMC).

Figure 13.2-4 Bit Configuration of the U-TIMER Control Register (UTIMC)

UTIMC controls the operation of the U-TIMER.

Be sure to use a byte transfer instruction to access this register.

[bit7] UCC1 (U-timer Count Control 1)

This bit controls the U-TIMER counting method.

The U-TIMER can set a normal cycle, 2(n+1) as well as an odd-numbered division for the UART.

Set UCC1 to 1 to generate a cycle of 2n+3.

Examples:

1. UTIMR=5, UCC1=0 → Generation cycle =2n+2= 12 cycles

2. UTIMR=25, UCC1=1 → Generation cycle =2n+3= 53 cycles

3. UTIMR=60, UCC1=0 → Generation cycle =2n+2=122 cycles

Set UCC1 to 0 to use the U-TIMER as the interval timer.

[bit6, bit5] (reserved)


[bit4] UTIE (U-TIMER Interrupt Enable)

This bit is the interrupt enable bit for a U-TIMER underflow.

0: Interrupt disabled [initial value]

1: Interrupt enabled

Note:

Always write 0 to this bit because the MB91319 has no U-Timer interrupt.

7 6 5 4 3 2 1 0 UCC1 UNDR CLKS UTST UTCR

R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1

UTIEch0ch1ch2

Address: 000067H

Address: 00006FH

Address: 000077Hch3ch4

Address: 00007FH

Address: 000087H

AccessInitial value

UTIMC

UCC1 Operation

0 Normal operation α=2n+2 [initial value]

1 +1 mode α=2n+3

n is the setting value of UTIMR.α is the cycle of the output clock for UART.

252

CHAPTER 13 U-TIMER

[bit3] UNDR (UNDeR flow flag)

This bit is a flag indicating that an underflow has occurred. The UNDR bit is cleared at resetand when 0 is written to it. For a read by a read modify write instruction, 1 is always read.

Writing 1 to the UNDR has no effect.

[bit2] CLKS (clock select)

In the MB91319, always write 0 to this bit.

[bit1] UTST (U-TIMER STart)

This bit is the U-TIMER operation enable bit.

0: Stopped. Writing 0 during operation stops running of the U-TIMER. [initial value]

1: Writing 1 during operation does not stop the U-TIMER.

[bit0] UTCR (U-TIMER CleaR)

Writing 0 to UTCR clears the U-TIMER to 0000H (also clears the f.f. to 0).

The read value is always 1.

Precautions on the U-TIMER Control Register (UTIMC)

• In the stop state, assert the start bit UTST (started) to automatically reload data.

• In the stop state, assert both the clear bit UTCR and the start bit UTST at the same time toclear the counter to 0 and generate an underflow in the count-down immediately after thecounter is cleared.

• During operation, the clear bit UTCR is asserted to clear the counter to 0. As a result, a short,whisker-like pulse may be output in the output waveform, possibly causing the UART tomalfunction. While the output clock is being used, do not clear it using the clear bit.

• In the timer stop state, assert both bit1 (U-TIMER start bit: UTST) and bit0 (U-TIMER clear bit:UTCR) of the U-TIMER control register at the same time to set bit3 (underflow flag: UNDR) ofthis register when the counter is loaded after it has been cleared. At this timing, the internalbaud rate clock is set to level.

• If the device attempts to set and clear the underflow flag at the same time, the flag is set andthe clear operation becomes ineffective.

• Always write 0 to bit4 (UTIE) and bit0 (CLKS) of the U-TIMER control register (UTIMC).

• If the device attempts to write to and reload the data into the U-TIMER reload register at thesame time, old data is loaded into the counter. New data is loaded into the counter only in thenext reload timing.

• If the device attempts to clear and load T-TIMER at the same time, the timer clear operationtakes precedence.

253

CHAPTER 13 U-TIMER

13.3 U-TIMER Operation

This section describes calculation of a baud rate for the U-TIMER.

Calculation of Baud Rate

The UART uses the underflow flip-flop (f.f. in the block diagram shown in Figure 13.1-1) of thecorresponding U-TIMER (from U-TIMER0 to UART0, from U-TIMER1 to UART1, from U-TIMER2to UART2, from U-TIMER3 to UART3, or from U-TIMER4 to UART4) as the clock source for baudrates.

Asynchronous (start-stop synchronization) mode

The UART uses the U-TIMER output divided by 8.

CLK synchronous mode

bps = (2n+2) 8

n: UTIMR (reload value)φ: Peripheral machine clock frequencyUCC 1=0

(Varies depending on the gear)

φ

bps = (2n+3) 8

UCC 1=1φ

bps = (2n+2)

n: UTIMR (reload value)φ: Peripheral machine clock frequencyUCC 1=0

(Varies depending on the gear)

φ

φbps = (2n+3)

UCC 1=1

254

CHAPTER 14UART

This chapter describes the UART, the configuration and functions of registers, and UART operation.

14.1 Overview of the UART

14.2 UART Registers

14.3 Example of Using the UART

14.4 Example of Setting U-TIMER Baud Rates and Reload Values

255

CHAPTER 14 UART

14.1 Overview of the UART

The UART is a serial I/O port used to perform asynchronous (start-stop synchronization) communication or CLK synchronous communication. The UART has the features shown below. The MB91319 has five UART channels.

Features

The UART has the following features:

• Full-duplex double buffer

• Either asynchronous (start-stop synchronization) or CLK synchronous communication can beselected.

• Multiprocessor mode is supported.

• Fully programmable baud rate: An arbitrary baud rate can be set using a built-in timer. (Seethe item about the U-TIMER.)

• An external clock can be used to set a baud rate.

• Error detection functions (parity, framing, overrun)

• The transfer signal is an NRZ code.

• UARTs Ch0 to Ch2 can use an interrupt to start DMA transfer (UARTs Ch3 and Ch4 cannotstart DMA transfer).

256

CHAPTER 14 UART

Block Diagram

Figure 14.1-1 shows a block diagram of the UART.

Figure 14.1-1 Block Diagram of the UART

Receive clock

Receive interrupt(to CPU)

SCK (clock)

Send interrupt(to CPU)

Send clock

SO (send data)

Send shifter

Sendingstarts

SODR

Control signal

Clockselection

circuit

From U-TIMER

External clock SCK

SI (receive data)

Receive controlcircuit

Start bit detectioncircuit

Receive bitcounter

Receive paritycounter

Send controlcircuit

Send controlcircuit

Send bitcounter

Send paritycounter

Receive shifter

Receivingcompleted

SIDR

Receive status decision circuit

DMA receive error occurrence signal

(To DMC)

R-bus

SMRregister

SCR register

SSR register

Control signal

MD1 MD0

CS0

PEN P SBL CL A/D REC RXE TXE

PE ORE FRE RDRF TDRE BDSRIE TIE

257

CHAPTER 14 UART

14.2 UART Registers

This section describes the configuration and functions of the registers used by the UART.

Registers

Figure 14.2-1 shows the registers used by the UART.

Figure 14.2-1 UART Registers

15 8 7 0

SCR SMR (R/W)

SSR SIDR(R)/SODR(W) (R/W)

8bi t 8bi t

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0(SIDR /SODR)

PE ORE FRE RDRF TDRE BDS RIE TIE (SSR)

MD1 MD0 - - CS0 - - - (SMR)

PEN P SBL CL A/D REC RXE TXE (SCR)

Serial status register

Serial mode register

Serial control register

Serial input registerSerial output register

258

CHAPTER 14 UART

14.2.1 Serial Mode Register (SMR)

The serial mode register (SMR) specifies the UART operating mode.Set an operating mode while operation is stopped. Do not write to this register while operation is in progress.

Serial Mode Register (SMR)

Figure 14.2-2 shows the bit configuration of the serial mode register (SMR).

Figure 14.2-2 Bit Configuration of the Serial Mode Register (SMR)

The SMR specifies the UART operating mode. Set the operating mode while operation isstopped. Do not write to this register during operation.

The following describes the functions of the serial mode register (SMR) bits.

[bit7, bit6] MD1, MD0 (MoDe select)

These bits select a UART operating mode.

Table 14.2-1 shows the settings for the UART operating modes.

Note:

In Mode 1, which is CLK asynchronous mode (multiprocessor), more than one slave CPU can beconnected to one host CPU. Since this resource cannot identify the data format of received data,however, only the master in multiprocessor mode is supported. Because the parity check functioncannot be used, set PEN of the SCR register to 0.

7 6 5 4 3 2 1 0 Initial value SMR

Address ch0 000063H MD1 MD0 CS0 00--0---B

ch1 00006BH ch2 000073H

ch3 00007BH

ch4 000083H

R/W R/W W

Table 14.2-1 Settings for UART Operating Modes

Mode MD1 MD0 Operating mode

0 0 0Asynchronous (start-stop synchronization) normal mode [initial value]

1 0 1Asynchronous (start-stop synchronization) multiprocessor mode

2 1 0 Clock synchronous mode

− 1 1 Setting disabled

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CHAPTER 14 UART


These bits are reserved. Always write 1 to these bits.

[bit3] CS0 (Clock Select)

This bit selects the UART operating clock.

Table 14.2-2 shows the UART operating clocks.


These bits are reserved. Always write 0 to these bits.

[bit0] (reserved)


Table 14.2-2 UART Operating Clocks

CS0 Operating clock

0 Built-in timer (U-TIMER) [initial value]

1 External clock

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14.2.2 Serial Control Register (SCR)

The serial control register (SCR) controls the transfer protocol that is used for serial communication.This section describes the configuration and functions of the serial control register (SCR)

Serial Control Register (SCR)

The SCR controls the transfer protocol that is used for serial communication.

Figure 14.2-3 shows the bit configuration of the serial control register (SCR).

Figure 14.2-3 Bit Configuration of the Serial Control Register (SCR)

[bit7] PEN (Parity Enable)

This bit specifies whether to add parity in serial communication when data communication isperformed.

Table 14.2-3 shows the parity.

Note:

Parity can be added only in normal mode (Mode 0) of asynchronous (start-stop synchronization)communication mode. No parity can be added in multiprocessor mode (Mode 1) or CLK synchronouscommunication mode (Mode 2).

Address: ch0 000062H PEN P SBL CL A/D REC RXE TXE 00000100B

7 6 5 4 3 2 1 0 Initial value

R/W R/W R/W R/W R/W W R/W R/W

SCR

ch1 00006AHch2 000072H

ch3 00007AH

ch4 000082H

Table 14.2-3 Parity

PEN Function

0 No parity [initial value]

1 Parity

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CHAPTER 14 UART

[bit6] P (Parity)

This bit specifies that even or odd parity be added to perform data communication.

Table 14.2-4 shows whether the parity is even or odd.

[bit5] SBL (Stop Bit Length)

This bit specifies the number of stop bits, which marks the end of a frame in asynchronous(start-stop synchronization) communication.

Table 14.2-5 shows the stop bit length.

[bit4] CL (Character Length)

This bit specifies the data length of one frame that is sent or received.

Table 14.2-6 shows the data length of one frame.

Note:

7-bit data can be handled only in normal mode (Mode 0) of asynchronous (start-stopsynchronization) communication mode. Use 8-bit data in multiprocessor mode (Mode 1) or CLKsynchronous communication mode (Mode 2).

[bit3] A/D (Address/Data)

This bit specifies the data format of a frame that is sent or received in multiprocessor mode(Mode 1) of asynchronous (start-stop synchronization) communication mode.

Table 14.2-4 Even or Odd Parity

P Parity

0 Even parity [initial value]

1 Odd parity

Table 14.2-5 Stop Bit Length

SBL Stop bit length

0 1 stop bit [initial value]

1 2 stop bits

Table 14.2-6 Data Length of One Frame

CL Data length of one frame

0 7 bits [initial value]

1 8 bits

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CHAPTER 14 UART

Table 14.2-7 shows the data format of a frame.

[bit2] REC (Receiver Error Clear)

Write 0 to this bit to clear the error flags (PE, ORE, and FRE) in the SSR register.

Writing 1 to this bit has no effect. 1 is always read from this bit.

[bit1] RXE (Receiver Enable)

This bit controls the UART receive operation.

Table 14.2-8 shows the UART receive operation.

Note:

If a receive operation is disabled while it is in progress (while data is being input to the receive shiftregister), reception of the frame is completed. The receive operation is stopped when the receiveddata is stored in the receive data buffer register (SIDR).

[bit0] TXE (Transmitter Enable)

This bit controls the UART send operation.

Table 14.2-9 shows the UART send operation.

Note:

If a send operation is disabled while it is in progress (while data is being output from the transmissionregister), sending is stopped when no more send data is stored in the send data buffer register(SODR).

Table 14.2-7 Data Format of Frame

A/D Data format of frame

0 Data frame [initial value]

1 Address frame

Table 14.2-8 UART Receive Operation

RXE Enabling or disabling the receive operation

0 Disables receive operation. [initial value]

1 Enables receive operation.

Table 14.2-9 UART Send Operation

TXE Enabling or disabling send operation

0 Disables send operation. [initial value]

1 Enables send operation.

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14.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

These registers are data buffer registers for receiving and sending.

Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

Figure 14.2-4 shows the bit configurations of the serial input data register (SIDR) and the serialoutput data register (SODR).

Figure 14.2-4 Bit Configurations of the Serial Input Data Register (SIDR) and the Serial Output Data Register (SODR)

These registers are data buffer registers for sending and receiving.

If the data length is seven bits, bit7 (D7) of SIDR and SODR contains invalid data. AccessingSIDR and SODR when BDS = 1 switches the high-order and low-order data on the bus. As aresult, it appears that bit0 (D0) is ignored.

Write to the SODR register only while the TDRE bit of the SSR register is 1.

Note:

Writing to the register with this address means writing to the SODR register. Reading from theregister with this address means reading from the SIDR register.

Address: ch0 000061H D7 D6 D5 D4 D3 D2 D1 D0


R R R R R R R Rch1 000069Hch2 000071Hch3 000079Hch4 000081H

Address: Same as above D7 D6 D5 D4 D3 D2 D1 D0

7 6 5 4 3 2 1 0

W W W W W W W W

SIDR

SODR

XXXXXXXXB

XXXXXXXXB

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14.2.4 Serial Status Register (SSR)

The serial status register (SSR) consists of flags that indicate the operation state of the UART.This section describes the configuration and functions of the serial status register (SSR).

Serial Status Register (SSR)

Figure 14.2-5 shows the bit configuration of the serial status register (SSR)

Figure 14.2-5 Bit Configuration of the Serial Status Register (SSR)

The SSR is configured from flags that indicate the operating status of the UART.

Address: ch0 000060H PE ORE FRE RDRF TDRE BDS RIE TIE 00001000B


R R R R R R/W R/W R/Wch1 000068Hch2 000070Hch3 000078Hch4 000080H

SSR

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CHAPTER 14 UART

Functions of Bits in the Serial Status Register (SSR)

The following describes the functions of the serial status register (SSR) bits.

[bit7] PE (Parity Error)

This bit, which is an interrupt request flag, is set when a parity error occurs during reception.

To clear the flag when it has been set, write 0 to the REC bit (bit10) of the SCR register.

If the PE bit is set, the SIDR data becomes invalid.

Table 14.2-10 shows the parity error interrupt request flag.

[bit6] ORE (Over Run Error)

This bit, which is an interrupt request flag, is set when an overrun error occurs duringreception.

To clear the flag when it has been set, write 0 to the REC bit of the SCR register.

If the ORE bit is set, the SIDR data becomes invalid.

Table 14.2-11 shows the overrun error interrupt request flag.

[bit5] FRE (FRaming Error)

This bit, which is an interrupt request flag, is set when a framing error occurs during reception.

To clear the flag when it has been set, write 0 to the REC bit of the SCR register.

If the FRE bit is set, the SIDR data becomes invalid.

Table 14.2-12 shows the framing error interrupt request flag.

Note:

Switch the internal and external baud rate clocks using bit3 of the serial mode register only while theUART is stopped, since the switching takes effect immediately after writing.

Bit3 of the serial mode register is write-only.

Table 14.2-10 Parity Error Interrupt Request Flag

PE Occurrence of parity error

0 No parity error has occurred. [initial value]

1 A parity error has occurred.

Table 14.2-11 Overrun Error Interrupt Request Flag

ORE Occurrence of overrun error

0 No overrun error has occurred. [initial value]

1 An overrun error has occurred.

Table 14.2-12 Framing Error Interrupt Request Flag

FRE Occurrence of framing error

0 No framing error has occurred. [initial value]

1 A framing error has occurred.

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CHAPTER 14 UART

[bit4] RDRF (Receiver Data Register Full)

This bit, which is an interrupt request flag, indicates that the SIDR register has receive data.

This bit is set when receive data is loaded into the SIDR register. It is automatically clearedwhen the data is read from the SIDR register.

Table 14.2-13 shows the receive data interrupt request flag.

[bit3] TDRE (Transmitter Data Register Empty)

This bit, which is an interrupt request flag, indicates whether send data can be written toSODR.

This bit is cleared when send data is written to the SODR register. It is set again when thewritten data is loaded into the send shiftier and begins to be transferred, indicating that thenext send data can be written.

Table 14.2-14 shows the send data interrupt request flag.

[bit2] BDS (Bit Direction Select)

This bit selects the transfer direction.

Table 14.2-15 shows the transfer direction selection bit.

Note:

Because the high-order and low-order data are switched when the serial data register is written to orread, the data will become invalid if the bit is rewritten after data is written to the SDR register. If theSODR register and BDS are rewritten at the same time using halfwords (16 bits), data will be writtento the SODR register based on the BDS value before rewriting.

Table 14.2-13 Receive Data Interrupt Request Flag

RDRF Presence of receive data

0 No receive data exists. [initial value]

1 Receive data exists.

Table 14.2-14 Send Data Interrupt Request Flag

TDRE Disabling or enabling writing of send data

0 Disables writing of send data.

1 Enables writing of send data. [initial value]

Table 14.2-15 Transfer Direction Selection Bit

BDS Transfer direction

0Sends starting from the least significant bit (LSB). [initial value]

1 Sends starting from the most significant bit (MSB).

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CHAPTER 14 UART

[bit1] RIE (Receiver Interrupt Enable)

This bit controls a reception interrupt.

Table 14.2-16 shows the receive interrupt.

Note:

Receive interrupt sources include errors due to PE, ORE, and FRE as well as normal receive due toRDRF.

[bit0] TIE (Transmitter Interrupt Enable)

This bit controls send interrupt.

Table 14.2-17 shows the send interrupt.

Note:

Send interrupt sources include send requests due to TDRE.

Table 14.2-16 Receive Interrupt

RIE Disabling or enabling receive interrupts

0 Disables receive interrupt. [initial value]

1 Enables receive interrupt.

Table 14.2-17 Send Interrupt

TIE Disabling or enabling send interrupts

0 Disables send interrupt. [initial value]

1 Enables send interrupt.

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14.2.5 UART Operation

The UART has two operating modes: asynchronous (start-stop synchronization) mode and clock mode.Asynchronous (start-stop synchronization) mode consists of normal and multiprocessor mode.This section describes the operation of these operating modes.

Operating Modes

The UART has the operating modes shown in Table 14.2-18. Set a value in the SMR and SCRregisters to switch mode.

Note:

The stop bit length in asynchronous (start-stop synchronization) mode can be specified only for asend operation. The stop bit length is always one bit for a receive operation. Since operation ispossible only in the above modes, do not make any other setting.

Table 14.2-18 UART Operating Modes

Mode Parity Data length Operating mode Stop bit length

0Yes/No 7 Asynchronous (start-stop

synchronization)normal mode 1 bit

or2 bits

Yes/No 8

1 No 8+1Asynchronous (start-stop

synchronization)multiprocessor mode

2 No 8 Clock mode No

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Selecting a Clock for the UART

Internal timer

If you select the U-TIMER by setting CS0 to 0, the baud rate is determined according to thereload value set for the U-TIMER. At this time, you can calculate the baud rate as follows:

Asynchronous (start-stop synchronization): φ/(8 × β)

CLK synchronous: φ/β

φ: Peripheral machine clock frequency

β: Cycle defined for the U-TIMER (2n+2 or 2n+3; n is the reload value.)

In asynchronous (start-stop synchronization) mode, data can be transferred in the range from -1% to +1% of the specified baud rate.

External clock

If you select an external clock by setting CS0 to 1, the baud rate is as follows (the frequency ofthe external clock is assumed to be f):

Asynchronous (start-stop synchronization): f/8

CLK synchronous: f

Note:

However, that the maximum value for f is 3.125 MHz.

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14.2.6 Asynchronous (Start-stop Synchronization) Mode

When the UART is used in Operating Mode 0 (normal mode) or Operating Mode 1 (multiprocessor mode), the asynchronous transfer method is used.

Transfer Data Format

UART handles only data in the NRZ (Non Return to Zero) format.

Figure 14.2-6 shows the data format.

Figure 14.2-6 Transfer Data Format (Modes 0 and 1)

As shown in Figure 14.2-6, the transfer of data always starts with the start bit (L level data),continues as long as the data bit length specified in LSB First, and ends with a stop bit (H leveldata). If an external clock is selected, you always must input a clock.

The data length can be set to 7 or 8 bits in normal mode (Mode 0), but must be set to 8 bits inmultiprocessor mode (Mode 1). In multiprocessor mode, no parity can be added; instead, the A/Dbit is always added.

Receive Operation

If the RXE bit (bit1) of the SCR register is set to 1, a receive operation is always in progress.

If a start bit appears on the receive line, one-frame data is received according to the data formatspecified in the SCR register. If an error occurs before reception of one frame is completed, theerror flag is set and then the RDRF flag (bit4 of the SSR register) is set. If, at this time, the RIE bit(bit1) of the same SSR register is set to 1, a receive interrupt is generated for the CPU. Check theflags of the SSR register and read the SIDR register if normal reception has occurred or performthe necessary processing if an error has occurred.

The RDRF flag is cleared when the SIDR register is read.

Send Operation

If the TDRE flag (bit3) of the SSR register is set to 1, send data is written to the SODR register. If,at this time, the TXE bit (bit0) of the SCR register is set to 1, transmission occurs.

The TDRE flag is set again when the data set in the SODR register is loaded into the send shiftregister and begins to be transferred, indicating that the next send data can be set. If, at this time,the TIE bit (bit0) of the same SSR register is set to 1, a send interrupt requesting that the senddata be set in the SODR register is generated for the CPU.

The TDRE flag is cleared if data is set in the SODR register.

SI,SO

0 1 0 1 1 0 0 1 0 1 1Start LSB MSB Stop (Mode 0)

A/D Stop (Mode 1)

Data that has been transferred is 01001101B.

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14.2.7 Clock Synchronous Mode

If the UART is used in Operating Mode 2, the clock synchronous transfer method is used.

Transfer Data Format

The UART handles only data in the NRZ (Non Return to Zero) format.

Figure 14.2-7 shows the relationship between send and receive clocks and data.

Figure 14.2-7 Transfer Data Format (Mode 2)

When the internal clock (U-TIMER) has been selected, a data receive synchronous clock isautomatically generated as soon as data is received. While an external clock has been selected,you must check that data exists in the send data buffer SODR register of the send side UART(TDRE flag is 0) and then supply an accurate clock for one byte. Before sending starts and after itends, be sure to set the mark level.

The data length is 8 bits only, and no parity can be added. Only overrun errors are detectedbecause there is no start or stop bit.

Writing to SODR

SCK

RXE, TXE

SI, SO

1 0 1 1 0 0 1 0

Data that has been transferred is 01001101B.

Mark

LSB MSB (Mode 2)

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CHAPTER 14 UART

Initialization

The following shows the setting values of the control registers required to use CLK synchronousmode.

• SMR register

• MD1, MD0: 10

• CS: Specifies the clock input.

• PFR (port function) register

• SCE: Set to 1 for an internal timer and to 0 for an external clock.

• SOE: Set to 1 for send and to 0 for receive only.

• SCR register

• PEN: 0

• P,SBL,A/D: These bits are meaningless.

• CL: 1

• REC: 0 (to initialize the register)

• RXE, TXE: At least one of the bits must be set to 1.

• SSR register

• RIE: Set to 1 to enable interrupts and to 0 to disables interrupts.

• TIE: 0

Start of Communication

Write to the SODR register to start communication.

If only reception is performed, dummy send data must be written to the SODR register.

End of Communication

Check for the end of communication by making sure that the RDRF flag of the SSR register haschanged to 1. Use the ORE bit of the SSR register to check that communication has beenperformed correctly.

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14.2.8 Occurrence of Interrupts and Timing for Setting Flags

The UART has five flags and two interrupt sources.The five flags are PE, ORE, FRE, RDRF, and TDRE. PE means parity error, ORE means overrun error, and FRE means framing error. These flags are set when an error occurs during reception and are then cleared when 0 is written to REC of the SCR register. RDRF is set when receive data is loaded into the SIDR register and then cleared when data is read from the SIDR register. Mode 1 does not provide a parity detection function. Mode 2 does not provide a parity detection function or a framing error function. TDRE is set when the SODR register is empty, and writing to it is enabled and then cleared when data is written to the SODR register.

Occurrence of Interrupts and Timing for Setting Flags

There are two interrupt sources, one for receiving and one for sending. During receiving, aninterrupt is requested due to PE, ORE, FRE, or RDRF. During sending, an interrupt is requesteddue to TDRE. The following shows the timing for setting the interrupt flags in each of thesemodes.

Receive operation in Mode 0

The PE, ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receivetransfer is completed, causing an interrupt request to be generated for the CPU. The SIDR data isinvalid while PE, ORE, and FRE are active.

Figure 14.2-8 shows the timing for setting ORE, FRE, and RDRF in Mode 0.

Figure 14.2-8 Timing for Setting ORE, FRE, and RDRF (Mode 0)

Data

PE,ORE,FRE

RDRF

Receive interrupt

D6 D7 Stop

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CHAPTER 14 UART

Receive operation in Mode 1

The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transferis completed, causing an interrupt request to be generated for the CPU. The data indicating anaddress or the data in bit9 is invalid because the length of data that can be received is 8 bits. TheSIDR data is invalid while ORE and FRE are active.

Figure 14.2-9 shows the timing for setting ORE, FRE, and RDRF in Mode 1.

Figure 14.2-9 Timing for Setting ORE, FRE, and RDRF (Mode 1)

Reception operation in Mode 2

The ORE and RDRF flags are set when the last data (D7) is set after the reception transfer iscompleted, generating an interrupt request to the CPU. The SIDR data is invalid while ORE isactive.

Figure 14.2-10 shows the timing of setting ORE and RDRF in Mode 2.

Figure 14.2-10 Timing of Setting ORE and RDRF (Mode 2)

Data

ORE,FRE

RDRF

Receive interrupt

D6 Address/Data Stop

Data

ORE

RDRF

Receive interrupt

D5 D6 D7

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CHAPTER 14 UART

Send operation in modes 0, 1, and 2

TDRE is cleared when data is written to the SODR register. This bit is set when data istransferred to the internal shift register and the next data can be written, causing an interruptrequest to be generated for the CPU. If 0 is written to TXE of the SCR register (as well as RXE inmode 2) during a send operation, TDRE of the SSR register is set to 1, disabling the UART sendoperation after the transmission shiftier stops. The device sends data written to the SODRregister before transmission stops after 0 is written to the TXE of the SCR register (as well asRXE in mode 2) during the send operation.

Figure 14.2-11 shows the timing for setting TDRE in Modes 0 and 1. Figure 14.2-12 shows thetiming for setting TDRE in Mode 2.

Figure 14.2-11 Timing for Setting TDRE (Modes 0 and 1)

Figure 14.2-12 Timing for Setting TDRE (Mode 2)

Precautions on Usage

Writing to the SODR register starts communication. Even for receive only, dummy send datamust be written to the SODR register.

Set the operating mode while operation is stopped. Data send and received while the operatingmode is being set is unpredictable.

Writing to SODR

TDRE

SO interrupt

SO output

Interrupt request to CPU

ST: Start bit, D0 to D7: Data bitsSP: Stop bit, A/D: Address/data multiplexer

ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3A/D

Writing to SODR

TDRE

SO interrupt

SO output

Interrupt request to CPU

D0 to D7: Data bits

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

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14.3 Example of Using the UART

This section provides an example of using the UART. Mode 1 is used if more than one slave CPU is connected to a single host CPU.

Example of Using the UART

Figure 14.3-1 shows an example of constructing a system using mode 1. This resource supportsonly a communications interface on the host.

Figure 14.3-1 Example of Constructing a System Using Mode 1

Communication starts when the host CPU transfers address data. Address data is data usedwhen A/D of the SCR register is set to 1. This data is used to select a destination slave CPU,enabling communication with the host CPU. Normal data is data used when A/D of the SCRregister is set to 0. Figure 14.3-2 shows the flowchart.

In this mode, set the PEN bit of the SCR register to 0, since the parity check function cannot beused.

SO

SI

Host CPU

SO SI SO SI

Slave CPU #0 Slave CPU #1

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CHAPTER 14 UART

Figure 14.3-2 Communication Flowchart in Mode 1

(Host CPU)

START

Set transfer mode to 1.

Set 0 in A/D.

Enable receive operation.

Communicate with a slave CPU.

No

No

Yes

Yes

END

Set data used to select slave CPUs in D0 to D7, set 1 in A/D, and

transfer one byte.

Communicationcompleted?

Communicate withother slave

CPUs?

Disable the receive operation.

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14.4 Example of Setting U-TIMER Baud Rates and Reload Values

This section provides an example of setting U-TIMER baud rates and reload values.

Example of Setting U-TIMER Baud Rates and Reload Values

Table 14.4-1 shows setting values to be used in asynchronous (start-stop synchronization) mode.Table 14.4-2 shows setting values to be used in CLK synchronous mode.

A frequency in the tables represents a peripheral machine clock frequency. UCC1 is a value tobe set in the UCC1 bit of the UTIMC register of the U-TIMER.

The U-Timer reload value is displayed as a decimal value.

Table 14.4-1 Setting Values in Asynchronous (Start-Stop Synchronization) Mode

Baud rate (bps) ms φ=20MHz φ=10MHz

1200 833.33 1040 (UCC1=1) 520 (UCC1=0)

2400 416.67 520 (UCC1=0) 259 (UCC1=1)

4800 208.33 259 (UCC1=1) 129 (UCC1=0)

9600 104.17 129 (UCC1=0) 64 (UCC1=0)

19200 52.08 64 (UCC1=0) 31 (UCC1=1)

38400 26.04 31 (UCC1=1) -

57600 17.36 20 (UCC1=1) -

115200 8.681 - * -

- -

10400 96.15 119 (UCC1=0) 59 (UCC1=0)

31250 32.00 39 (UCC1=0) 19 (UCC1=0)

62500 16.00 19 (UCC1=0) 9 (UCC1=0)

*: When φ = 20.27MHz, the value of 115200 can be used.φ = Peripheral machine clock frequency

Table 14.4-2 Setting Values in CLK Synchronous Mode

Baud rate (bps) ms φ=20MHz φ=10MHz

250K 4.00 39 (UCC1=1) 19 (UCC1=1)

500K 2.00 19 (UCC1=1) 9 (UCC1=0)

1M 1.00 9 (UCC1=0) 4 (UCC1=0)

φ = Peripheral machine clock frequency

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CHAPTER 14 UART

280

CHAPTER 15

I2C INTERFACE

This chapter describes the I2C interface, the

configuration and functions of registers, and I2C interface operation.

15.1 Overview of the I2C Interface

15.2 I2C Interface Registers

15.3 I2C Interface Operation

15.4 Operation Flowcharts

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CHAPTER 15 I2C INTERFACE

15.1 Overview of the I2C Interface

The I2C interface is a serial I/O port that supports Inter IC BUS.

Features

The I2C interface serves as a master or slave device on the I2C bus and has the followingfeatures:

• Master or slave sending and receiving

• 16-byte internal FIFO for both transmission and reception

• Arbitration function

• Clock synchronization function

• Slave address and general call address detection function

• Transfer direction detection function

• Function that generates and detects a repeated START condition

• Bus error detection function

• 10-bit and 7-bit slave addresses

• Slave address reception acknowledge control in master mode

• Compound slave addresses available

• Interrupt enabled for a transmission or bus error

• Standard mode (maximum of 100 Kbps) and high-speed mode (maximum of 400 Kbps at themaximum) available

Multi-master does not support.

282


FIFO Operational Overview

To execute transfer using FIFO, set FEN=1

This macro usually sets SCL=L when INT=1 and so that I2C bus is waited. However, SCL=L isnot set when IFCR.TED=1.

Transmission of 7-bit address master

During slave address transmission, FIFO is not used. Write the slave address into IDAR and setMSS=1.

INT is set to 1 (INT=1) after transmitting the slave address. If data of arbitrary byte length iswritten into IFDR while INT=1, the data is stored in the FIFO. Then, when INT is set to 0 (INT=0),either the FIFO is emptied, or data is transmitted without generating any acknowledge by theslave.

When the FIFO is emptied, INT is set to 1(INT=1, IFCR.TFE=1). To transmit data continuously,write the data into the IFDR and set INT=0. To stop the transfer, set MSS=0 (INT is set to 0(INT=0) automatically).

If the slave does not generate an acknowledge during the data transfer using FIFO, INT is set to1 (INT=1). In this case, set MSS=0 (INT is set to 0 (INT=0) automatically). Clear the remainingdata in the FIFO by setting IFCR.FCL=1.

If arbitration is lost during the data transmission using FIFO, clear the FIFO and then start thetransfer from the beginning.

Transmission of 10-bit address master

During slave address transmission, FIFO is not used. Write the primary slave address into IDARand set MSS=1. INT is set to 1 (INT=1) after transmitting the primary slave address. Then, writethe secondary slave address into the IDAR and set INT=0.

INT is set to 1 (INT=1) after transmitting the secondary slave. If data of arbitrary byte length iswritten into IFDR while INT=1, the data is stored in the FIFO. Then, when INT is set to 0 (INT=0),the data is transmitted until the FIFO is emptied.

When the FIFO is emptied, INT is set to 1(INT=1, IFCR.TFE=1). To transmit data continuously,write the data into the IFDR and set INT=0. To stop the transfer, set MSS=0 (INT is set to 0(INT=0) automatically).

If the slave does not generate an acknowledge during the data transfer using FIFO, INT is set to1 (INT=1). In this case, set MSS=0 (INT is set to 0 (INT=0) automatically). Clear the remainingdata in the FIFO by setting IFCR.FCL=1.

If arbitration is lost during the data transmission using FIFO, clear the FIFO and then start thetransfer from the beginning.

283


Reception of 7-bit address master

During slave address transmission, FIFO is not used. Write the slave address into IDAR and setMSS=1.

INT is set to 1 (INT=1) after transmitting the slave address. While INT=1, set receiving dataamount into FIFO register (IFRN), and then set INT=0. FIFO captures the amount of data as setin the IFRN register. For each byte received, FRN of the IFRN register is decremented, andwhen IFRN.FRN value becomes 0 (IFRN.FRN=0), INT is set to 1(INT=1, IFCR.FRED=1). Readout all data in the FIFO from the IFDR while INT=1.

To receive data continuously, set the IFRN register with the FIFO empty, and then set INT=0. Tostop the transfer, set MSS=0 (INT is set to 0 (INT=0) automatically).

If FACK=0 is set in the IFRN register, an acknowledge is not generated for the last receiving data(when IFRN.FRN=1).

Reception of 10-bit address master

During slave address transmission, FIFO is not used. Write the primary slave address into IDARand set MSS=1. INT is set to 1 (INT=1) after transmitting the primary slave address. Then, writethe secondary slave address into the IDAR and set INT=0. INT is set to 1 (INT=1) aftertransmitting the secondary slave address. After that, read 8th bit of the primary slave addressand write it into the IDAR, and set SSC=1.

INT is set to 1 (INT=1) after transmitting the slave address. While INT=1, set receiving dataamount into FIFO register (IFRN), and then set INT=0. FIFO captures the amount of data as setin the IFRN register. For each byte received, FRN of the IFRN register is decremented, andwhen IFRN.FRN value becomes 0 (IFRN.FRN=0), INT is set to 1(INT=1, IFCR.FRED=1). Readout all data in the FIFO from the IFDR while INT=1.

To receive data continuously, set the IFRN register with the FIFO empty, and then set INT=0. Tostop the transfer, set MSS=0 (INT is set to 0 (INT=0) automatically).

If FACK=0 is set in the IFRN register, an acknowledge is not generated for the last receiving data(when IFRN.FRN=1).

Transmission of 7-bit address slave

INT is set to 1 (INT=1) after receiving slave address (slave address is not captured into FIFO). Ifdata of arbitrary byte length is written into IFDR while INT=1, the data is stored in the FIFO.When INT is set to 0 (INT=0) after writing the data, the amount of data written in the FIFO istransmitted. When the FIFO is emptied, INT is set to 1(INT=1, IFCR.TFE=1). Write thetransmission data continuously and set INT=0. These processes will be repeated until the masteroutputs a repeat "START" condition or a "STOP" condition.

When either a repeat "START" condition or a "STOP" condition is detected, TED of the IFCR isset to 1. In this case, SCL is not set to L. Clear the FIFO if there is any remaining data in it.Write 0 into TED, and end the FIFO.

284


Transmission of 10-bit address slave

INT is set to 1 (INT=1) after receiving 10-bit slave address (slave address is not captured intoFIFO), so set INT=0. Then, when a repeat "START" condition is detected, TED of the IFCR is setto 1. In this case, SCL is not set to L. Set TED=0.

INT is set to 1 (INT=1) after receiving slave address with a read request (slave address is notcaptured into FIFO). If data of arbitrary byte length is written into IFDR while INT=1, the data isstored in the FIFO. When INT is set to 0 (INT=0) after writing the data, the amount of data writtenin the FIFO is transmitted. When the FIFO is emptied, INT is set to 1(INT=1, IFCR.TFE=1).Write the transmission data continuously and set INT=0. These processes will be repeated untilthe master outputs a repeat "START" condition or a "STOP" condition.

When either a repeat "START" condition or a "STOP" condition is detected, TED of the IFCR isset to 1. In this case, SCL is not set to L. Clear the FIFO If there is any remaining data in it.Write 0 into TED, and end the FIFO.

Reception of 7-bit slave and 10-bit slave

INT is set to 1 (INT=1) after receiving slave address (slave address is not captured into FIFO).While INT=1, set receiving data amount into FIFO register (IFRN), and then set INT=0. FIFOcaptures the amount of data as set in the IFRN register. For each byte received, FRN of theIFRN register is decremented, and when IFRN.FRN value becomes 0 (IFRN.FRN=0), INT is setto 1(INT=1, IFCR.FRED=1). Read out all data in the FIFO from the IFDR while INT=1.

Read the data from the FIFO, and set FRN register when FIFO is emptied. Then receivecontinuous data by setting INT=0. These processes will be repeated until the master outputs arepeat "START" condition or a "STOP" condition.

When either a repeat "START" condition or a "STOP" condition is detected, TED of the IFCR isset to 1. In this case, SCL is not set to L. Read all receiving data in the FIFO, write 0 into TED,and then end the FIFO.

If FACK=0 is set in the IFRN register, an acknowledge is not generated for the last receiving data(when IFRN.FRN=1). The receiving data with no acknowledge generation is captured into theFIFO.

Bus errors in FIFO operation

If a bus error occurs while FIFO is receiving data, the transfer process will be stopped. The dataduring the bus error is not captured into the FIFO.

If a bus error occurs while FIFO is transmitting data, the transfer process will be stopped.However, the number of bytes calculated as below will have been transferred.

Number of bytes transferred = Number of bytes written into FIFO - Number of bytes shown inIFN register - 1

State information is cleared during a bus error. To know whether FIFO is transmitting or receivingdata in any situation, the state information should be managed at the program level.

285


Block Diagram

Figure 15.1-1 shows a block diagram of the I2C interface.

Figure 15.1-1 Block Diagram of the I2C Interface

ICCR CS4 CS3 CS2 CS1 CS0

I BSR BB

RSC

LRB

TRX

ADT

AL

IBCR

SCC

IBCR

INT INTE

BEIE

BER

GCAA

ACK

MSS

2 3 4 5 32

Sync

IBSR

AAS

GCA

ITBA

IDAR

ITMK ISBA ISMK

ENTB RAL

FNSB

ICCR EN

ISMK

ITMK

Clock selection 2 (1/12)

Clock division 2

Shift clock generation

Shift clock edge change timing

I2C operation enable

R-b

us

Bus busy

Repeat start

Last Bit

Send/receive

First Byte

Error

Start/Stop condition detection

Arbitration lost detection

Interrupt request

End

GC-ACK permission

ACK permission

Master

Start

Start-stop conditiongeneration

Slave addresscomparisonGlobal call

Slave

NSF

ICCR

No

ise F

ilter

SCL0-2

SDA0- 2

SDA3

SCL3

SCL4

SDA4

SD

A3

SC

L3

SC

L2

SD

A2

enable

Register

I2C Input/output

I2C Input/output

I2C Input/output

IFDR

FIFO

Interrupt request 2

IFN

IFCR

TEDE

TED

FRED

TFE

FEN

FER

FCL

FN

IFRN

FACK

FRN

8

7

IRQ

286


15.2 I2C Interface Registers

This section describes the configuration and functions of registers used by the I2C interface.

I2C Interface Registers

Figure 15.2-1 shows the registers used by the I2C interface.

Figure 15.2-1 I2C Interface Registers

(Continued)

15 14 13 12 11 10 9 8Address: BER BEIE SCC MSS ACK GCAA INTE INT

R/W R/W W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0Initial value

ch0 0000B4H

ch1 0000C4H

ch2 0000D4H

ch3 0000E4H

Bus control register (IBCR)

7 6 5 4 3 2 1 0

BB RSC AL LRB TRX AAS GCA ADT

R R R R R R R R

0 0 0 0 0 0 0 0

Address:

Initial value

ch0 0000B5H

ch1 0000C5H

ch2 0000D5H

ch3 0000E5H

Bus status register (IBSR)

15 14 13 12 11 10 9 8TA9 TA8

R/W R/W

0 0

7 6 5 4 3 2 1 0TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0

R/W R/W R/W R/W R/W R/W

R R R R R R

R/W R/W

0 0 0 0 0 0

- - - - - -

0 0

Address:

Initial value

Initial value

ch0 0000B6H

ch1 0000C6H

ch2 0000D6H

ch3 0000E6H

10-bit slave address register (ITBA)

15 14 13 12 11 10 9 8ENTB RAL TM9 TM8

R/W R R/W R/W

0 0

R

-

R

-

R

-

R

- 1 1

7 6 5 4 3 2 1 0TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0R/W R/W R/W R/W R/W R/W R/W R/W

1 1 1 1 1 1 1 1

Address:

Initial value

Initial value

ch0 0000B8H

ch1 0000C8H

ch2 0000D8H

ch3 0000E8H

10-bit slave address mask register (ITMK)

287


(Continued)

7 6 5 4 3 2 1 0SA6 SA5 SA4 SA3 SA2 SA1 SA0R/WR R/W R/W R/W R/W R/W R/W00 0 0 0 0 0 0

Address:

Initial value

ch0 0000BBH

ch1 0000CBH

ch2 0000DBH

ch3 0000EBH

7-bit slave address register (ISBA)

15 14 13 12 11 10 9 8ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0R/W R/W R/W R/W R/W R/W R/W R/W0 1 1 1 1 1 1 1

Address:

Initial value

ch0 0000BAH

ch1 0000CAH

ch2 0000DAH

ch3 0000EAH

7-bit slave address mask register (ISMK)

7 6 5 4 3 2 1 0D7 D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W0 0 0 0 0 0 0 0

Address:

Initial value

ch0 0000BDH

ch1 0000CDH

ch2 0000DDH

ch3 0000EDH

Data register (IDAR)

15 14 13 12 11 10 9 8TEST EN CS4 CS3 CS2 CS1 CS0

W R/WNSFR/W R/W R/W R/W R/W R/W

0 0 0 1 1 1 1 1

Address:

Initial value

ch0 0000BEH

ch1 0000CEH

ch2 0000DEH

ch3 0000EEH

Clock control register (ICCR)

15 14 13 12 11 10 9 8FN4 FN3 FN2 FN1 FN0

R R R R R R R R0 0 0 0 0 0 0 0

Address:

Initial value

ch0 0000B0H

ch1 0000C0H

ch2 0000D0H

ch3 0000E0H

FIFO data count register (IFN)

7 6 5 4 3 2 1 0FRN4 FRN3 FRN2FACK FRN6 FRN5 FRN1 FRN0

R/W R/W R/W R/W R/W R/W R/W R/W0 0 0 0 0 0 0 0

Address:

Initial value

ch0 0000B1H

ch1 0000C1H

ch2 0000D1H

ch3 0000E1H

FIFO reception register (IFRN)

15 14 13 12 11 10 9 8TEDIEFCLFEN FER TED FRED TFE

R/W R/W - R/W R/W R R R0 0 - 0 0 0 0 0

Address:

Initial value

ch0 0000B2H

ch1 0000C2H

ch2 0000D2H

ch3 0000E2H

FIFO control register (IFCR)

7 6 5 4 3 2 1 0FD4 FD3 FD2FD7 FD6 FD5 FD1 FD0


Address:

Initial value

ch0 0000B3H

ch1 0000C3H

ch2 0000D3H

ch3 0000E3H

FIFO data register (IFDR)

288


15.2.1 Bus Status Register (IBSR)

The bus status register (IBSR) indicates the status of the I2C interface.This register is read-only.

Bus Status Register (IBSR)

Figure 15.2-2 shows the bit configuration of the bus status register (IBSR).

Figure 15.2-2 Bit Configuration of the Bus Status Register (IBSR)

This register is read-only for all bits. All bits are cleared when I2C interface operation is stopped(ICCR EN = 0).

[bit7] BB (Bus Busy)

This bit indicates the status of the I2C bus.

[bit6] RSC (Repeated Start Condition)

This bit is the repeated START detection bit.

This bit is cleared when the address data transfer ends (ADT=0) or when the STOP condition isdetected.

[bit5] AL (Arbitration Lost)

This bit is the arbitration lost detection bit.

Write 0 to the INT bit or 1 to the MSS bit of the IBCR register to clear this bit.

Arbitration loss is detected if:

• The transmission data does not match the data on the SDA line at the rising edge of SCL.

• A repeated START condition is generated in the first bit of the data by another master.

• The I2C interface cannot generate a START or STOP condition because the SCL line is drivento L by another slave device.

7 6 5 4 3 2 1 0BB RSC AL LRB TRX AAS GCA ADTR R R R R R R R0 0 0 0 0 0 0 0

Address:

Initial value

ch0 0000B5H

ch1 0000C5H

ch2 0000D5H

ch3 0000E5H

0 STOP condition detected

1 START condition detected (bus used)

0 Repeated START condition not detected

1 Repeated START condition detected while bus is being used

0 Arbitration lost not detected

1 Arbitration lost detected during master transmission

289


[bit4] LRB (Last Received Bit)

This bit is an acknowledge storage bit that stores an acknowledge from the receiving device.

This bit is ten if an acknowledge is detected (reception 9 bits). This bit is cleared if a START orSTOP condition is detected.

[bit3] TRX (Transferring Data)

This bit indicates the transmission status during a data transfer.

This bit is set to 1 if:

• A START condition occurs in master mode.

• Transfer of the first byte ends during read access (transmission) in slave mode.

• Data is being sent in master mode.


• The bus is idle (IBCR BB=0).

• An arbitration loss occurs.

• 1 is written to the SCC bit in the mask interrupt status (MSS=1, INT=1).

• The MSS bit is cleared in the mask interrupt status (MSS=1, INT=1).

• No acknowledge occurred for the last transfer byte in slave.

• Data is received in slave mode.

• Data is received from a slave in master mode.

[bit2] AAS (Addressed As Slave)

This bit is the slave addressing detection bit.

This bit is cleared when a (repeated) START or STOP condition is detected.

This bit is set when a 7-bit or 10-bit slave address is detected.

[bit1] GCA (General Call Address)

This bit is the general call address (00H) detection bit.

This bit is cleared when a (repeated) START or STOP condition is detected.

0 Slave acknowledge detected

1 Slave acknowledge not detected

0 Data transmission stopped

1 Data transmission in progress

0 The interface is not specified as a slave.

1 The interface is specified as a slave.

0 General call address is not received as a slave.

1 General call address is received as a slave.

290


[bit0] ADT (Address Data Transfer)

This bit is the slave address reception detection bit.

This bit is set to 1 if a START condition is detected. It is cleared after the second byte if theheader section of a slave address is detected during 10-bit write access. Otherwise, it is clearedafter the first byte.

"After the first or second byte" means the following:

• Writing 0 to the MSS bit during master interrupt (MSS=1, INT=1)

• Writing 1 to the SCC bit during master interrupt (MSS=1, INT=1)

• Clearing the INT bit

• Beginning of a transfer byte that is not used for the transfer destination as master or slave

0Received data is not a slave address (or the bus is idle).

1 Received data is a slave address.

291


15.2.2 Bus Control Register (IBCR)

This section describes the configuration and functions of the bus control register (IBCR).

Bus Control Register (IBCR)

Figure 15.2-3 shows the bit configuration of the bus control register (IBCR).

Figure 15.2-3 Bit Configuration of the Bus Control Register (IBCR)

Bits other than BER and BEIE are cleared if the I2C interface is stopped (ICCR EN=0).

[bit15] BER (Bus ERror)

This bit is the bus error interrupt request flag bit.

For a read by a read modify instruction, 1 is always read.

During writing

During reading

If this bit is set, the EN bit of the CCR register is cleared, the I2C interface is stopped, and datatransfer is halted. All bits of the IBSR and IBCR registers except BER and BEIE are cleared.

Clear this bit before the I2C interface is enabled (EN = 1) again.


• An illegal START or STOP condition at a specific location is detected (while an slave address

or data is being transferred). *

• The header section of a slave address is received during a 10-bit read access before 10-bit

write access with the first byte is performed. *

• A STOP condition is detected during transfer in master mode.

*: When the I2C interface is enabled during transfer, this detection flag is set after the first STOPcondition is received to prevent an incorrect bus error report from being issued.

15 14 13 12 11 10 9 8BER BEIE SCC MSS ACK GCAA INTE INTR/W R/W W R/W R/W R/W R/W R/W0 0 0 0 0 0 0 0

Address:

Initial value

ch0 0000B4H

ch1 0000C4H

ch2 0000D4H

ch3 0000E4H

0 Clears the bus error interrupt request flag.

1 Has no meaning.

0 Bus error not detected

1 Error condition detected

292


[bit14] BEIE (Bus Error Interrupt Enable)

This bit is the bus error interrupt enable bit.

An interrupt occurs if this bit is set to 1 and the BER bit is set to 1.

[bit13] SCC (Start Condition Continue)

This bit is the repeated [START] condition generation bit.

During writing


If 1 is written to this bit in master mode (MSS = 1, INT = 1), a repeated START condition isgenerated and the INT bit is automatically cleared.

[bit12] MSS (Master Slave Select)

This bit is the master or slave selection bit.

This bit is cleared when arbitration lost occurs during master transmission, causing slave mode tostart.

Write 0 to this bit during a master interrupt (MSS=1, INT=1) to automatically clear the INT bit.Then, generate a [STOP] condition to end the transfer.

Note:

The MSS bit functions as a direct reset. To detect a STOP condition, check the BB bit of the IBSRregister.

If 1 is written to this bit while the bus is idle (MSS = 0, BB = 0), a START condition is generated andthe value of IDAR is sent.

If 1 is written to this bit while the bus is busy (BB = 1, TRX = 0, MSS = 0), the I2C interface starts

transmission when the bus becomes idle. If the I2C interface is specified as the address for a slavethat is accompanied by a write access during this time, the bus becomes idle after the transfer ends.If the interface is transmitting as a slave (IBCR AAS = 1, TRX = 1) during this time, no data is sent

even if the bus has become idle. It is important to check whether the I2C interface is specified as aslave (IBSR AAS = 1), and whether data transmission has ended normally (IBCR MSS = 1) at thenext interrupt or otherwise data transmission has failed with an error (IBSR AL = 1).

When using in the following condition, transmission of general call address is prohibited sincereception as a slave cannot be performed.

ln addition to this LSl, if another LSI that becomes master mode exists on the bus, this LSI sendsgeneral call address as a master, and arbitration lost occurs at the second byte or later.

0 Bus error interrupt disabled

1 Bus error interrupt enabled

0 Has no meaning.

1 Generates a repeated START condition in master transfer.

0 Selects slave mode.

1Selects master mode. Generates a START condition to enable the value of the IDAR register to be sent as a slave address.

293


[bit11] ACK (ACKnowledge)

This bit generates an acknowledge according to the setting of the data receive enable bit.

This bit is disabled when a slave address is received in slave mode. When the I2C interfacedetects a 7-bit or 10-bit slave address specification, an acknowledge is returned if thecorresponding enable bits (ENTB ITMK, ENSB ISMK) are set.

Write to this bit while an interrupt flag is set (INT = 1), the bus is idle (IBSR BB = 0), or the I2Cinterface is stopped (ICCR EN = 0).

[bit10] GCAA (General Call Address Acknowledge)

This bit is an acknowledge enable bit used when a general call address is received.

Write to this bit while an interrupt flag is set (INT = 1), the bus is idle (IBSR BB = 0), or the I2Cinterface is stopped (ICCR EN = 0).

[bit9] INTE (INTerrupt Enable)

This bit is the interrupt enable bit.

[bit8] INT (INTerrupt)

This bit is the transfer end interrupt request flag bit. For a read by a read modify instruction, 1is read.

During writing

During reading

0 Acknowledge not generated when data is received

1 Acknowledge generated when data is received

0 Acknowledge not generated when general call address is received

1 Acknowledge generated when general call address is received

0 Interrupts disabled

1 Interrupts enabled

0 Clears the transfer end interrupt request flag.

1 Has no meaning.

0 Transfer not ended, not the transfer target, or bus is idle.

1

This bit is set to 1 if a one-byte transfer that includes the acknowledge bit is completed and the following conditions are met:• Bus master• The interface was specified as a slave address.• A general call address was received.• Arbitration lost occurred.If the interface is specified as a slave address, this bit is set at the end of slave address reception that includes an acknowledge.

294


Note:

If this bit is set to 1, the SCL line is maintained at the L level. Write 0 to this bit to clear it and to openthe SCL line to transfer the next byte. In master mode, a repeated START or STOP condition isgenerated.

This bit is cleared when the SCC bit is set to 1 or the MSS bit is cleared.

• Contention of SCC, MSS, and INT bits

If data is simultaneously written to the SCC, MSS, and INT bits, contention occurs between thenext-byte transfer, repeated START condition generation, and STOP condition generation. If thissituation occurs, the priorities are as follows:

1. Next-byte transfer and STOP condition generation

When the INT bit is set to 0 and the MSS bit is set to 0, writing of the MSS bit has precedenceand a STOP condition is generated.

2. Next-byte transfer and START condition generation

When 0 is written to the INT bit and 1 is written to the SCC bit, writing to the SCC bit hasprecedence, a repeated START condition is generated, and the value of IDAR is sent.

3. Repeated START condition generation and STOP condition generation

When the SCC bit is set to 1 and the MSS bit is set to 1 at the same time, clearing of the MSS

bit has precedence. A STOP condition is generated and the I2C interface enters slave mode.

When an instruction which generates a start condition is executed (set 1 to MSS bit) at timingshown in Figure 15.2-4 and Figure 15.2-5, arbitration lost detection (AL bit=1) prevents aninterrupt (INT bit=1) from being generated.

• Condition 1 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur

When an instruction which generates a start condition is executed (set 1 to MSS bit in IBCRregister) with no start condition detected (BB bit=0) and with the SDA or SCL pin at the "L" level.

Figure 15.2-4 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur

"L"

"L"

SCL pin

SCL or SDA pin at Low level

SDA pin

I2C operation enable state (EN bit=1)

Master mode setting (MSS bit=1)

Arbitration lost detection (AL bit=1)

Bus busy (BB bit)

Interrupt (INT bit)

1

0

0

295


• Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur

When an instruction which generates a start condition by enabling I2C operation (EN bit=1) is

executed (set 1 to MSS bit in IBCR register) with the I2C bus occupied by another master.

This is because, as shown in Figure 15.2-5, when the other master on the I2C bus starts

communication with I2C disabled (EN bit=0), the I2C bus enters the occupied state with no startcondition detected (BB bit =0).

Figure 15.2-5 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur

If a symptom as described above can occur, follow the procedure below for software processing.

1. Execute the instruction that generates a start condition (set the MSS bit to 1)

2. Use, for example, the timer function to wait for the time for three-bit data transmission at the

I2C transfer frequency set in the ICCR register.*

Example: Time for three-bit data transmission at an I2C transfer frequency of 100 kHz = 1/

(100x103)x30=30 µs

3. Check the AL and BB bits in the IBSR register and, if the AL and BB bits are 1 and 0,

respectively, set the EN bit in the ICCR register to 0 to initialize I2C. When the AL and BB bitsare not so, perform normal processing.

0

0

DATSLAVE ADDRESS

Stop ConditionStart Condition

INT bit interruption is not generatedin 9th clock.

SCL pin

SDA pin

EN bit

MSS bit

AL bit

BB bit

INT bit

ACKACK

296


A sample flow is given below.

*: When the arbitration lost is detected, the MSS bit is set to 1 and then the AL bit is set to 1

without fail after the time for three-bit data transmission at the I2C transfer frequency.

• Example of occurrence for an interrupt (INT bit=1) upon detection of "AL bit=1"

When an instruction which generates a start condition is executed (setting the MSS bit to 1) with"bus busy" detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detectionof "AL bit=1".

Figure 15.2-6 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs

BB bit=0 and AL bit=1NO

YES

Setting EN bit to "0" and initializing of I2CTo normal process

Master mode settingSet MSS bit in bus control register (IBCR) to "1".

When for the time for three-bit data transmission at the I2Ctransfer frequency set in the clock control register (ICCR)*

DATSLAVE ADDRESS

Start Condition Interrupt at 9th clock

SCL pin

EN bit

MSS bit

AL bit clear by software

INT bit clear by softwareand open SCL

AL bit

BB bit

INT bit

SDA pin ACK

297


15.2.3 Clock Control Register (ICCR)

This section describes the configuration and functions of the clock control register (ICCR).

Clock Control Register (ICCR)

Figure 15.2-7 shows the bit configuration of the clock control register (ICCR).

Figure 15.2-7 Bit Configuration of the Clock Control Register (ICCR)

[bit15] Test bit

This bit is used for testing.

Be sure to write 0 to it.

[bit14] NSF (NoiSe Filter enable)

Input noise filter enable bit.

Set to "1" when used at speed of 100Kbps or more.

[bit13] EN (ENable)

This bit is the enable bit for the I2C interface.

If this bit is set to 0, all bits of the IBSR and IBCR registers (except the BER and BEIE bits) arecleared. This bit is cleared when a bus error occurs (IBCR BER = 1).

Note:

If this bit is set to 0 (disabled), the I2C interface immediately stops sending and receiving.

15 14 13 12 11 10 9 8TEST ENNSF CS4 CS3 CS2 CS1 CS0

W R/W R/W R/W R/W R/W R/W0 0

R0 1 1 1 1 1

Address:

Initial value

ch0 0000BEH

ch1 0000CEH

ch2 0000DEH

ch3 0000EEH

0 Noise filter disabled

1 Noise filter enabled

0 Disabled

1 Enabled

298


[bit12 to bit8] CS4 to CS0(Clock Period Select 4-0)

These bits set the frequency of the serial clock.

These bits can be written only when the I2C interface is disabled (EN = 0) or the EN bit iscleared.

The frequency of the shift clock, fsck, is set as shown below.

Table 15.2-1 shows the serial clock frequency settings.

fsck= n 12+17

NSF = 0 n > 0

fsck= n 12+18

NSF = 1 n > 0

φ: Peripheral resource clock

φ: Peripheral resource clock

φ

φ

Table 15.2-1 Register Setting

n CS4 CS3 CS2 CS1 CS0

1 0 0 0 0 1

2 0 0 0 1 0

3 0 0 0 1 1

... ... ... ... ... ...

31 1 1 1 1 1

Setting CS4 to CS0=00000 is enabled.

Peripheral resource clock frequencyRCLK [MHz], condition

100 Kbps 400 Kbps

n fsck n fsck

20 MHz NSF=1 16 95.2 3 370.4

299


15.2.4 10-bit Slave Address Register (ITBA)

This section describes the configuration and functions of the 10-bit slave address register (ITBA).

10-bit Slave Address Register (ITBA)

Figure 15.2-8 shows the bit configuration of the 10-bit slave address register (ITBA).

Figure 15.2-8 Bit Configuration of the 10-bit Slave Address Register (ITBA)

Rewriting of this register should be executed during operation is stopped. (ICCR EN=0)


Set to "0" at reading.

[bit9 to bit0] 10-bit slave address bit (TA9 to TA0)

When 10-bit address is valid (ENTB="1": ITMK), the slave address is received in the slavemode, compare the received address with ITBA.

Acknowledge is transmitted to the master after address header of 10-bit write access isreceived.

Received data of the first and second bytes and the TBAL register are compared. When amatch is detected, an acknowledge signal is transmits the master device and the AAS bit isset.

I2C interface responds to the reception of address header for 10-bit read access afterrepetition START condition.

All bits of slave address is masked by setting of ITMK. Reception slave address is over writtenby the ITBA register. This register is effective only when "1" is set to ASS (IBSR register).

15 14 13 12 11 10 9 8TA9 TA8R/W R/W0 0

7 6 5 4 3 2 1 0TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0R/W R/W R/W R/W R/W R/W R/W R/W0 0 0 0 0 0

R R R R R R- - - - - -

0 0

Address:

Initial value

Initial value

ch0 0000B6H

ch1 0000C6H

ch2 0000D6H

ch3 0000E6H

ITBAH

ITBAL

300


15.2.5 10-bit Slave Address Mask Register (ITMK)

This section describes the configuration and functions of the 10-bit slave address mask register (ITMK).

10-bit Slave Address Mask Register (ITMK)

Figure 15.2-9 shows the bit configuration of the 10-bit slave address mask register (ITMK).

Figure 15.2-9 Bit Configuration of the 10-bit Slave Address Mask Register (ITMK)

[bit15] ENTB (10-bit slave address enable bit)

This bit is the 10-bit slave address enable bit.

Write to this bit while the I2C interface is stopped (ICCR EN = 0).

[bit14] RAL (Slave address length bit)

This bit indicates the slave address length.

If the 10-bit and 7-bit slave address enable bits are both enabled (ENTB =1 and ENSB = 1), thisbit can be used to determine whether the transfer length of a 10-bit or 7-bit slave addressbecomes valid.

This bit is valid when the AAS bit (IBSR) is set to 1.

This bit is cleared when the interface is disabled (ICCR EN = 0).

This bit is read-only.


These bits are reserved. The values read from these bits are always 1s.

15 14 13 12 11 10 9 8ENTB RAL TM9 TM8

RR/W R/W R/W0 0

RR1 1

RR1 1 1 1

7 6 5 4 3 2 1 0TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0R/W R/W R/W R/W R/W R/W R/W R/W1 1 1 1 1 1 1 1

Address:

Initial value

Initial value

ch0 0000B8H

ch1 0000C8H

ch2 0000D8H

ch3 0000E8H

0 10-bit slave address disabled

1 10-bit slave address enabled

0 7-bit slave address

1 10-bit slave address

301


[bit9 to bit0] 10-bit slave address mask bits

These bits mask the bits of the 10-bit slave address register (ITBA). Write to this register when

the I2C interface is disabled (ICCR EN = 0).

Setting this bit enables transmission of an acknowledge to a compound 10-bit slave address.When using this register for comparison of 10-bit slave addresses, set this bit to 1. The receivedslave address is overwritten to ITBA. When ASS = 1 (IBSR), the specified slave address can bedetermined by reading the ITBA register.

Each of TM9 to TM0 of ITMK corresponds to one bit of the ITBA address. If the value of each ofthe TM9 to 0 bits is 1, the ITBA address becomes valid; if it is 0, the ITBA address becomesinvalid.

Example: ITBA address is 0010010111B and ITMK address is 1111111100B:

The slave address is in the space from 0010010100B to 0010010111B.

0 This bit not used for comparison of slave addresses

1 This bit used for comparison of slave addresses

302


15.2.6 7-bit Slave Address Register (ISBA)

This section describes the configuration and functions of the 7-bit slave address register (ISBA).

7-bit Slave Address Register (ISBA)

Figure 15.2-10 shows the bit configuration of the 7-bit slave address register (ISBA).

Figure 15.2-10 Bit Configuration of the 7-bit Slave Address Register (ISBA)

Rewrite this register while operation is stopped (ICCR EN = 0).

[bit7] Reserved bit


The value read from this bit is 0.

[bit6 to bit0] Slave address bits A6 to A0

If a 7-bit slave address is enabled (ISMK ENSB = 1) when slave address data is received inslave mode, these bits of ISBA and the received slave address data are compared. If a slaveaddress match is detected, an acknowledge is sent to the master and the AAS bit is set.

The I2C interface returns an acknowledge in response to reception of the address header of a7-bit read access after a repeated START condition is generated.

All bits of a slave address are masked using the setting of the ISMK. The received slaveaddress data is overwritten to the ISBA register. This register is enabled only when AAS(IBSR register) is set to 1.

The I2C interface does not compare ISBA and the received slave address when a 10-bit slaveaddress is specified or a general call is received.

7 6 5 4 3 2 1 0SA6 SA5 SA4 SA3 SA2 SA1 SA0R/WR R/W R/W R/W R/W R/W R/W00 0 0 0 0 0 0

Address:

Initial value

ch0 0000BBH

ch1 0000CBH

ch2 0000DBH

ch3 0000EBH

303


15.2.7 7-bit Slave Address Mask Register (ISMK)

This section describes the configuration and functions of the 7-bit slave address mask register (ISMK).

7-bit Slave Address Mask Register (ISMK)

Figure 15.2-11 shows the bit configuration of the 7-bit slave address mask register (ISMK).

Figure 15.2-11 7-bit Slave Address Mask Register (ISMK)

Rewrite this register while operation is stopped (ICCR EN=0).

[bit15] ENSB (7-bit slave address enable bit)

This bit is the 7-bit slave address enable bit.

[bit14 to bit8] 7-bit slave address mask bits

These bits mask the bits of the 7-bit slave address register (ISBA).

Setting this bit enables transmission of an acknowledge to a compound 7-bit slave address.When using this register for comparison of a 7-bit slave address, set this bit to 1. The receivedslave address is overwritten to ISBA. When ASS = 1 (IBSR), the specified slave address can bedetermined by reading the ISBA register.

After the I2C interface is enabled, the slave address (ISBA) is rewritten by reception operation.When SMK is rewritten, SMK must be set again to provide the expected operation.

Each of the SM6-0 bits of ISMK corresponds to one bit of the ISBA address. If the value of eachof the SM6-0 bit is 1, the ISBA address becomes valid; if it is 0, the ISBA address becomesinvalid.

Example: If ISBA address is 0010111B and ISMK address is 1111100B:

The slave address is in the space from 0010100B to 0010111B.

15 14 13 12 11 10 9 8ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0


Address:

Initial value

ch0 0000BAH

ch1 0000CAH

ch2 0000DAH

ch3 0000EAH

0 7-bit slave address disabled

1 7-bit slave address enabled

0 This bit not used for comparison of slave addresses

1 This bit used for comparison of slave addresses

304


15.2.8 Data Register (IDAR)

This section describes the configuration and functions of the data register (IDAR).

Data Register (IDAR)

Figure 15.2-12 shows the bit configuration of the data register (IDAR).

Figure 15.2-12 Data Register (IDAR)

[bit7 to bit0] Data bits D7 to D0

Bits D7 to D0 are a data register used for serial transfer. Data is transferred from the MSB.

The writing side of this register has a double buffer. While the bus is busy (BB = 1), write datais loaded into the register for serial transfer. When the INT bit (IBCR) is cleared or the bus isidle (IBSR BB = 0), transfer data is loaded into the internal transfer register.

Since data is directly read from the register for serial transfer during reading, receive data inthis register is valid only while the INT bit (IBCR) is set.

7 6 5 4 3 2 1 0D7 D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W0 0 0 0 0 0 0 0

Address:

Initial value

ch0 0000BDH

ch1 0000CDH

ch2 0000DDH

ch3 0000EDH

305


15.2.9 Clock Disable Register (IDBL)

This section describes the configuration and functions of the clock disable register (IDBL).

IDBL (Clock Disable Register)

Figure 15.2-13 IDBL (Clock Disable Register)

[bit0] IDBL (Clock Disable Bit)

This bit set enable disable of the operation clock supply for I2C interface. This bit can be usedat the low-power consumption mode.

0: Supply the I2C clock

1: Stop the I2C clock. I2C line is opened.

This bit is initialized to "0" by reset.

When the bit is set to "1", the read values are undefined without the register, and write isinvalid without the bit (the register).

Note:

If the bit is set to "1", I2C operation is stop.

IFN (FIFO Data Count Register)

Figure 15.2-14 IFN (FIFO Data Count Register)

[bit12 to 8] FN4 to FN0 (FIFO data count)

The number of data stored in FIFO is shown.

If this register is 00H, it indicates the data is empty in FIFO and if it is 10H, it indicates the FIFOfull.

When under-run of over-run is occurred, 11H to 1FH is shown.

7 6 5 4 3 2 1 0

- - - - - - - DBLR R R R R R R R/W

0-------

Address:

Initial value

ch0 0000BFH

ch1 0000CFH

ch2 0000DFH

ch3 0000EFH

15 14 13 12 11 10 9 8FN4 FN3 FN2 FN1 FN0

R R R R R R R R0 0 0 0 0 0 0 0

Address:

Initial value

ch0 0000B0H

ch1 0000C0H

ch2 0000D0H

ch3 0000E0H

306


IFDR (FIFO Data Register)

Figure 15.2-15 IFDR (FIFO Data Register)

[bit7 to 0] FD7 to FD0 (FIFO data bit)

When FEN=1, access is performed for FIFO.

When FEN=0, access is invalid.

At reading, the receive data is read from receive FIFO, and the transmission data is written tothe transmission FIFO at write operation.

Be sure to access when INT=1. When INT=0, if access is performed to this register, theoperation is not guaranteed. (If access is performed when INT=0, FER flag of IFCR becomes1, so please use program debugging.)

IFCR (FIFO Control Register)

Figure 15.2-16 IFCR (FIFO Control Register)

[bit15] FEN (FIFO enable bit)

FIFO operation enable bit

FIFO is initialized at ‘0’.

If the FIFO is changed 1 to 0 during transfer, the transfer by the FIFO is suspended and theINT is set to 1 when the transfer of 1 byte is ended.

[bit14] FCL (FIFO clear bit)

Clear the FIFO. 0 is always read at reading.

7 6 5 4 3 2 1 0

FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0R/W R/W R/W R/W R/W R/W R/W R/W

XXXXXXXX

Address:

Initial value

ch0 0000B3H

ch1 0000C3H

ch2 0000D3H

ch3 0000E3H

15 14 13 12 11 10 9 8TEDIE FERFEN FCL TED FRED TFE

R/W R/W R/W R/W R/W R R0 0 0 0 0 0 0

Address:

Initial value

ch0 0000B2H

ch1 0000C2H

ch2 0000D2H

ch3 0000E2H

0 FIFO is not used.

1 FIFO is used.

0 No meaning

1 Receive FIFO is cleared.

307


[bit13] Unused bit. ‘0’ is always read.

[bit12] TEDIE (slave transfer end interrupt enable bit)

This is transfer end interrupt enable bit in slave mode.

When this bit is set to ‘1’, irrespective of the FEN value, RSC=1 or BB=1 with the slave state isdetected and the interrupt is generated. If the interrupt clearance is slower than the addressreception, the NACK is output.

[bit11] FER (FIFO error flag)

This is an error flag to notify access to the IFDR register during INT is set to 0.

This flag does not generate interrupt. Please use program debugging.

[bit10] TED (slave transfer end flag)

This flag indicates end of transfer at slave mode.

This interrupt source bit is set in slave mode when STOP condition or repetition STARTcondition is detected.

It is valid when the FIFO is not used (FEN=0).

Writing ‘0’ to this bit is cleared. Writing ‘1’ is invalid.

This bit is always read ‘1’ at read modify instruction.

[bit9] FRED (FIFO reception end flag)

This flag indicates that the FIFO reception ends.

If 1-byte transfer including acknowledge bit with 1-byte of last reception by FIFO is ended, theinterrupt source bit is set.

When the FIFO is empty, writing ‘0’ to the INT bit is cleared. Also, writing MSS or SCC to 0and 1, respectively is cleared.

0 Transfer end interrupt disabled

1 Transfer end interrupt enabled

0 FIFO error does not generate.

1 FIFO error generates.

0 Transfer does not end at slave mode.

1 Transfer ends at slave mode.

0 FIFO reception does not end.

1 FIFO reception ends.

308


[bit8] TFE (Transmission FIFO empty flag)

This indicates the FIFO is empty at the time of transmission.

The data is not in FIFO at data transmission, and if 1-byte transfer including acknowledge bitis ended, the interrupt source bit is set.

When the data is in FIFO, writing ‘0’ to the INT bit is cleared. Writing the MSS or SCC bit to 0and 1, respectively is cleared.

IFRN (FIFO Reception Count Register)

Figure 15.2-17 IFRN (FIFO Reception Count Register)

Write to this register when the FEN and INT is set to 1.

[bit7] FACK (FIFO reception acknowledge)

This flag is allowed when ACK is set to 1. Acknowledge is occurred when the data other thanFRN=1 is received.

When the data of FRN=1 is received, acknowledge is output according to this bit. Writing isperformed when INT=1.

[bit3 to bit0] FRN3 to FRN0 (Reception data count bit)

This register sets the number of received data. The register is decremented to FIFO every 1-byte reception. Writing 0000B is 16-byte reception. At reading, number of remaining receptiondata is read. When the FRN is changed from 1 to 0, the INT becomes 1. When INT=1, writeoperation is performed.

0 Data exists in FIFO at transmission.

1 Data does not exist in FIFO at transmission.

7 6 5 4 3 2 1 0

FACK FRN3 FRN2 FRN1 FRN0R/W R/W R/W R/W R/W R/W R/W R/W

00000000

Address:

Initial value

ch0 0000B1H

ch1 0000C1H

ch2 0000D1H

ch3 0000E1H

0 Acknowledge is not generated when data of FRN=1 is received.

1 Acknowledge is generated when data of FRN=1 is received.

309


15.3 I2C Interface Operation

The I2C bus consists of two bidirectional bus lines used for transfer: one serial data line

(SDA) and one serial clock line (SCL). The I2C interface has two corresponding open-drain I/O pins (SDA and SCL), enabling wired logic.

START Condition

Write 1 to the MSS bit while the bus is open (BB=0, MSS=0) to place the I2C interface in mastermode and to generate a START condition. The interface sends the value of the IDAR register asa slave address.

Write 1 to the SCC bit while the interrupt flag is set in bus master mode (IBCR MSS =1, INT = 1)to generate a repeated START condition.

Write 1 to the MSS bit while the bus is busy (IBSR BB = 1, TRX = 0, IBCR MSS = 0 or INT = 0) torelease the bus and start transmission.

If a write (reception) access is performed in slave mode, the interface starts transmission aftertransmission is completed and the bus is released. If the interface is sending data, it does notstart transmission even though the bus has been released.

The interface must be checked for the following:

• Whether the interface is specified as a slave (IBCR MSS=0, IBSR AAS=1)

• Whether data byte transmission is normal (IBCR MSS=1) or not (IBSR AL=1) when the nextinterrupt is received

Writing 1 to the MMS or SCC bit in any other state is ignored.

STOP Condition

Write 0 to the MSS bit in master mode (IBCR MSS = 1, INT = 1) to generate a STOP conditionand to place the interface in slave mode. Writing 0 to the MSS bit in any other state is ignored.

After the MSS bit is cleared, the interface attempts to generate a STOP condition. However, aSTOP condition will not be generated if the SCL line is driven to L. An interrupt is generated afterthe next byte is transferred.

Note:

After 0 is written to the MSS bit, it takes time until a STOP condition is generated. If the I2C interfaceis disabled (IDAR DBL = 1 or ICCR EN = 0) before the STOP condition is generated, the operationstops immediately and an incorrect clock is generated on the SCL line.

Disable the I2C interface (IDAR DBL = 1 or ICCR EN = 0) after checking that a STOP condition hasbeen generated (IBSR BB = 0).

310


Slave Address Detection

In slave mode, BB=1 is set after a START condition is generated. The receive data from themaster is stored in the IDAR register.

When a 7-bit slave address is enabled (ISMK ENSB=1)

After 8-bit data is received, the IDAR and ISBA register values are compared. However, the bitsmasked in the ISMK register are not compared.

At this time, the values are compared with the values of the bits masked with the ISMK register.

If the comparison result is a match, the AAS bit is set to 1 and an acknowledge is sent to themaster. The value of bit0 of the received data (bit0 of the IDAR register after reception) is theninverted and stored in the TRX bit.

When a 10-bit slave address is enabled (ITMK ENTB=1)

If the header section of a 10-bit address (11110, TA1, TA0, write) is detected, an acknowledge issent to the master and the value of bit0 of received data is inverted and stored in the TRX bit. Nointerrupt occurs at this time.

Then, the next data to be transferred and the low-order data of the ITBA register are compared.They are compared with the values of the bits masked with the ISMK register.

If the result is a match, the AAS bit is set to 1, an acknowledge is sent to the master, and aninterrupt occurs.

If the address has been specified as a slave and a repeated START condition is detected, theAAS bit is set to 1 and an interrupt occurs after the header section of a 10-bit address (11110,TA1, TA0, read) is received.

The interface has a 10-bit slave address register (ITBA) and a 7-bit slave address register (ISBA).If both registers are enabled (ISMK ENSB = 1, ITMK ENTB = 1), an acknowledge can be sent forthe 10-bit and 7-bit addresses.

The receive slave address length in slave mode (AAS = 1) is determined by the RAL bit of theITMK register. In master mode, disabling both registers (ISMK ENSB = 0, ITMK ENTB = 0) can

prevent a slave address from being generated for the I2C interface.

All slave addresses can be masked by setting the ITMK and ISMK registers.

Slave Address Mask

The slave address mask registers (ITMK and ISMK) can mask each bit of the slave addressregisters. A bit set to 1 in the mask register is address-compared while a bit set to 0 is ignored. Inslave mode (IBSR AAS = 1), a receive slave address can be read from the ITBA register (for a10-bit address) or the ISBA register (for a 7-bit address).

If the bit mask is cleared, the interface can be used as the bus monitor because it is alwaysaccessed as a slave.

Note:

This feature does not become a real bus monitor because it returns an acknowledge when a slaveaddress is received even though no other slave device is available.

311


Master Addressing

In master mode, BB = 1 and TRX = 1 are set after a START condition is generated and the IDARregister contents are output starting with the MSB. After address data is sent and anacknowledge is received from a slave device, bit0 of the send data (bit0 of the IDAR register aftertransmission) is inverted and stored in the TRX bit. This operation is also performed for arepeated START condition.

Two bytes are sent for a 10-bit slave address during write access. The first byte consists of theheader section (11110, A9, A8, 0) that indicates a 10-bit sequence, and the second byte consistsof the low-order 8 bits of the slave address (A7 to A0).

The 10-bit slave device in the read access state sends the above bytes and generates a repeatedSTART condition as well as the header section (11110, A9, A8, 1) that indicates a read access.

Table 15.3-1 shows the slave accesses and START condition.

Arbitration

Arbitration occurs if other master devices are also sending data during sending in master mode. Ifdata sent by the local device is 1 and the data on the SDA line is the L level, the local deviceassumes arbitration to have been lost and sets AL=1.

AL = 1 is set if the interface detects an unnecessary START condition in the first bit of the data orneither a START condition nor a STOP condition can be generated.

If arbitration loss is detected, MSS = 0 and TRX = 0 are set and the device enters slave receivemode and returns an acknowledge when it receives the device's own slave address.

Acknowledge

The receiving device sends an acknowledge to the sending device. The ACK bit (IBCR) canspecify whether an acknowledge is sent when data is received.

Even if an acknowledge is not returned from the master during data transmission in slave mode(read access from other master devices), the TRX bit is set to 0 and the device enters receivemode. This allows the master to generate a STOP condition when the slave releases the SCLline.

In master mode, an acknowledge from the slave can be checked by reading the LRB bit (IBSR).

Table 15.3-1 Slave Accesses and START Condition

7-bit slave address

Write START condition - A6 A5 A4 A3 A2 A1 A0 0

Read START condition - A6 A5 A4 A3 A2 A1 A0 1

10-bit slave access

Write START condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0

Read START condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0Repeated START condition - 1 1 1 1 0 A9 A8 1

312


Bus Error

A bus error is recognized and the I2C interface is stopped if:

• A violation of the basic convention on the I2C bus during data transfer (including the ACK bit)is detected.

• A stop condition in master mode is detected.

• A violation of the basic convention on the I2C bus while the bus is idle is detected.

Note:

The bus error of a 10-bit mode addressing is detected when a 10-bit address is disabled.

Communication Error that Causes No Error

If an incorrect clock is generated on the SCL line due to noise or some other reason during

transmission in master mode, the transmission bit counter of the I2C interface may run quickly,causing the slave to hang while the L level appears on the SDA line in the ACK cycle. An error(AL = 1, BER = 1) does not occur for such an incorrect clock.

If this situation occurs, perform the following error processing:

1. Determine that when MSS = 1, TRX = 1, INT = 1, and LRB = 1, there is a communicationerror.

2. Set EN to 0, and then set EN to 1 to cause SCL to generate one clock on a pseudo basis.This action causes the slave to release the bus.The period from when EN is set to 0 until EN is set to 1 must be long enough for the slave torecognize it as a clock (about as long as the H period of a transmission clock).

3. Since IBSR and IBCR are cleared when EN is set to 0, perform retransmission processingfrom the START condition. At this time, a STOP condition cannot be generated even if BSS isset to 0.Insert an interval equal to or longer than n × 7 × tCCP between the point where EN is set to 1and the point where MSS is set to 1 (START condition).

Example:

High-speed mode: 6 × 7 × 30.3 ≅ about 1.273 ms

Standard mode: 27 × 7 × 30.3 ≅ about 5.727 ms

When BER is set, it is not cleared even if EN is set to 0. Clear BER, and then retransmit it.

313


Other Items

• After arbitration lost occurs, check whether or not the local device is addressed usingsoftware.

When arbitration lost occurs, the device becomes a slave in terms of hardware. However, afterone-byte transfer is completed, both the CLK and DATA lines are pulled to L. Thus, if thedevice is not addressed, immediately open the CLK and DATA lines. If the device isaddressed, open the CLK and DATA lines after preparing for slave transmission or reception.All of these things must be processed using software.

• Since the I2C bus has only one interrupt, an interrupt source is generated when one-bytetransfer is completed or when an interrupt condition is met.Since multiple interrupt conditions must be checked using one interrupt, each of the flags mustbe checked by the interrupt routine. The following lists the interrupt conditions used when one-byte transfer is completed:

• The device is a bus master.

• The device is an addressed slave.

• A general call address is received.

• Arbitration lost occurs.

• When arbitration lost is detected, an interrupt source is generated, not immediately but afterone-byte transfer is completed. When arbitration lost is detected, the device becomes a slavein terms of hardware. However, in slave mode, a total of nine clocks must be output before aninterrupt source can be generated. Thus, since an interrupt source is not immediatelygenerated, no processing can be performed after arbitration lost occurs.

314



This section provides flowcharts for the following types of operation:• Main routine• Interrupt routine

When FIFO is not Used (FEN=0)

Figure 15.4-1 Flowchart of I2C Master Transmission/Reception Program

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315


Figure 15.4-2 Flowchart of I2C Slave Transmission/Reception Program

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316


When FIFO is Used (FEN=0)

Figure 15.4-3 Flowchart of I2C Master Transmission/Reception Program for Internal FIFO

No

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BB

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it =

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31

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317


Figure 15.4-4 Flowchart of I2C Slave Transmission/Reception Program for Internal FIFO

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318

CHAPTER 16DMA CONTROLLER (DMAC)

This chapter describes the DMA controller (DMAC), the configuration and functions of registers, and DMAC operation.

16.1 Overview of the DMA Controller (DMAC)

16.2 DMA Controller (DMAC) Registers

16.3 DMA Controller Operation


16.5 Data Bus

319

CHAPTER 16 DMA CONTROLLER (DMAC)

16.1 Overview of the DMA Controller (DMAC)

The DMA controller (DMAC) is a module that implements DMA (Direct Memory Access) transfer on FR family devices. When this module is used to control DMA transfer, various kinds of data can be transferred at high speed by bypassing the CPU, enhancing system performance.The external transfer request pins are connected to DMA transfer requests at end points 1 and 2 of the USB function inside the chip.

Hardware Configuration

The DMA controller (DMAC) consists mainly of the following blocks:

• Five independent DMA channels

• 5-channel independent access control circuit

• 32-bit address registers (reload specifiable, two registers for each channel)

• 16-bit rotation count register (reload specifiable, one register for each channel)

• 4-bit block rotation register (one for each channel)

• External transfer request input pins: DREQ0, DREQ1, and DREQ2 (for ch0, ch1, and ch2only)

• External transfer request acceptance output pins: DACK0, DACK1, and DACK2 (for ch0, ch1,and ch2 only)

• DMA end output pins: DEOP0, DEOP1, and DEOP2 (for ch0, ch1, and ch2 only)

• Fly-by transfer (memory to I/O and I/O to memory) (for ch0, ch1, and ch2 only)

• 2-cycle transfer

Main Functions

The following are the main functions related to data transfer by the DMA controller (DMAC):

• Data can be transferred independently over multiple channels (5 channels)

• Priority (ch.0>ch.1>ch.2>ch.3>ch.4)

• The priority can be rotated between ch.0 and ch.1.

• DMAC start sources

• External dedicated pin input (edge detection/level detection for ch0, ch1, and ch2 only)

• Built-in peripheral requests (shared interrupt requests, including external interrupts)

• Software request (register write)

• Transfer mode

• Demand transfer, burst transfer, step transfer, and block transfer

• Addressing mode: 32-bit full addressing (increment/decrement/fixed)

• The address increment/decrement range is from -255 to plus 255.

• Data types: Byte, halfword, and word length

• Single shot/reload selectable

320


Block Diagram

Figure 16.1-1 shows a block diagram of the DMA controller (DMAC).

Figure 16.1-1 Block Diagram of the DMA Controller (DMAC)

Statetransition

circuit

DMA control

BLK register

DTC 2-stage register DTCR

DSAD 2-stage register

DDAD 2-stage register

DDNO register

TYPE.MOD,WS

DSS[3:0]

ERIR,EDIR

SADM,SASZ[7:0]

DADM,DASZ[7:0]

SADR

DADR

DDNO

Read

Write

Access

address

Selector

Sel

ecto

rS

elec

tor

Sel

ecto

r

Counter

X-b

us

To interrupt controller IRQ[4:0]Priority circuit

Peripheral activation request/stop input

Write back

Write back

Buffer

Selector

Counter

Buffer

MCLREQ

Read/writecontrol

To bus controller

DMA transfer request to the bus controller

DMA activation source

selection circuit & request

acceptance control External pin activation request/stop input

Peripheral interrupt clear

Bus

con

trol

uni

t

Bus

con

trol

uni

t

Add

ress

cou

nter

Cou

nter

buf

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Cou

nter

buf

fer

Writ

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ck

321


16.2 DMA Controller (DMAC) Registers

This section describes the configuration and functions of the registers used by the DMA controller (DMAC).

DMA Controller (DMAC) Registers

Figure 16.2-1 shows the registers used by the DMA controller (DMAC).

Figure 16.2-1 DMA Controller (DMAC) Registers

24 31 23 16 15 08 07 00

ch.0 control/status register A

ch.0 control/status register B

DMACA0 00000200H



DMACB0 00000204H

DMACA1 00000208H







DMAC all-channel control register

DMACB1 0000020CH

DMACA2 00000210H

DMACB2 00000214H

DMACA3 00000218H

DMACB3 0000021CH

DMACA4 00000220H

DMACB4 00000224H

DMACR 00000240H

ch.0 transfer source address register

ch.0

DMASA0 00001000H

transfer destination address register DMADA0 00001004H


ch.1 transfer destination address register

DMASA1 00001008H

DMADA1 0000100CH


ch.2

DMASA2 00001010H

transfer destination address register DMADA2 00001014H


ch.3

DMASA3 00001018H

transfer destination address register DMADA3 0000101CH


ch.4 transfer destination address register

DMASA4 00001020H

DMADA4 00001024H

(bit)

322


Notes on Setting Registers

When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If theyare set while DMA is in progress (during transfer), correct operation cannot be guaranteed.

An asterisk ("*") following a bit when its function is described later indicates that the operation ofthe bit is affected if it is set during DMAC transfer. Rewrite this bit while DMAC transfer is stopped(start is disabled or temporarily stopped).

The setting of this bit that is made while DMA transfer start is disabled (when the DMAE bit ofDMACR is 0 or the DENB bit of DMACA is 0) becomes effective when DMA transfer start isenabled.

The setting of this bit that is made while DMA transfer is temporarily stopped (when the DMAH3to DMAH0 bits of DMACR are not 0000 or the PAUS bit of DMACA is 1) becomes effective whentemporary stop of DMA transfer is canceled.

323


16.2.1 Control/Status Registers A (DMACA0 to DMACA4)

Control/status registers A (DMACA0 to DMACA4) control the operation of the DMACA channels. There is a separate register for each channel.

Control/Status Registers A (DMACA0 to DMACA4)

Figure 16.2-2 shows the bit configuration of control/status registers A (DMACA0 to DMACA4).

Figure 16.2-2 Bit Configuration of Control/Status Registers A (DMACA0 to DMACA4)

[bit31] DENB (Dma ENaBle): DMA operation enable bit

This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer.

The activated channel starts DMA transfer when a transfer request is generated andaccepted.

All transfer requests that are generated for a deactivated channel are disabled.

When the transfer on an activated channel reaches the specified count, this bit is set to 0 andtransfer stops.

The transfer can be forced to stop by writing 0 to this bit. Be sure to stop a transfer forcibly (0write) only after temporarily stopping DMA using the PUAS bit [bit30 of DMACA]. If the transferis forced to stop without first temporarily stopping DMA, DMA stops but the transferred datacannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [bit18 to bit16of DMACB].

• If a stop request is accepted during reset: Initialized to 0.


If the operation of all channels is disabled by bit15 (DMAE bit) of the DMAC all-channel controlregister (DMACR), writing 1 to this bit is disabled and the stopped state is maintained. If theoperation is disabled by the above bit while it is enabled by this bit, 0 is written to this bit and thetransfer is stopped (forced stop).

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DENB BLK[3:0]DDNO[3:0]IS[4:0]STRGPAUS

DTC[15:0]

(Initial value: 00000000_0000XXXX_XXXXXXXX_XXXXXXXX bit)

DENB Function

0 Disables operation of DMA on the corresponding channel (initial value).

1 Enables operation of DMA on the corresponding channel.

324


[bit30] PAUS (PAUSe)*: Temporary stop instruction

This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMAtransfer is not performed before this bit is cleared (While DMA is stopped, the DSS bits are1xx).

If this bit is set before starting, DMA transfer continues to be temporarily stopped.

New transfer requests that occur while this bit is set are accepted, but no transfer starts beforethis bit is cleared (See "16.3.9 Operation from Starting to End/Stopping").

• When reset: Initialized to 0.


[bit29] STRG (Software TRiGger): Transfer request

This bit generates a DMA transfer request for the corresponding channel. If 1 is written to thisbit, a transfer request is generated when write operation to the register is completed andtransfer on the corresponding channel is started.

However, if the corresponding channel is not activated, operations on this bit are disabled.

If starting by a write operation to the DMAE bit and a transfer request occurring due to this bitare simultaneous, the transfer request is enabled and transfer is started. If writing of 1 to thePAUS bit and a transfer request occurring due to this bit are simultaneous, the transferrequest is enabled, but DMA transfer is not started before 0 is written to the PAUS bit.


• The read value is always 0.

• Only a read value of 1 is valid. If 0 is read, operation is not affected.

PAUS Function

0 Enables operation of the corresponding channel DMA (initial value)

1 Temporarily stops DMA on the corresponding channel.

STRG Function

0 Disabled

1 DMA starting request

325


[bit28 to bit24] IS4 to 0 (Input Select)*: Transfer source selection

These bits select the source of a transfer request as shown in Table 16.2-1. Note that thesoftware transfer request by the STRG bit function is always valid regardless of the settings ofthese bits.



Table 16.2-1 Settings for Transfer Request Sources

IS Function

00000 Hardware

00001

01101

01110 External pin (DREQ) H level or edge

01111 External pin (DREQ) L level or edge

10000 UART0 (receiving complete)



10011 UART0 (sending complete)



10110 Setting disabled


11000 Reload timer 0








Setting disabled

Setting disabled

326


Notes:

• If DMA start resulting from an interrupt from a function is set (IS=1xxxx), disable interrupts fromthe selected peripheral function with the ICR register.

• If demand transfer mode is selected, only IS[4:0]=01110, 01111 can be set. Starting by othersources is disabled.

• External request input is valid only for CH0, CH1, and CH2. External request input cannot beselected for CH3 and CH4. Whether level detection or edge detection is used is determined bythe mode setting. Level detection is selected for demand transfer. (For all other cases, edgedetection is selected.)

[bit23 to bit20] DDNO3 to DDNO0 (direct access number)*:Fly-by function for built-in peripherals

These bits specify the built-in peripheral of the transfer destination/source used by thecorresponding channel.

Table 16.2-2 shows the settings of the direct access number.



Table 16.2-2 Settings of the Direct Access Number

DDN0 Function


0001 No use

0010 No use

0011 No use

0100 No use

0101 No use

0110 No use

0111 No use

1000 No use

1001 No use

1010 No use

1011 No use

1100 No use

1101 No use

1110 No use


327


Note:

This function is not supported by the MB91319. Any data written is ignored.

[bit19 to bit16] BLK3-0 (BLocK size): Block size specification

These bits specify the block size for block transfer on the corresponding channel. The valuespecified by these bits becomes the number of words in one transfer unit (more exactly, therepetition count of the data width setting). If block transfer will not be performed, set 01H (size1). This register value is ignored during demand transfer. The size becomes 1.

Table 16.2-3 shows the specification of the block size.

• When reset: Not initialized.


• If 0 is specified for all bits, the block size becomes 16 words.

• During reading, the block size is always read (reload value).

[bit15 to bit00] DTC (Dma Terminal Count register)*: Transfer count register

These bits compose a register for storing the transfer count. Each register has 16-bit length.

All registers have a dedicated reload register. When the register is used for a channel that isenabled to reload the transfer count register, the initial value is automatically written back tothe register when the transfer is completed.

Table 16.2-4 shows the function of the transfer count register.

When DMA transfer is started, data in this register is stored in the counter buffer of the DMA-dedicated transfer counter and is decremented by 1 (subtraction) after each transfer unit. WhenDMA transfer is completed, the contents of the counter buffer are written back to this register andthen DMA ends. Thus, the transfer count value during DMA operation cannot be read.


• These bits are readable and writable. Always access DTC using halfword length or wordlength.

• During reading, the count value is read. The reload value cannot be read.


Table 16.2-3 Specification of the Block Size

BLK Function

XXXX Block size of the corresponding channel

Table 16.2-4 Function of the Transfer Count Register

DTC Function

XXXX Transfer count for the corresponding channel

328


16.2.2 Control/Status Registers B (DMACB0 to DMACB4)

Control/status registers B (DMACB0 to 4) control the operation of each DMACB channel and exist independently for each channel.

Control/Status Register B (DMACB0 to DMACB4)

Figure 16.2-3 shows the bit configuration of control/status registers B (B0 to B4).

Figure 16.2-3 Bit Configuration of Control/Status Registers B (DMACB0 to DMACB4)

[bit31 to bit30] TYPE (TYPE)*: Transfer type setting

These bits specify the operation type of the corresponding channel as described below.

• 2-cycle transfer mode:In this mode, the transfer source address (DMASA) and transferdestination address (DMADA) are set and transfer is performed byrepeating the read operation and write operation for the number oftimes specified by the transfer count. All areas can be specified as atransfer source or transfer destination (32-bit ADDRESS).

• Fly-by transfer mode: In this mode, external ↔ external transfer is performed in one cycle bysetting a memory address as the transfer destination address(DMADA). Be sure to specify an external area for the memory address.

Table 16.2-5 shows the settings of the transfer type.



bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TYPE[1:0] DADM ERIE EDIE DSS[2:0]DADRSADRDTCRSADMWS[1:0]MOD[1:0]

SASZ[7:0] DASZ[7:0]

(Initial value: 00000000_00000000_XXXXXXXX_XXXXXXXX bit)

Table 16.2-5 Settings for the Transfer Types

TYPE Function

00 2-cycle transfer (initial value)

01 Fly-by: Memory → I/O transfer

10 Fly-by: I/O → memory transfer

11 Setting disabled

329


[bit29 to bit28] MOD (MODe)*: Transfer mode setting

These bits specify the operation mode of the corresponding channel as shown in Table 16.2-6.



[bit27 to bit26] WS (Word Size)*: Transfer data width selection

These bits are used to select the transfer data width of the corresponding channel. Transferoperations are repeated in units of the data width specified in this register for as many timesas the specified count.

Table 16.2-7 shows the specification of the transfer data width.

• Setting disabled


Table 16.2-6 Settings for Transfer Modes

MOD Function

00 Block/step transfer mode (initial value)

01 Burst transfer mode

10 Demand transfer mode

11 Setting disabled

Table 16.2-7 Selection of the Transfer Data Width

WS Function

00 Byte-width transfer (initial value)

01 Halfword-width transfer

10 Word-width transfer

11 Setting disabled

330


[bit25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode specification

This bit specifies the address processing of the transfer source address of the correspondingchannel for each transfer operation.

An address increment is added or an address decrement is subtracted after each transferoperation according to the specified transfer source address count width (SASZ). When thetransfer is completed, the next access address is written to the corresponding address register(DMASA).

As a result, the transfer source address register is not updated until DMA transfer iscompleted.

To make the address always the same, specify 0 or 1 for this bit and set the address countwidth (SASZ and DASZ) to 0.

Table 16.2-8 shows the specification of the transfer source address count mode.



[bit24] DADM (Destination-ADdr. Count-Mode select)*:Transfer destination address count mode specification

This bit specifies the address processing for the transfer destination address of thecorresponding channel in each transfer operation.

An address increment is added or an address decrement is subtracted after each transferoperation according to the specified transfer destination address count width (DASZ). Whenthe transfer is completed, the next access address is written to the corresponding addressregister (DMADA).

As a result, the transfer destination address register is not updated until the DMA transfer iscompleted.

To make the address always the same, specify 0 or 1 for this bit and set the address countwidth (SASZ and DASZ) to 0.

Table 16.2-9 shows the specification of the transfer destination address count mode.



Table 16.2-8 Specification of the Transfer Source Address Count Mode

SADM Function

0 Increments the transfer source address. (initial value)

1 Decrements the transfer source address.

Table 16.2-9 Specification of the Transfer Destination Address Count Mode

DADM Function

0 Increments the transfer destination address. (initial value)

1 Decrements the transfer destination address.

331


[bit23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification

This bit controls reloading of the transfer count register for the corresponding channel.

If reloading of the counter is enabled by this bit, the count register value is restored to its initialvalue after transfer is completed, then DMAC stops and starts waiting for a new transferrequest (an activation request by STRG or IS setting). If this bit is 1, the DENB bit is notcleared.

DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forciblystopped.

If reloading of the counter is disabled, a single shot operation occurs. In single shot operation,operation stops after the transfer is completed even if reload is specified in the addressregister. The DENB bit is also cleared in this case.

Table 16.2-10 shows the specification of transfer counter register reloading.



[bit22] SADR (Source-ADdr.-reg. Reload)*: Transfer source address register reload specification

This bit controls reloading of the transfer source address register for the correspondingchannel.

If this bit enables the reload operation, the transfer source address register value is restored toits initial value after the transfer is completed.

If reloading of the counter is disabled, a single shot operation occurs. In single shot operation,operation stops after the transfer is completed even if reload is specified in the addressregister. The address register value also stops in this case while the initial value is beingreloaded.

If this bit disables the reload operation, the address register value when the transfer iscompleted is the address to be accessed next to the final address. When address increment isspecified, the next address is an incremented address.

Table 16.2-11 shows the specification of transfer source address register reloading.



Table 16.2-10 Specification of Transfer Counter Register Reloading

DTCR Function

0 Disables transfer count register reloading (initial value)

1 Enables transfer count register reloading.

Table 16.2-11 Specification of Transfer Source Address Register Reloading

SADR Function

0 Disables transfer source address register reloading. (initial value)

1 Enables transfer source address register reloading.

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[bit21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification

This bit controls reloading of the transfer source address register for the correspondingchannel.

If this bit enables reloading, the transfer source address register value is restored to its initialvalue after the transfer is completed.

The details of other functions are the same as those described for bit22 (SADR).

Table 16.2-11 shows the specification of transfer destination address register reloading.



[bit20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable

This bit controls the occurrence of an interrupt for termination after an error occurs. The natureof the error that occurred is indicated by DSS2 to 0. Note that an interrupt occurs only forspecific termination causes and not for all termination causes. Refer to bits DSS2-0, which arebit18 to bit16.

Table 16.2-13 shows the specification of the error interrupt request output permission.



[bit19] EDIE (EnD Interrupt Enable)*: End interrupt output enable

This bit controls the occurrence of an interrupt for normal termination.

Table 16.2-14 shows the specification of the end interrupt request output permission.



Table 16.2-12 Specification of Transfer Destination Address Register Reloading

DADR Function

0 Disables transfer destination address register reloading. (initial value)

1 Enables transfer destination address register reloading.

Table 16.2-13 Specification of the Error Interrupt Request Output Permission

ERIE Function

0 Disables error interrupt request output. (initial value)

1 Enables error interrupt request output.

Table 16.2-14 Specification of the End Interrupt Request Output Permission

EDIE Function

0 Disables end interrupt request output. (initial value)

1 Enables end interrupt request output.

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[bit18 to bit16] DSS2 to DSS0 (DMA Stop Status)*: Transfer stop source indication

These bits indicate a code (end code) of 3 bits that indicates the source of stopping ortermination of DMA transfer on the corresponding channel. For a list of end codes, see Table16.2-15.

The code indicating a transfer stop request is set only if the request is received from a peripheralcircuit and the external pin DSTP function is used.

The Interrupt column indicates the type of interrupts that can occur.


• These bits can be cleared by writing 000 to them.

• These bits are readable and writable. Note, however, that the only valid written value is 000.

[bit15 to bit8] SASZ (Source Addr count SiZe)*: Transfer source address count size specification

These bits specify the increment or decrement width for the transfer source address (DMASA)of the corresponding channel for each transfer operation. The value set by these bits becomesthe address increment/decrement width for each transfer unit. The address increment/decrement width conforms to the instruction in the transfer source address count mode(SADM).

Table 16.2-16 shows the specification of the transfer source address count size.

• When reset: Not initialized


Table 16.2-15 End Codes

DSS Function Interrupt

000 Initial value None

x01 Address error (underflow/overflow) Error

x10 Transfer stop request Error

x11 Normal end End

1xxDMA stopped temporarily (due, for example, to DMAH, PAUS bit, and an interrupt)

None

Table 16.2-16 Specification of the Transfer Source Address Count Size

SASZ Function

XXXX Specify the increment/decrement width of the transfer source address. 0 to 255

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[bit7 to bit0] DASZ (Des Addr count size)*:Transfer destination address count size specification

These bits specify the increment or decrement width for the transfer destination address(DMADA) of the corresponding channel for each transfer operation. The value set by thesebits becomes the address increment/decrement width for each transfer unit. The addressincrement/decrement width conforms to the instruction in the transfer destination addresscount mode (DADM).

Table 16.2-17 shows the specification of the transfer destination address count size.

• When reset: Not initialized


Table 16.2-17 Specification of the Transfer Destination Address Count Size

DASZ Function

XXXX Specify the increment/decrement width of the transfer destination address. 0 to 255

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16.2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to 4/DMADA0 to 4)

The transfer source/transfer destination address setting registers (DMASA0 to 4/DMADA0 to 4) control the operation of the DMAC channels. There is a separate register for each channel.

Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to 4/DMADA0 to 4)

Figure 16.2-4 shows the bit configuration of the transfer source/transfer destination addresssetting registers (DMASA0 to 4/DMADA0 to 4).

Figure 16.2-4 Bit Configuration of the Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to 4/DMADA0 to 4)

The transfer source/transfer destination address setting registers (DMASA0 to 4/DMADA0 to 4)are a group of registers that store the transfer source/transfer destination addresses. Eachregister is 32 bits.

[bit31 to bit0] DMASA (DMA Source Addr)*: Transfer source address setting

These bits set the transfer source address.

bit

bit

bit

bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16DMASA[31:16]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DMASA[15:0]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16DMADA[31:16]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DMADA[15:0]

(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXXbit)

(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXXbit)

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[bit31 to bit0] DMADA (DMA Destination Addr)*: Transfer destination address setting

If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated address counter and then the address is calculated according to the settings for thetransfer operation. When the DMA transfer is completed, the contents of the counter buffer arewritten back to this register and then DMA ends. Thus, the address counter value during DMAoperation cannot be read.

All registers have a dedicated reload register. When the register is used for a channel that isenabled for reloading of the transfer source/transfer destination address register, the initialvalue is automatically written back to the register when the transfer is completed. Otheraddress registers are not affected.


• These bits are readable and writable. For this register, be sure to access these bits as 32-bitdata.

• If these bits are read during transfer, the address before the transfer is read. If they are readafter transfer, the next access address is read. Because the reload value cannot be read, it isnot possible to read the transfer address in real time.

Note:

Do not set any of the DMAC’s registers using this register. DMA transfer is not possible for theDMAC’s registers themselves.

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16.2.4 All-Channel Control Register (DMACR)

The all-channel control register (DMACR) controls the operation of the all five DMAC channels. Be sure to access this register using byte length.

All-Channel Control Register (DMACR)

Figure 16.2-5 shows the bit configuration of the DMAC all-channel control register (DMACR).

Figure 16.2-5 Bit Configuration of the All-Channel Control Register (DMACR)

[bit31] DMAE (DMA Enable): DMA operation enable

This bit controls the operation of all DMA channels.

If DMA operation is disabled with this bit, transfer operations on all channels are disabledregardless of the start/stop settings for each channel and the operating status. Any channelcarrying out transfer cancels the requests and stops transfer at a block boundary. All startoperations on each channel in a disabled state are disabled.

If this bit enables DMA operation, start/stop operations are enabled for all channels. Simplyenabling DMA operation with this bit does not activate each channel.

DMA operation can be forced to stop by writing 0 to this bit. However, be sure to forcestopping (0 write) only after temporarily stopping DMA using the DMAH[3:0] bits [bit27 to bit24of DMACR]. If forced stopping is carried out without first temporarily stopping DMA, DMAstops, but the transfer data cannot be guaranteed. Check whether DMA is stopped using theDSS[2:0] bits [bit18 to bit16 of DMACB].

Table 16.2-18 shows the specification of the DMA operation permission.



bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16DMAE - - PM01 DMAH[3:0] - - - - - - - -

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0- - - - - - - - - - - - - - - -

(Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXX_bit)

Table 16.2-18 Specification of the DMA Operation Permission

DMAE Function

0 Disables DMA transfer on all channels. (initial value)

1 Enables DMA transfer on all channels.

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[bit28] PM01 (Priority mode ch0, ch1 robin): Channel priority rotation

This bit is set to alternate priority for each transfer between Channel0 and Channel1.

Table 16.2-19 shows the specification of the channel priority rotation.



[bit27 to bit24] DMAH (DMA Halt): DMA temporary stop

These bits control temporary stopping of all DMA channels. If these bits are set, DMA transferis not performed on any channel before these bits are cleared.

When DMA transfer is activated after these bits are set, all channels remain temporarilystopped.

Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) whilethese bits are set are all enabled. The transfer can be started by clearing all these bits.

Table 16.2-20 shows the specification of the DMA temporary stop function.



[bit30, bit29, bit23 to bit0] (Reserved): Reserved bits


• A read value is undefined.

Table 16.2-19 Specification of the Channel Priority Rotation

PM01 Function

0 Fixes the priority. (ch0 > ch1)(initial value)

1 Alternates priority. (ch1 > ch0)

Table 16.2-20 Specification of the DMA Temporary Stop Function

DMAH Function

0000 Enables the DMA operation on all channels. (initial value)

Other than 0000 Temporarily stops DMA operation on all channels.

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16.2.5 Other Functions

The MB91319 has the DACK, DEOP, and DREQ pins, which can be used for external transfer. These pins can also be used as general-purpose ports.

Pin Function of the DACK, and DEOP, and DREQ Pins

To use the DACK, DEOP, and DREQ pins for external transfer, their operation mode must beswitched from the port function to the DMA pin function.

To make the switch, set the PFR register.

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16.3 DMA Controller Operation

A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-functional DMAC that controls data transfer at high speed without the use of CPU instructions.

Principal Operations

• Functions can be set for each transfer channel independently.

• Once starting has been enabled, a channel starts transfer operation only after a specifiedtransfer request has been detected.

• After a transfer request is detected, a DMA transfer request is output to the bus controller andthe bus right is acquired by the bus controller before the transfer is started.

• The transfer is carried out as a sequence conforming to the mode settings madeindependently for the channel being used.

Transfer Mode

Each DMA channel performs transfer according to the transfer mode set by the MOD[1:0] bits ofits DMACB register.

Block/step transfer

Only a single block transfer unit is transferred in response to one transfer request. DMA thenstops requesting the bus controller for transfer until the next transfer request is received.

The block transfer unit is the specified block size (BLK[3:0] of DMACA).

Burst transfer

Transfer in response to one transfer request is carried out continuously for the number of times inthe specified transfer count.

The specified transfer count is the transfer count (BLK[3:0] of DMACA × DTC[15:0] of DMACA) ×block size.

Demand transfer

Transfer is carried out continuously until the transfer request input (detected with a level at theDREQ pin) from an external device ends or a specified transfer count is reached.

The specified transfer count in a demand transfer is the specified transfer count (DTC[15:0] ofDMACA). The block size is always 1 and the register value is ignored.

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Transfer Type

2-cycle transfer (normal transfer)

The DMA controller operates using as its unit of operation a read operation and a write operation.

Data is read from an address in the transfer source register and then written to another addressin the transfer destination register.

Fly-by transfer (memory → I/O)

The DMA controller operates using as its unit of operation a read operation.

If DMA transfer is performed when fly-by transfer is set, DMA issues a fly-by transfer (read)request to the bus controller and the bus controller lets the external interface carry out the fly-bytransfer (read).

Fly-by transfer (I/O → memory)

The DMA controller operates using as its unit of operation a write operation.

Otherwise, operation is the same as fly-by transfer (memory → I/O) operation.

Access areas used for MB91319 fly-by transfer must be external areas.

Transfer Address

The following types of addressing are available and can be set independently for each channeltransfer source and transfer destination.

The method for specifying the address setting register (DMASA/DMADA) for a 2-cycle transferand the method for a fly-by transfer are different.

Specifying the address for a 2-cycle transfer

The value read from a register (DMASA/DMADA) in which an address has been set in advance isused as the address for access. After receiving a transfer request, DMA stores the address fromthe register in the temporary storage buffer and then starts transfer.

After each transfer (access) operation, the next access address is generated (increment/decrement/fixed selectable) by the address counter and then written to the temporary storagebuffer. Because the contents of the temporary storage buffer are written back to the register(DMASA/DMADA) after each block transfer unit is completed, the address register (DMASA/DMADA) value is updated after each block transfer unit is completed, making it impossible todetermine the address in real time during transfer.

Specifying the address for a fly-by transfer

In a fly-by transfer, the value read from the transfer destination address register (DMADA) is usedas the address for access. The transfer source address register (DMASA) is ignored. Be sure tospecify an external area as the address to be set.

After receiving a transfer request, DMA stores the address from the register in the temporarystorage buffer and then starts transfer.

After each transfer (access) operation, the next access address is generated (increment/decrement/fixed selectable) by the address counter and then written to the temporary storagebuffer. Because the contents of this temporary storage buffer are written back to the register(DMADA) after each block transfer unit is completed, the address register (DMADA) value isupdated after each block transfer unit is completed, making it impossible to determine theaddress in real time during transfer.

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Transfer Count and Transfer End

Transfer count

The transfer count register is decremented (-1) after each block transfer unit is completed. Whenthe transfer count register becomes 0, counting for the specified transfer ends, and the transferstops with the end code displayed or is reactivated*.

Like the address register, the transfer count register is updated only after each block transfer unit.

*: If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, theregister is initialized and then waits for transfer (DTCR of DMACB)

Transfer end

Listed below are the sources for transfer end. When transfer ends, a source is indicated as theend code (DSS[2:0] of DMACB).

• End of the specified transfer count (DMACA:BLK[3:0] × DMACA:DTC[15:0]) => Normal end

• A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error

• An address error occurred => Error

• A reset occurred => Reset

The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for theend source is generated.

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16.3.1 Setting a Transfer Request

The following three types of transfer requests are provided to activate DMA transfer:• External transfer request pinBuil• t-in peripheral request• Software requestSoftware requests can always be used regardless of the settings of other requests.

External Transfer Request Pin

A transfer request is generated by input to the input pin prepared for a channel.

The MB91319 supports channels 0 to 2 (DREQ0, DREQ1, and DREQ2).

If the input is valid at this point, the following sources are selected depending on the settings forthe transfer type and the start source:

Edge detection

If the transfer type is block, step, or burst transfer, select edge detection:

• Falling edge detection: Set with the transfer source selection register. Set when the IS4 toIS0 bits of DMACA are 01110.

• Rising edge detection: Set with the transfer source selection register. Set when the IS4 toIS0 bits of DMACA are 01111.

Level detection

If the transfer type is demand transfer, select level detection:

• "H" level detection:Set with the transfer source selection register. Set when the IS4 to IS0 bitsof DMACA are 01110.

• "L" level detection:Set with the transfer source selection register. Set when the IS4 to IS0 bitsof DMACA are 01111.

Built-in Peripheral Request

A transfer request is generated by an interrupt from the built-in peripheral circuit.

For each channel, set the peripheral’s interrupt by which a transfer request is generated (whenthe IS4 to IS0 bits of DMACA are 1xxxx).

The built-in peripheral request cannot be used together with an external transfer request.

Note:

Because an interrupt request used in a transfer request seems like an interrupt request to the CPU,disable interrupts from the interrupt controller (ICR register).

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Software Request

A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA).

The software request is independent of the above two types of transfer request and can alwaysbe used.

If a software request occurs concurrently with activation (transfer enable request), a DMA transferrequest is output to the bus controller immediately and transfer is started.

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16.3.2 Transfer Sequence

The transfer type and the transfer mode that determine, for example, the operation sequence after DMA transfer has started can be set independently (Settings for TYPE[1:0] and MOD[1:0] of DMACB).

Selection of the Transfer Sequence

The following sequence can be selected with a register setting:

• Burst 2-cycle transfer

• Demand 2-cycle transfer

• Block/step 2-cycle transfer

• Burst fly-by transfer

• Demand fly-by transfer

• Block/step fly-by transfer

Burst 2-Cycle Transfer

In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performedcontinuously for one transfer source. For a 2-cycle transfer, all 32-bit areas can be specified usinga transfer source/transfer destination address.

A peripheral transfer request, software transfer request, or external pin (DREQ) edge inputdetection request can be selected as the transfer source.

Table 16.3-1 shows the specifiable transfer addresses.

[Features of a burst transfer]

• When one transfer request is received, transfer is performed continuously until the transfercount register reaches 0.

• The transfer count is the transfer count × block size (BLK[3:0] of DMACA × DTC[15:0] ofDMACA).

• Another request occurring during transfer is ignored.

• If the reload function of the transfer count register is enabled, the next request is acceptedafter transfer ends.

• If a transfer request for another channel with a higher priority is received during transfer, thechannel is switched at the boundary of the block transfer unit. Processing resumes only afterthe transfer request for the other channel is cleared.

Figure 16.3-1 shows an example of burst transfer.

Table 16.3-1 Specifiable Transfer Addresses

Transfer source addressing Direction Transfer destination addressing

All 32-bit areas specifiable => All 32-bit areas specifiable

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Figure 16.3-1 Example of Burst Transfer Started by Rising Edge Detection at an External Pin. The Number of Blocks is 1, and the Transfer Count is 4.

Burst Fly-by Transfer

A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer areacan only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory)only.


Demand Transfer 2-Cycle Transfer

A demand transfer sequence is generated only if H level or L level of an external pin is selectedas a transfer request. Select the level with IS[3:0] of DMACA.

[Features of a continuous transfer]

• The following are some features of a continuous transfer:

• Each transfer operation of a transfer request is checked. While the external input level iswithin the range of the specified transfer request levels, transfer is performed continuouslywithout the request being cleared. If the external input changes, the request is cleared and thetransfer stops at the transfer boundary. This operation is repeated for the number of timesspecified by the transfer count.

• Otherwise, operations are the same as those of a burst transfer.

Figure 16.3-2 shows an example of demand transfer, and Table 16.3-3 shows the specifiabletransfer addresses.

Figure 16.3-2 Example of Demand Transfer Started by "H" Level Detection at an External Pin. The Number of Blocks is 1, and the Transfer Count is 3.

Transfer count

Bus operation CPU SA DA SA DA SA DA SA DA CPU

4 3 12

Transfer end

0

Transfer request ( edge)

Table 16.3-2 Specifiable Transfer Addresses (for Burst Fly-by Transfer)


Specification not required (invalid) None External area

CPU SA DA SA DA SA DA

3 2 1 0

CPU

Transfer request ("H" level)

Bus operation

Transfer count

Transfer end

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• For a demand transfer, be sure to set an external area address for the transfer source ortransfer destination or both. Since DMA transfer is adjusted to the external bus timing indemand transfer mode, access to external areas is always needed.

• Since the SDRAM area is not supported as a transfer source/transfer destination duringdemand transfer, this area cannot be set.

Demand Transfer Fly-by Transfer

A demand transfer fly-by transfer has the same features as a 2-cycle transfer except that thetransfer area can only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only.


Table 16.3-3 Specifiable Transfer Addresses (for Demand Transfer 2-Cycle Transfer)

Transfer source address Direction Transfer destination address

External area => External area

External area => Built-in IO

External area => Built-in RAM

Built-in IO => External area

Built-in RAM => External area

Table 16.3-4 Specifiable Transfer Addresses (for Demand Transfer Fly-by Transfer)



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Step/Block Transfer 2-Cycle Transfer

For a step/block transfer (Transfer for each transfer request is performed as many times as thespecified block count), all 32-bit areas can be specified as the transfer source/transfer destinationaddress.


Step transfer

If 1 is set as the block size, a step transfer sequence is generated.

[Features of a step transfer]

• If a transfer request is received, the transfer request is cleared after one transfer operationand then the transfer is stopped (The DMA transfer request to the bus controller is canceled).

• Another request occurring during transfer is ignored.

• If a transfer request for another channel with a higher priority is received during transfer, thechannel is switched after the transfer is stopped and then restarted. Priority in a step transferis valid only if transfer requests occur simultaneously.

Block transfer

If any value other than 1 is specified as the block size, a block transfer sequence is generated.

[Features of a block transfer]

• The block transfer has the same features as those of a step transfer except that one transferunit consists of multiple transfer cycle counts (number of blocks).

Figure 16.3-3 shows an example of block transfer.

Figure 16.3-3 Example of Demand Transfer Started by Rising Edge Detection at an External Pin. The Number of Blocks is 2, and the Transfer Count is 2.

Table 16.3-5 Specifiable Transfer Addresses (for Step/Block Transfer 2-Cycle Transfer)


All 32-bit areas specifiable => All 32-bit areas specifiable

CPU SA DA SA DA SA DA SA DA

2 1 120

CPU

2 1Transfer count

Bus operation

Number of blocks

Transfer end

Transfer request ( edge)

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Step/Block Transfer 2-Cycle Transfer Fly-by Transfer

This transfer has the same features as those of a 2-cycle transfer except that the transfer areacan only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory)only.


Table 16.3-6 Specifiable Transfer Addresses (for Step/Block Transfer 2-Cycle Transfer Fly-by Transfer)



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16.3.3 General Aspects of DMA Transfer

This section describes the block size for DMA transfers and the reload operation.

Block Size

• The unit and increment for transfer data is a set of (the number set in the block sizespecification register × data width) data.

• Since the amount of data transferred in one transfer cycle is determined by the value specifiedas the data width, one transfer unit is consists of the number of transfer cycles for thespecified block size.

• If a transfer request with a higher priority is received during transfer or if a temporary stoprequest for a transfer occurs, the transfer stops only at the transfer unit boundary, whether ornot the transfer is a block transfer. This arrangement makes it possible to protect data forwhich division or temporary stopping is not desirable. However, if the block size is large,response time increases.

• Transfer stops immediately only when a reset occurs, in which case the data being transferredcannot be guaranteed.

Reload Operation

In this module, the following three types of reloading can be set for each channel:

Transfer count register reloading

After transfer is performed the specified number of times, the initial value is set in the transfercount register again and waiting for a start request starts.

Set this type of reloading when the entire transfer sequence is to be performed repeatedly.

If reload is not specified, the count register value remains 0 after the transfer is performed thespecified number of times and no further transfer is performed.

Transfer source address register reloading

After transfer is performed the specified number of times, the initial value is set in the transfersource address register again.

Set this type of reloading when transfer is to be repeated from a fixed area in the transfer sourceaddress area.

If reload is not specified, the transfer source address register value after the transfer is performedthe specified number of times becomes the next address. Use this type when the address area isnot fixed.

Transfer destination address register reloading

After transfer is performed the specified number of times, the initial value is set in the transferdestination address register again.

Set this type of reloading when transfer is to be repeated to a fixed area in the transfer destinationaddress area.

(The processing hereafter is the same as described in "Transfer source address registerreloading" above.)

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• If only reloading of the transfer source/transfer destination register is enabled, restart aftertransfer is performed the specified number of times is not implemented and only the values ofeach address register are set.

Special examples of operating mode and the reload operation

• If transfer is performed in continuous transfer mode by external pin input level detection andtransfer count register reloading is used, transfer continues by reloading even though transferends during continuous input. Also in this case, an end code is set.

• If it is preferable that processing stops when data transfer ends and starts after input isdetected again, do not specify reload.

• For a transfer in burst, block, or step transfer mode, transfer stops temporarily after reloadwhen data transfer ends. Transfer does not start until new transfer request input is detected.

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16.3.4 Addressing Mode

Specify the transfer destination/transfer source address independently for each transfer channel.

Address Register Specifications

The following two methods are provided to specify an address register. The method specifieddepends on the transfer sequence.

• In 2-cycle transfer mode, set the transfer source address in the transfer source addresssetting register (DMASA) and the transfer destination address in the transfer destinationaddress setting register (DMADA).

• In fly-by transfer mode, specify the memory address in the transfer destination address settingregister (DMADA). In this case, the value in the transfer source address setting register(DMASA) is ignored.

Features of the Address Register

This register has the maximum 32-bit length. With 32-bit length, all space in the memory map canbe accessed.

Function of the Address Register

• The address register is read in each access operation and the read value is sent to theaddress bus.

• At the same time, the address for the next access is calculated by the address counter andthe address register is updated using the calculated address.

• For address calculation, increment or decrement is selected independently for each channel,transfer destination, and transfer source. The address increment/decrement width is specifiedby the address count size register (SASZ/DASZ of DMACB).

• If reloading is not enabled, the address resulting from the address calculation of the lastaddress remains in the address register when the transfer ends.

• If reloading is enabled, the initial value of the address is reloaded.

Notes:

• If an overflow or underflow occurs as a result of 32-bit length full address calculation, an addresserror is detected and transfer on the relevant channel is stopped. (Refer to the description for theitems related to the end code).

• Do not set any of the DMAC’s registers as the address register.

• For demand transfer, be sure to set an address in an external area for the transfer source,transfer destination, or both.

• Do not let the DMAC transfer data to any of the DMAC’s registers.

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16.3.5 Data Types

Select the data length (data width) transferred in one transfer operation from the following:• Byte• Halfword• Word

Data Length (Data Width)

Since the word boundary specification is also observed in DMA transfer, different low-order bitsare ignored if an address with a different data length is specified for the transfer destination/transfer source address.

• Byte: The actual access address and the addressing match.

• Halfword:The actual access address has 2-byte length starting with 0 as the lowest-order bit.

• Word: The actual access address has a 4-byte length starting with 00 as the lowest-orderbits.

If the lowest-order bits in the transfer source address and transfer destination address aredifferent, the addresses as set are output on the internal address bus. However, each transfertarget on the bus is accessed after the addresses are corrected according to the above rules.

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16.3.6 Transfer Count Control

Specify the transfer count within the range of the maximum 16-bit length (1 to 65536).

Transfer Count Control

Set the transfer count value in the transfer count register (DTC of DMACA).

The register value is stored in the temporary storage buffer when the transfer starts and isdecremented by the transfer counter. When the counter value becomes 0, end of transfer end forthe specified count is detected, and the transfer on the channel is stopped or waiting for a restartrequest starts (when reload is specified).

Features of the group of transfer count registers:

• Each register has 16-bit length.

• All registers have a dedicated reload register.

• If transfer is activated when the register value is 0, transfer is performed 65536 times.

Reload operation

• The reload operation can be used only if reloading is enabled in a register that allowsreloading.

• When transfer is activated, the initial value of the count register is saved in the reload register.

• If the transfer counter counts down to 0, end of transfer is reported and the initial value is readfrom the reload register and written to the count register.

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16.3.7 CPU Control

When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller.The bus controller passes the right to use the internal bus to DMA at a break in bus operation and DMA transfer starts.

DMA Transfer and Interrupts

• During DMA transfer, interrupts are generally not accepted until the transfer ends.

• If a DMA transfer request occurs during interrupt processing, the transfer request is acceptedand interrupt processing is stopped until the transfer is completed.

• If, as an exception, an NMI request or an interrupt request with a higher level than the holdsuppress level set by the interrupt controller occurs, DMAC temporarily cancels the transferrequest via the bus controller at a transfer unit boundary (one block) to temporarily stop thetransfer until the interrupt request is cleared. In the meantime, the transfer request is retainedinternally. After the interrupt request is cleared, DMAC issues a transfer request to the buscontroller to acquire the right to use the bus and then restarts DMA transfer.

Suppressing DMA

When an interrupt source with a higher priority occurs during DMA transfer, an FR family deviceinterrupts the DMA transfer and branches to the relevant interrupt routine. This feature is valid aslong as there are any interrupt requests. When all interrupt sources are cleared, the suppressionfeature no longer works and the DMA transfer is restarted by the interrupt processing routine.Thus, if you want to suppress restart of DMA transfer after clearing interrupt sources in theinterrupt source processing routine at a level that interrupts DMA transfer, use the DMA suppressfunction. The DMA suppress function can be activated by writing any value other than 0 to theDMAH[3:0] bits of the DMA all-channel control register and can be stopped by writing 0 to thesebits.

This function is mainly used in the interrupt processing routines. Before the interrupt sources inan interrupt processing routine are cleared, the DMA suppress register is incremented by 1. If thisis done, then no DMA transfer is performed. After interrupt processing, decrement the DMAH[3:0]bits by 1 before returning. If multiple interrupts have occurred, DMA transfer continues to besuppressed since the DMAH[3:0] bits are not 0 yet. If a single interrupt has occurred, theDMAH[3:0] bits become 0. DMA requests are then enabled immediately.

Notes:

• Since the register has only four bits, this function cannot be used for multiple interrupts exceeding15 levels.

• Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher thanother interrupt levels.

356


16.3.8 Hold Arbitration

When a device is operating in external bus extended mode, an external hold function can be used. The relationship between external hold requests and DMA transfer requests by this module when the hold function can be used is described below.

DMA Transfer Request during External Hold

The device is externally held. When an external bus area is accessed by DMA transfer, DMAtransfer is temporarily stopped. When the external hold is released, DMA transfer is restarted.

External Hold Request During DMA Transfer

The device is externally held. When an external bus area is accessed by DMA transfer, DMAtransfer is temporarily stopped. When the external hold is released, DMA transfer is restarted.

Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request

The device is externally held and internal DMA transfer is started. When an external bus area isaccessed by DMA transfer, DMA transfer is temporarily stopped. When the external hold isreleased, DMA transfer is restarted.

357


16.3.9 Operation from Starting to End/Stopping

Starting of DMA transfer is controlled independently for each channel, but before transfer starts, the operation of all channels needs to be enabled. This section describes operation from starting to end/stopping.

Operation Start

Enabling operation for all channels

Before activating each DMAC channel, operation for all channels needs to be enabled in advancewith the DMA operation enable bit (DMAE of DMACR). All start settings and transfer requests thatoccurred before operation is enabled are invalid.

Starting transfer

The transfer operation can be started by the operation enable bit of the control register for eachchannel. If a transfer request to an activated channel is accepted, the DMA transfer operation isstarted in the specified mode.

Starting from a temporary stop

If a temporary stop occurs before starting with channel-by-channel or all-channel control, thetemporary stopped state is maintained even though the transfer operation is started. If transferrequests occur in the meantime, they are accepted and retained. When temporary stopping isreleased, transfer is started.

Transfer Request Acceptance and Transfer

Sampling for transfer requests set for each channel starts after starting.

If edge detection is selected for the external pin start source and a transfer request is detected,the request is retained within DMAC until the clear conditions are met (when the external pin startsource is selected for block, step, or burst transfer).

If level detection or peripheral interrupt start is selected for the external pin start source, DMACcontinues the transfer until all transfer requests are cleared. When they are cleared, DMAC stopsthe transfer after one transfer unit (demand transfer or peripheral interrupt start).

Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handlethe interrupts.

Transfer requests are always accepted while other channel requests are being accepted andtransfer performed. The channel that will be used for transfer is determined for each transfer unitafter priority has been checked.

358


Clearing Peripheral Interrupts by DMA

This DMA has a function that clears peripheral interrupts. This function works when peripheralinterrupt is selected as the DMA start source (when IS[4:0]=1xxxx).

Peripheral interrupts are cleared only for the set start sources. That is, only the peripheralfunctions set by IS[4:0] are cleared.

Timing for Clearing an Interrupt

The timing for clearing an interrupt depends on the transfer mode. (See "16.4 OperationFlowcharts").

Block/step transfer

If block transfer is selected, a clear signal is generated after one block (step) transfer.

Burst transfer

If burst transfer is selected, a clear signal is generated after transfer is performed the specifiednumber of times.

Demand transfer

Since only start requests from external pins are supported in demand transfer, no clear signalis generated.

Temporary Stopping

DMA transfer is stopped in the following cases:

Setting of temporary stopping by writing to the control register (Set independently for each channel or all channels simultaneously)

If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel isstopped until release of temporary stopping is set again. You can check the DSS bits fortemporary stopping.

Transfer is restarted when temporary stopping is canceled.

NMI/hold suppress level interrupt processing

If an NMI request or an interrupt request with a higher level than the hold suppress level occurs,all channels on which transfer is in progress are stopped at the boundary of the transfer unit andthe bus right is returned to give priority to NMI/interrupt processing. Transfer interrupts acceptedduring NMI/interrupt processing are retained, initiating a wait for completion of NMI processing.

Channels for which requests are retained restart transfer after NMI/interrupt processing iscompleted.

359


Operation End/Stopping

The end of DMA transfer is controlled independently for each channel. It is also possible todisable operation for all channels at once.

Transfer end

If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and alltransfer requests are disabled after the transfer count register becomes 0 (Clear the DENB bit ofDMACA).

If reloading is enabled, the initial value is reloaded, "Normal end" is displayed as the end code,and a wait for transfer requests starts after the transfer count register becomes 0 (Do not clearthe DENB bit of DMACA).

Disabling all channels

If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMACoperations, including operations on active channels, are stopped. Then, even if the operation ofall channels is enabled again, no transfer is performed unless a channel is restarted. In this case,no interrupt whatever occurs.

Stopping Due To an Error

In addition to normal end after transfer for the number of times specified, stopping as the result ofvarious types of errors and the forced stopping are provided.

Transfer stop requests from peripheral circuits

Depending on the peripheral circuit that outputs a transfer request, a transfer stop request isissued when an error is detected (Example: Error when data is received at or sent from acommunications system peripheral).

The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" as theend code and stops the transfer on the corresponding channel.

For details of the conditions under which a transfer stop request is generated, see thespecifications for each peripheral circuit.

00000

01111

10000

10010

10011

11111

Hardware

External pin "L" level or edgeNone

Yes

None

IS Function Transfer stop request

360


Occurrence of an address error

If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, anaddress error is detected (if an overflow or underflow occurs in the address counter when a 32-bitaddress is specified).

If an address error is detected, "An address error occurred" is displayed as the end code andtransfer on the corresponding channel is stopped.

361


16.3.10 DMAC Interrupt Control

Independent of peripheral interrupts that become transfer requests, interrupts can also be output for each DMAC channel.

DMAC Interrupt Control

• Transfer end interrupt: Occurs only when operation ends normally.

• Error interrupt: Transfer stop request due to a peripheral circuit (error due to a peripheral)

• Error interrupt: Occurrence of address error (error due to software)

All of these interrupts are output according to the meaning of the end code.

An interrupt request can be cleared by writing 000 to DSS2 to 0 (end code) of DMACS. Be sure toclear the end code by writing 000 before restarting.

If reloading is enabled, the transfer is automatically restarted. At this point, however, the end codeis not cleared and is retained until a new end code is written when the next transfer ends.

Since only one end source can be displayed in an end code, the result after considering the orderof priority is displayed when multiple sources occur simultaneously. The interrupt that occurs atthis point conforms to the displayed end code.

The following shows the priority for displaying end codes (in order of decreasing priority):

• Reset

• Clearing by writing 000

• Peripheral stop request or external pin input (DSTP) stop request

• Normal end

• Stopping when address error detected

• Channel selection and control

DMA Transfer during Sleep

• This model cannot operate the DMAC in sleep mode.

362


16.3.11 Channel Selection and Control

Up to five channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel.

Priority Among Channels

Since DMA transfer is possible only on one channel at a time, priority must be set for thechannels.

Two modes, fixed and rotation, are provided as the priority settings and can be selected for eachchannel group (described later).

Fixed mode

The order of priority is fixed by channel number, with priority decreasing from channel 0 tochannel 4:

(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)

If a transfer request with a higher priority is received during a transfer, the transfer channelbecomes the channel with the higher priority when the transfer for the transfer unit (number set inthe block size specification register × data width) ends.

When higher priority transfer is completed, transfer is restarted on the previous channel.

Figure 16.3-4 shows the timing diagram for the transfer operation in fixed mode

Figure 16.3-4 Timing Diagram for the Transfer Operation in Fixed Mode

Rotation mode (ch.0 to ch.1 only)

When operation is enabled, the initial states have the same order that they would have in fixedmode, but at the end of each transfer operation, the priority of the channels is reversed. Thus, ifmore than one transfer request is output at the same time, the channel is switched after eachtransfer unit.

This mode is effective when continuous or burst transfer is set.

Figure 16.3-5 shows the timing diagram for the transfer operation in rotation mode.

CPU SA DA SA DA SA DA SA DA CPU

ch1 ch0 ch0 ch1

ch0 transfer request


Bus operation

Transfer ch

ch0 transfer end

ch1 transfer end

363


Figure 16.3-5 Timing Diagram for the Transfer Operation in Rotation Mode

Channel Group

Table 16.3-7 shows the selection priority of channel groups.

CPU SA DA SA DA SA DA SA DA CPU

ch1 ch0 ch1 ch0



Bus operation

Transfer ch

ch0 transfer end

ch1 transfer end

Table 16.3-7 Selection Priority of Channel Groups

MODE Priority Remarks

Fixed ch0 > ch1 −

RotationThe initial state is the top row.If transfer occurs for the top row, the priority is reversed.

ch0 > ch1

ch0 < ch1

364


16.3.12 Supplement on External Pin and Internal Operation Timing

This section provides supplementary information about external pins and internal operation timing.

Minimum Effective Pulse Width of the DREQ Pin Input

Only channels 0, 1, and 2 are applicable for the MB91319.

Operation in all transfer modes (i.e., burst, step, block, and demand transfer) requires a minimumeffective pulse width of five system clock cycles (five cycles of external bus clock [CLKT]).

Note:

DACK output does not indicate acceptance of DREQ input. DREQ input is always accepted if DMAis enabled but transfer has not started. Therefore, it is not necessary to retain DREQ input untilDACK output is asserted (except in demand transfer mode).

Timing to Stop a Demand Transfer Request and Timing to Invalidate the DREQ Pin Input

For 2-cycle transfer

For a demand transfer, be sure to set an address in an external area for the transfer source, thetransfer destination, or both.

• For transfer from external to external circuits:

Use the DREQ negation sense timing so that it is placed prior to the write strobe negationtiming by a single cycle or more. There are following measures for achieving this:

- Make the DREQ negation timing by a single cycle or more with the adjustment on theexternal I/O side or external glue logic side.

- Increase the wait value from the current value by a single cycle or more by using the autowait capability in the external bus controller provided with the FR.

If DREQ is negated after the period when DACK and WR are at the L level, the next transfermay be executed.

• For transfer from external to internal circuits:

When accessing the transfer source for the last DMA transfer, negate DREQ while theexternal RD pin output is at the L level

If DREQ is negated after the period when DACK and RD are at the L level, the next transfermay be executed.

Figure 16.3-6 shows an example of the timing for negating the DREQ pin input for 2-cycletransfer from an external circuit to an internal circuit.

365


Figure 16.3-6 Example of the Timing for Negating the DREQ Pin Input for 2-Cycle Transfer from an External Circuit to an Internal Circuit

• For transfer from internal to external circuits:

Use the DREQ negation sense timing so that it is placed prior to the write strobe negationtiming by a single cycle or more. There are following measures for achieving this:

- Make the DREQ negation timing by a single cycle or more with the adjustment on theexternal I/O side or external glue logic side.

- Increase the wait value from the current value by a single cycle or more by using the autowait capability in the external bus controller provided with the FR.

If DREQ is negated after the period when DACK and WR are at the L level, the next transfermay be executed.

External bus clock

CS0

CS1

AS

RD

WRn

DREQn

DACKn

Negate the range of DERQ pin input indicated with the arrow. If you set the negation timing later than

the circular mark , an extra round of signal may be transferred.

366


For fly-by transfer

For a demand transfer, be sure to set an address in an external area for the transfer destination.

• For fly-by (timing to read pin) transfer:

After the IOWR pin output for the last DMA transfer goes to the H level, negate DREQ whilethe external RD pin output is at the L level.

If DREQ is negated after the period when DACK and RD are at the L level, the next transfermay be executed.

• For fly-by (timing to IORD pin) transfer:

After the external WR pin output for the last DMA transfer goes to the H level, negate DREQwhile IORD is at the L level.

If DREQ is negated after the period when DACK and IORD are at the L level, the next transfermay be executed.

Figure 16.3-7 shows an example of the timing for negating the DREQ pin input for fly-by (write)transfer.

Figure 16.3-7 Example of the Timing for Negating the DREQ Pin Input for Fly-by (Timing to IORD Pin) Transfer

External bus clock

CS0

CS1

AS

RD

WRn

DREQn

DACKn

IORD

Negate the range of DERQ pin input indicated with the arrow. If you set the negation timing later

than the circular mark , an extra round of signal may be transferred.

367


Timing of the DREQ Pin Input for Continuing Transfer Over the Same Channel

For burst, step, block, and demand transfers

Operation in which transfer is continued over the same channel by the DREQ pin input cannot beguaranteed. If DREQ is reasserted at the fastest timing to clear requests retained internally afterthe transfer ends, at least one system clock cycle (one CLK output cycle) is provided to detecttransfer requests for other channels. If, as a result, a transfer request for another channel with ahigher priority is detected, transfer on that channel will be started.

Even if DREQ is reasserted earlier, it is ignored because the transfer has not been completed. Ifno transfer requests for other channels occur, transfer over the same channel is restarted byreasserting DREQ when the DACK pin output is asserted.

Timing of DACK Pin Output

The DACK output of this DMAC indicates that transfer with respect to an accepted transferrequest is being performed.

The output of DACK is basically synchronized with the address output of external bus accesstiming. To use DACK output, it is necessary to enable the DACK output with a port.

Timing of the DEOP Pin Output

The DEOP of this DMA indicates that DMA transfer for the specified number of times of theaccepted channel has been completed.

DEOP is output when access to an external area of the last transfer block starts. Thus, if anyvalue other than 1 is set (block transfer mode) as the block size, DEOP is output when the lastdata of the last block is transferred. In this case, the acceptance of the next DREQ is alreadystarted even during transfer (before DEOP output) if the DACK pin output is asserted.

The DEOP output is synchronized with external bus access timing controlled with RD or WR.However, if the transfer source/transfer destination is internal access, DEOP is not output. TheDEOP output, it is necessary to enable the DEOP output using the port register.

Timing of the DSTP Pin Input

Operation in all transfer modes (i.e., burst, step, block, and demand transfer) requires a minimumeffective pulse width of five system clock cycles (1/2θ or two cycles of the CPU system clock).

As with DREQ, we recommend that you use DSTP input timing in synchronization with externalaccess (Use the DACK output and the signal decoded by RD or WR).

Use the pin input to force DMA transfer to stop. Although transfer can be forced to stop by usingthis pin input, the status register (DSS[2:0] of DMACB) indicates "Transfer stop request" and ishandled as an error. If interrupts are enabled, interrupts will occur.

Since this function is shared with the DEOP pin, both functions cannot be used. Set switching offunctions with the port register.

368


If an External Pin Transfer Request is Reentered During Transfer

For burst, step, and block transfers

While the DACK signal is asserted within the DMAC, the next transfer request, if it is entered, isdisabled. However, since operation of the external bus control unit and operation of the DMACare not completely synchronous, the circuit must be initialized to create DREQ pin input usingDACK and DEOP output to enable transfer requests by using DREQ input.

For a demand transfer

If reloading of the transfer count register is specified when transfer for as many transfers asspecified has been completed, another transfer request is accepted.

If Another Transfer Request Occurs During Block Transfer

No request is detected before the transfer of the specified blocks is completed. At the blockboundaries, transfer requests accepted at that time are evaluated and then transfer on thechannel with the highest priority is performed.

Transfer Between External I/O and External Memory

As targets of transfer by the DMAC, external I/O and external memory are not distinguished.Specify an external I/O as a fixed external address. To perform fly-by transfer, set the address ofexternal memory in the transfer destination address register. For external I/O, use the signaldecoded by the DACK output and RD or WR.

AC Characteristics of DMAC

DREQ pin input, DACK pin output, and DEOP pin output are provided as the external pins relatedto the DMAC,. Output timing is synchronized with external bus access. Refer to the AC standardfor the DMAC.

369



This section contains operation flowcharts for the following transfer modes:• Block transfer• Burst transfer• Demand transfer

Block Transfer

Figure 16.4-1 shows the flowchart for block transfer.

Figure 16.4-1 Operation Flowchart for Block Transfer

Load the initial address,transfer count, and number

of blocks

Activation requestwait

Interrupt clear

DMA transfer end DMA interrupted

BLK=0

DTC=0

DMA stop

DENB=1DENB=>0

Write back the address, transfer count, and number of blocks

Number of blocks - 1

Activation request

One-time access for fly-by

Reload enable

Only when the peripheralinterrupt activation sourceis selected

Calculate the address for transfer source address access

Calculate the address for transferdestination address access

Block transfer- Can be activated by all activation sources (selection).- Can access all areas.- The number of blocks can be set.- Interrupt clear is issued when transfer of the specified number of blocks is completed.- The DMA interrupt is issued when transfer for the number of times specified is completed.

Transfer count - 1

Interrupt cleared

370


Burst Transfer

Figure 16.4-2 shows the operation flowchart for burst transfer.

Figure 16.4-2 Operation Flowchart for Burst Transfer

Load the initial address,transfer count, andnumber of blocks



BLK=0

DTC=0

DMA stop

DENB=1DENB=>0

Write back the address,transfer count, and number

of blocks


Interrupt clear


Reload enable

Only when the peripheral interruptactivation source is selected

Calculate the address fortransfer source address access


Transfer count - 1

Interrupt cleared

Burst transfer- Can be activated by all activation sources (selection).- Can access all areas.- The number of blocks can be set.- Interrupt clear and the DMA interrupt are issued when transfer for the number of times specified is completed.

371


Demand Transfer

Figure 16.4-3 shows the operation flowchart for demand transfer.

Figure 16.4-3 Operation Flowchart for Demand Transfer

Load the initial address,transfer count, andnumber of blocks



DTC=0

DMA stop

DENB=1DENB=>0

Write back the address,transfer count, and number

of blocks

Interrupt clear

Activation request


Reload enable

Only when the peripheral interruptactivation source is selected

Calculate the address fortransfer source address access



Interrupt cleared

None

Demand transfer- Only requests from the external pin (DREQ) are accepted. Activation by

other sources is disabled.- Access to an external area is required (since access to an external area

becomes the next activation source).- The number of blocks is always 1, regardless of the settings.- Interrupt clear and the DMA interrupt are issued when transfer for the

number of times specified is completed.

372


16.5 Data Bus

This section shows the flow of data during 2-cycle transfer and fly-by transfer.

Flow of Data During 2-Cycle Transfer

Figure 16.5-1 shows examples of six types of transfer during 2-cycle transfer.

Figure 16.5-1 Examples of 2-Cycle Transfer

(Continued)

DMAC

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

RAM

CP

U

MB91xxx

Read cycle

Read cycle

Read cycle

IO

Bus controller

DMAC

RAMC

PU

MB91xxx

Data buffer

Bus controller

Data buffer

Write cycle

Write cycle

Write cycle

IO

DMAC

RAM

CP

U

MB91xxx

IO

DMAC

RAM

CP

U

MB91xxx

IO

DMAC

RAM

CP

U

MB91xxx

IO

DMAC

RAM

CP

U

MB91xxx

IO

External area => external area transfer

External area => internal RAM area transfer

External area => built-in IO area transfer

Bus controller

Data buffer

Bus controller

Data buffer

Bus controller

Data buffer

Bus controller

Data buffer

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

373


(Continued)

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

UMB91xxx

IO

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Read cycle

Read cycle

Read cycle

Write cycle

Write cycle

Write cycle

Built-in IO area => internal RAM area transfer

Internal RAM area => external area transfer

Internal RAM area => built-in IO area transferE

xter

nal b

us I/

FE

xter

nal b

us I/

FE

xter

nal b

us I/

F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Data buffer Data buffer



374


Flow of Data During Fly-By Transfer

Figure 16.5-2 shows examples of two types of transfer during fly-by transfer.

Figure 16.5-2 Examples of Fly-By Transfer

mem

ory

Fly-by transfer by SDRAM disabled

Fly-by transfer by SDRAM disabled

Memory read by RD or CSxX

IO write by RD or DACK

mem

ory Memory write by WR or CSxX

IO read by WR or DACK

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

IOIO

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Read cycle

Read cycle

Fly-by transfer (memory IO)

Fly-by transfer (IO memory)

Ext

erna

l bus

I/F

Data buffer

Data buffer

375


376

CHAPTER 17USB FUNCTION

This chapter gives an overview of the USB function, register configuration and functions, operation of the USB function, and supplementary notes on the USB function.

17.1 Overview of the USB Function

17.2 USB Interface Registers

17.3 Operation of the USB Function

17.4 Supplementary Notes on the USB Function

377

CHAPTER 17 USB FUNCTION

17.1 Overview of the USB Function

The USB function consists of a protocol engine, physical end points (FIFO buffers) required for data transfer, CPU DMA interface, and other components. The USB function carries out the protocol processing to be done by a USB function device.

Overview of the USB Function

The USB function consists of the following blocks:

USB protocol engine

The USB protocol engine handles the basic USB communication protocol to reduce the load onapplication programs.

Note:

The following processing must be handled by application programs:

• Processing of class and vendor requests

• Set_Descriptor, Get_Descriptor, and Synch_Frame processing for standard requests

FIFO buffers for end points

For control:

IN: 8 bytes

OUT: 8 bytes

For bulk transfer:

IN: 64 bytes × 2 (double buffer)

OUT: 64 bytes × 2 (double buffer)

For interrupt transfer:

IN: 8 bytes

Interface (internal bus interface circuit) between end point and protocol engine

Registers

CPU DMA interface circuit

CPU interface: 16 bits (CS2X)

DMA interface: 16 bits (DREQ0, DREQ1)

378


The USB function macro program operates as a self-powered device.

Table 17.1-1 lists the end points of the USB function.

Table 17.1-1 End Points of the USB Function

End point

Configuration Interface ALTERNATE TRANS TYPEMax Packet

Size (in bytes)

0 - - - CONTROL 8

1 1 0 0 BULK(OUT) 64

2 1 0 0 BULK(IN) 64

3 1 0 0 INTERRUPT (IN) 8

379


Block Diagram

Figure 17.1-1 shows the block diagram of the USB function.

Figure 17.1-1 Block Diagram of the USB Function

Internal bus (8 bits)

Control and status registers

CPU/DMA interface

Internal bus interface

USB (D+,D-)

Protocol engine

FIFOs for ENDPOINT

CPU (16-bit)/DMA (16-bit) bus

380


17.2 USB Interface Registers

This section describes the configuration and functions of the registers used for the USB interface.

USB Interface Registers

The USB interface is connected to the CS2 area via an external memory interface. For theexternal memory interface, see "APPENDIX G External Bus Interface Setting".

DMA request of USB end point 1 and 2 is connected to the external transfer request pin of ch0and ch1 for DMAC, respectively.

The DMA request is Hi-active.

Byte access to the internal registers of the USB interface is not allowed.

Figure 17.2-1 shows the register map for the USB interface.

381


Figure 17.2-1 Register Map for the USB Interface

Address Register name

0006_0000 FIFO0o

0006_0002 FIFO0i

0006_0004 FIF01

0006_0006 FIF02

0006_0008 FIF03

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

0006_0022 CONT1

0006_0024 CONT2

0006_0026 CONT3

0006_0028 CONT4

0006_002A CONT5

0006_002C CONT6

0006_002E CONT7

0006_0030 CONT8

0006_0032 CONT9

0006_0034 CONT10

0006_0036 TTSIZE

0006_0038 TRSIZE

0006_0040 RSIZE0

0006_0044 RSIZE1

0006_0062 ST1

0006_0068 ST2

0006_006A ST3

0006_006C ST4

0006_006E ST5

0006_007E RESET

382


Notations for Registers

The notations described below are used to explain each USB interface register.

Figure 17.2-2 shows the notations for the registers.

Figure 17.2-2 Notations for Registers

*1: Indicates the bit positions (15 to 0) in each register.

*2: Indicates the bit names in each register.

*3: Indicates that the register does not exist physically. The read value is always 0.

*4: Indicates whether the bit is readable and/or writable.

W: Write-only

R: Read-only

R/W: Readable and writable

*5: Indicates the bit value after reset (RESET = 0)

"X": Undefined

"0": 0

"1": 1

Note:

Each register must be accessed in units of 16 bits.

15*1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value*5

Address:0000-0000H *3 *2 XXXXXXXXXXXXXXXXB

R*4 R R R R R R R R R R R R R R R

383


17.2.1 Data Transmission Registers (for End Points)

Data transmission registers are available in the types listed below. Data is read from or written to an end point by reading from or writing to the corresponding data transmission register.• FIFO0o and FIFO0i• FIFO1 to FIFO3

FIFO0o

The FIFO0o register is an 8-byte FIFO buffer for end point 0 (CONTROL OUT end point). Theaddress of the FIFO0o register is 0006_0000H.

Figure 17.2-3 shows the FIFO0o register.

Figure 17.2-3 FIFO0o Register

USB transfer data is stored in the register in the order of byte 1 (bit15 to bit8) and byte 2 (bit7 tobit0). If only 1 byte of data is stored, it is stored in byte 1 (bit15 to bit8).

FIFO0i

The FIFO0i register is an 8-byte FIFO buffer for end point 0 (CONTROL IN end point). Theaddress of the FIFO0i register is 0006_0002H.

Figure 17.2-4 shows the FIFO0i register.

Figure 17.2-4 FIFO0i Register

USB transfer data is stored in the register in the order of byte 1 (bit15 to bit8) and byte 2 (bit7 tobit0). If only 1 byte of data is stored, it is stored in byte 1 (bit15 to bit8). A data stored in byte 2(bit7 to bit0) is ignored.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0000H XXXXXXXXXXXXXXXXB

R R R R R R R R R R R R R R R R

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value


W W W W W W W W W W W W W W W W

384


FIFO1

The FIFO1 register is a 64-byte FIFO buffer for end point 1 (BULK OUT end point). The addressof the FIFO1 register is 0006_0004H.

Figure 17.2-5 shows the FIFO1 register.

Figure 17.2-5 FIFO1 Register

USB transfer data is stored in the register in the order of byte 1 (bit15 to bit8) and byte 2 (bit7 tobit0). If only 1 byte of data is stored, it is stored in byte 1 (bit15 to bit8).

The FIFO1 register has a double-buffer configuration (64 bytes × 2). The FIFO buffer is switchedat the following timings:

• On the USB bus side: When ACK is transferred

• On the CPU bus side: When the BFOK1 bit of the CONT3 register is set to 1

Note that switching is done at DMA transfer because the BFOK1 bit ofthe CONT3 register is automatically set to 1 at DMA transfer.

FIFO2

The FIFO2 register is a 64-byte FIFO buffer for end point 2 (BULK IN end point). The address ofthe FIFO2 register is 0006_0006H.




The FIFO2 register has a double-buffer configuration (64 bytes × 2). The FIFO buffer is switchedat the following timings:

• On the USB bus side: When ACK is transferred

• On the CPU bus side: When the BFOK2 bit of the CONT3 register is set to 1

Note that switching is done at DMA transfer because the BFOK2 bit ofthe CONT3 register is automatically set to 1 at DMA transfer.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value


R R R R R R R R R R R R R R R R

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value



385


FIFO3

The FIFO3 register is an 8-byte FIFO buffer for end point 0 (INTERRUPT IN end point). Theaddress of the FIFO3 register is 0006_0008H.




15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value



386


17.2.2 Status Registers

Status registers are available in the types listed below. Internal status is monitored by reading the status registers.• ST1 to ST5• RSIZE0 and RSIZE1

ST1

The ST1 register has interrupt source bits and is used to monitor the ACK and NACK signals forUSB transfer. The address of the ST1 register is 0006_0062H.

Figure 17.2-8 shows the ST1 register.

Figure 17.2-8 ST1 Register

Table 17.2-1 lists the bits of the ST1 register and their functions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0062H NACK3

ACK3

NACK2

ACK2

NACK1

ACK1

NACK0i

ACK0i

NACK0o

ACK0o

XXXXXX0000000000B

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Table 17.2-1 Bits of the ST1 Register

Bit name Polarity Function

ACK0o ActiveHighThis bit indicates that the device received an ACK handshake signal during OUT transfer at end point 0.

NACK0o ActiveHighThis bit indicates that the device received an NACK handshake signal, received a transfer request in stalled status, or detected a packet error during OUT transfer at end point 0.

ACK0i ActiveHighThis bit indicates that the device received an ACK handshake signal during IN transfer at end point 0.

NACK0i ActiveHighThis bit indicates that the device received a transfer request in stalled status or time-out occurred during IN transfer at end point 0.

ACKn(n: 1 to 3)

ActiveHighThis bit indicates that the device sent and received an ACK handshake signal during transfer at end point n.

NACKn(n: 1 to 3)

ActiveHigh

The NACKn bit indicates that the device received an NACK handshake signal, received a transfer request in stalled status, or detected a packet error during OUT transfer at end point n.The NACKn bit indicates also that the device received a transfer request in stalled status or time-out occurred during IN transfer at end point n.

387


Each bit is cleared to 0 when 1 is written to the bit. Writing 0 to each bit is ignored.

The ACK1, NACK1, ACK2, and NACK2 bits provide two sides of registers corresponding to thedouble-buffer configuration. The sides of the ACK1, NACK1, ACK2, and NACK2 bits areswitched at the same time as buffer switching. The side of the ST1 register currently available forreading and writing by an application program corresponds to the side of the FIFO registerscurrently available for reading and writing.

ST2

Figure 17.2-9 shows the ST2 register. The address of the ST2 register is 0006_0068H.



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0068H DCT6

DCT5

DCT4

DCT3

DCT2

DCT1

DCT0

XXXXXXXXX0000000B

R R R R R R R



DCT[6:0] ActiveHigh

These bits indicate the number of bytes of data that was read from or written to an FIFO register via the USB bus.These bits are updated when an ACK handshake signal is sent and received after USB transfer has ended normally.

388


ST3


The address of the ST3 register is 0006_006AH.



Only 0 is valid for writing to bit2, bit4, and bit6.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-006AH STDREQ2

STDREQ1

EP

O0NULL

CFGVAL

SETUP

CFEND

SOF

SUSP - 00-------0000000B

R R R/W R R/W R R/W R R/W



- -This bit is reserved. WRITE is allowed, but it does not affect the USB transfer. The bit indicates ‘1’ or ‘0’ at READ.

SUSP ActiveHighThis bit is reset when the device enters the suspended status and is cleared when the device is released from the suspended status.

SOF ActiveHighThis bit indicates that an SOF packet was received.After this bit is set, the set status is retained until 0 is written to this bit.

CFEND ActiveHigh This bit indicates that initialization of the device was completed.

SETUP ActiveHigh

This bit indicates that a SETUP packet was received.This bit is set when the macro receives command that does not perform automatic response and it responds using the ACK. This bit is not set for command that does automatic response.This bit is reset when tha data of OUT transfer other than SETUP packet is received by control transfer and responds by the ACK.

CFGVLAL -This bit indicates current Configuration value.If the macro receives BUS RESET and Set Configuration 0, it transits to the default state. CFGVAL shows ‘0’ at the default state.

EPO0NULL ActiveHighThis bit indicates that the data packet of length 0 is received at OUT side in ENDPOINT0.Once it is set, 0 is retained until write operation is performed.

STDREQ1 ActiveHigh This bit indicates that DREQ1 asserts.

STDREQ2 ActiveHigh This bit indicates that DREQ2 asserts.

389


ST4


The address of the ST4 register is 0006_006CH.



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-006CH FMR10

FMR9

FMR8

FMR7

FMR6

FMR5

FMR4

FMR3

FMR2

FMR1

FMR0

XXXXX00000000000B

R R R R R R R R R R R



FMR[10:0] -

These bits indicate the frame number of the latest frame received by USB transfer.The received-frame number is extracted from an SOF packet.

390


ST5

The ST5 register has interrupt source bits. The address of the ST5 register is 0006_006EH.




Writing for each bit other than STSTALLWriting 1 to this bit is reset to 0. Writing 0 is prohibited.

When STSTALL is set, the NACK bit in ST1 register is simultaneously set.

To reset TTRSEND, write 1 after CONT10 TTCNTEN is set to 0.To reset TRCVEND, write 1 after CONT10 TRCNTEN is set to 0.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address: 0006-006EH RESERVED

SETCFG

USBRESET

STSRALL3

STSRALL2

STSRALL1

STSRALL0

TRCVEND

TTRSEND

0--00-----000000B

R/W R/W R/W R R R R R R/W R/W



TTRSEND ActiveHighThis bit indicates that data transmission for the specified total number of send bytes from the BULK IN FIFO buffer was completed.

TRCVEND ActiveHighThis bit indicates that data reading for the specified total number of receive bytes from the BULK OUT FIFO buffer was completed.

STSRALLn(n: 0 to 3)

ActiveHighThe STSTALLn bits indicate that end point n is in the stalled status. The bit is reset when the end point is released from the stalled status.

USERSET ActiveHigh This bit indicates that USB bus reset occurred.

SETCFG ActiveHighThis bit is set when Set Cofiguration is received and ACK is returned. This bit is reset by USB BUS RESET.

Reserved ActiveHigh Write ‘0’ to this bit.

391


RSIZE0

The RSIZE0 register indicates the size of the latest data transferred at end point 0 (CONTROLOUT end point). The address of the RSIZE0 register is 0006_0040H.

Figure 17.2-13 shows the RSIZE0 register.

Figure 17.2-13 RSIZE0 Register

Table 17.2-6 lists the bits of the RSIZE0 register and their functions.

The RSIZE0 bits are updated when the USB function macro program transmits an ACK signal.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0040H RSIZE3

RSIZE2

RSIZE1

RSIZE0

XXXXXXXXXXXX0000B

R R R R

Table 17.2-6 Bits of the RSIZE0 Register


RSIZE[3:0] -These bits indicate the size of the latest data transferred at end point 0 (CONTROL OUT end point).

392


RSIZE1

The RSIZE1 register indicates the size of the latest data transferred at end point 1 (BULK OUTend point). The address of the RSIZE0 register is 0006_0044H.

Figure 17.2-4 shows the RSIZE1 register.

Figure 17.2-14 RSIZE1 Register

Table 17.2-7 lists the bits of the RSIZE1 register and their functions.

The RSIZE1 register has two sides corresponding to the double-buffer configuration. The sidesof the RSIZE1 register are switched at the same time as buffer switching. The side of theRSIZE1 register currently available for reading and writing by an application program correspondsto the side of the FIFO register currently available for reading and writing.

The RSIZE1 bits are updated when the USB function macro program transmits an ACK signal.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0044H RSIZE16

RSIZE15

RSIZE14

RSIZE13

RSIZE12

RSIZE11

RSIZE10

XXXXXXXXX0000000B

R R R R R R R

Table 17.2-7 Bits of the RSIZE1 Register


RSIZE1[6:0] -These bits indicate the size of the latest data transferred at end point 1 (BULK OUT end point).

393


17.2.3 Control Registers

Control registers are available in the types listed below. The device is controlled by reading from or writing to the control registers.• CONT1 to CONT10• TTSIZE• TRSIZE• RESET

CONT1

The CONT1 register is used to initialize the device and resume device operation. The address ofthe CONT1 register is 0006_0022H.

Figure 17.2-15 shows the CONT1 register.

Figure 17.2-15 CONT1 Register

Table 17.2-8 lists the bits of the CONT1 register and their functions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0022H RESERVED

IODIS

AUTOBFOK

RESUM

S TALL3

S TALL2

S TALL1

S TALL0

CFGEN

000XX0XXXXX00000B

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Table 17.2-8 Bits of the CONT1 Register (1 / 2)


CFGEN ActiveHighWriting 1 to this bit executes initialization (setup of end point buffers). After the initialization (setting of ENDPOINT BUFFER) is executed, it does not perform until the macro is reset.

STALLn(n: 0 to 3)

ActiveHigh

Writing 1 to the STALLn bit sets end point n into the stalled status.Note:

This bit is a self-reset register.After 1 is written to this bit, it is automatically cleared to 0.

RESUM ActiveHigh

This bit is used to issue a request to resume operation of the device after the device is set into the suspended status (the SUSP bit of the ST3 register is 1). (Writing 1 to this bit sets a resume request.)Note:

This bit is a self-reset register.After 1 is written to this bit, it is automatically cleared to 0.

394


Only ‘1’ is valid for writing to the CFGEN bit.

STALL0, STALL1, STALL2, and STALL3 have a transfer request in Endpoint that set STALL, andit is reset when STALL is transmitted.

Even though STALL0 is set, the macro responds correctly if the setup is received. In this case,STALL0 is reset when the ACK response is performed for the setup.

AUTOBFOK ActiveHigh

If 1 is set when the received byte count of OUT side in ENDPOINT is 0, USB transfer of OUT side in ENDPOINT0 is automatically enabled. At that time, ST1.ACKO0 interrupt cause is not asserted. (Set CONT3.BFOKO0 bit to 1 automatically.)

IODIS ActiveHighIf this bit set to ‘1’, the SUSPEND signal (macro output signal) is asserted.When this bit is set or this device is in the suspend state, the SUSPEND signal is asserted.

Reserved ActiveHigh Write ‘0’ to this bit.

Table 17.2-8 Bits of the CONT1 Register (2 / 2)


395


CONT2

The CONT2 register is used to initialize the FIFO registers. The address of the CONT2 register is0006_0024H.




Only 1 is valid for writing to every bit of the CONT2 register.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0024H INI3

INI2

INI1

INI0i

INI0o

XXXXXXXXXXX00000B

R/W R/W R/W R/W R/W

Table 17.2-9 Bits of the CONT2 Register


INI0o ActiveHigh

Writing 1 to this bit initializes the address counter of the FIFO0o register. At the same time, the ACK0o and NACK0o bits of the ST1 register, the RSIZE0 register, and the BFOK0o bit of the CONT3 register are initialized.This bit is a self-reset register.After 1 is written to this bit, it is automatically cleared to 0.

INI0i ActiveHigh

Writing 1 to this bit initializes the address counter of the FIFO0i register. At the same time, the ACK0i and NACK0i bits of the ST1 register, the BFOK0i bit of the CONT3 register, and the LSTD0 bit of the CONT10 register are initialized.This bit is a self-reset register. After 1 is written to this bit, it is automatically cleared to 0.

INI1 ActiveHigh

Writing 1 to this bit initializes the address counter of the FIFO1 register. At the same time, the double-buffer switching status, the ACK1 and NACK1 bits of the ST1 register, the RSIZE1 register, the BFOK1 bit of the CONT3 register, and the TRSIZE register are initialized.This bit is a self-reset register.After 1 is written to this bit, it is automatically cleared to 0.

INI2 ActiveHigh

Writing 1 to this bit initializes the address counter of the FIFO2 register. At the same time, the double-buffer switching status, the ACK2 and NACK2 bits of the ST1 register, the BFOK2 bit of the CONT3 register, the LSTD2 bit of the CONT10 register, and the TISIZE register are initialized.This bit is a self-reset register.After 1 is written to this bit, it is automatically cleared to 0.

INI3 ActiveHigh

Writing 1 to this bit initializes the address counter of the FIFO3 register. At the same time, the ACK3 and NACK3 bits of the ST1 register, the BFOK3 bit of the CONT3 register, and the LSTD3 bit of the CONT10 register are initialized.This bit is a self-reset register.After 1 is written to this bit, it is automatically cleared to 0.

396


Each bit of the CONT2 register is cleared to 0 automatically after 1 is written to each bit.Therefore, the value of each bit normally read by the CPU is always 0.

All bits of the registers (ST1, RSIZE1, CONT3, and CONT10) that have two sides correspondingto the double-buffer configuration (end points 1 and 2) are initialized when the INI1 or INI2 bit isset.

Reading and writing of the FIFO buffer and other registers initialized by setting the INIn bit (n: 0o,0i, 1, 2, or 3) are disabled until nine cycles are counted by CPUCLK after the INIn bit is set.

If each bit of BFOK for CONT3 sets each bit of INI, the following value is set.

End point for IN transfer BFOK=0

End point for OUT transfer BFOK=1

397


CONT3

The CONT3 register is used to enable USB transfer at each end point. The address of theCONT3 register is 0006_0026H.




If the ACK0o or ACK0i bit of the ST1 register is set for an end point, the BFOK bit correspondingto the end point cannot be set. However, even if the NACK0o or NACK0i bit of the ST1 register isset for an end point, the BFOK bit corresponding to the end point can be set. When deviceinitialization is completed (when the CFEND bit of the ST3 register is set) or the INIn bit of theCONT2 register is set, the BFOK bits are set to values as follows:

• End point for IN transfer: BFOK = 0

• End point for OUT transfer: BFOK = 1

All bits of CONT3 is enabled by writing 1 only.After 1 is set to CONT3, and if the FIFO is set to BUBY, set FIFOBUSY bit of CONT4 andDFIFOBUSY bit of CONT5 to 0.

Writing 1 to the BFOK1 and BFOK2 bits (for double-buffer end points) switches the side of thedouble buffer. At the same time, the side of the CONT3 registers is switched accordingly. Theside of the CONT3 register currently available for reading and writing by an application programcorresponds to the side of the FIFO registers currently available for reading and writing. Anapplication program can access only one side of registers and cannot access the other side of theregisters.

Each BFOK bit is reset when ACK transfer occurs at the corresponding end point.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0026H BFOK3

BFOK2

BFOK1

BFOK0i

BFOK0o

XXXXXXXXXXX00000B

R/W R/W R/W R/W R/W



BFOK0o ActiveHighWriting 1 to this bit enables USB transfer on the OUT side of end point 0.

BFOK0i ActiveHighWriting 1 to this bit enables USB transfer on the IN side of end point 0.

BFOKn(n: 1 to 3)

ActiveHighWriting 1 to the BFOKn bit enables USB transfer at end point n.

398


CONT4

The CONT4 register is used to set each end point into the USB busy status. The address of theCONT4 register is 0006_0028H.




To perform transfer by CPU access, the NACK handshake can always be returned in response toa token from the HOST when 0 is written to FIFOBUSYn. Always write 0 to this bit for DMAtransfer.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0028H FIFOBUSY3

FIFOBUSY2

FIFOBUSY1

FIFOBUSY0i

FIFOBUSY0o

XXXXXXXXXXX00000B

R/W R/W R/W R/W R/W



FIFOBUSY (n: 0o, 0i, 1

to 3)ActiveLow

This bit is used to set end point n into the busy status.

399


CONT5

The CONT5 register is used to set each end point into USB busy status. The address of theCONT5 register is 0006_002AH.




To perform transfer by DMA, the NACK handshake can always be returned in response to atoken from the HOST when writting 0 to FIFOBUSYn. Always write 0 to this bit for DMA transfer.

To perform transfer by CPU access, always set to 0.

To write 0 to DFIFOBUSYn, the DREQ is masked by setting MDREQ bit to 0.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-002AH DFIFOBUSY2

DFIFOBUSY1

XXXXXXXXXXXX00XXB

R/W R/W



DFIFOBUSYn (n: 1 to 2)

ActiveLowThis bit is used to set end point n into the busy status.

400


CONT6

The CONT6 register is used to mask DREQ at each end point. The address of the CONT6register is 0006_002CH.




15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-002CH MDREQ2

MDREQ1

XXXXXXXXXXXX00XXB

R/W R/W



MDREQn(n: 1 to 2)

ActiveLowThis bit is used to mask DREQn assertion during transfer at end point n.

401


CONT7

The CONT7 register is used to mask the IRQ due to an ACK source at each end point. Theaddress of the CONT7 register is 0006_002EH.




15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-002EH MACK3

MACK2

MACK1

MACK0i

MACK0o

XXXXXXXXXXX00000B

R/W R/W R/W R/W R/W



MACK0o ActiveLowThis bit is used to mask IRQ assertion by an ACK signal during OUT transfer at end point 0.

MACKOi ActiveLowThis bit is used to mask IRQ assertion by an ACK signal during IN transfer at end point 0.

MACKn(n: 1 to 3)

ActiveLowThis bit is used to mask IRQ assertion by an ACK signal during transfer at end point n.

402


CONT8

The CONT8 register is used to mask the IRQ due to an NACK source at each end point. Theaddress of the CONT8 register is 0006_0030H.




15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0030H MNACK3

MNACK2

MNACK1

MNACK0i

MNACK0o

XXXXXXXXXXX00000B

R/W R/W R/W R/W R/W



MNACK0o ActiveLowThis bit is used to mask IRQ assertion by a NACK signal during OUT transfer at end point 0.

MNACKOi ActiveLowThis bit is used to mask IRQ assertion by a NACK signal during IN transfer at end point 0.

MNACKn(n: 1 to 3)

ActiveLowThis bit is used to mask IRQ assertion by a NACK signal during transfer at end point n.

403


CONT9

The CONT9 register is used to mask the IRQ due to a STALL source at each end point. Theaddress of the CONT9 register is 0006_0032H.




15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0032H

-

MSETCFG

MUSBRESET

MSTALL3

MSTALL2

MSTALL1

MSTALL0

0XX0XXXX0XXX0000B

R/W R/W R/W R/W R/W R/W R/W



MSTALLn (n: 0 to 3)

ActiveLowThis bit is used to mask IRQ assertion by a STALL signal at end point n.

MUSBRESET ActiveLowThis bit is used to mask IRQ assertion by a USB bus reset signal.

MSETCFG ActiveLow IRQ is masked by SETCFG.

- ActiveLow Write ‘0’ to this bit.

404


CONT10

The address of the CONT10 register is 0006_0034H.




The LSTD bit need not be reset by the CPU because the bit is reset automatically at reception ofan ACK signal after the last packet has been transmitted. The ODD bit need not be reset by theCPU because the bit is reset automatically after the last data has been written.

The NULLSET bit is valid for the data stage of control transfer and for BULK IN transfer interruptIN transfer. If the NULLSET bit is set to 1, a null packet is transmitted automatically in responseto the transfer request after the last packet is transmitted when the size of the last packet is equalto the maximum packet size. Note that the NULLSET bit does not control the transmission of 0-

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0034H DREQCNT

ODD3

ODD2

ODD0

NULLSET3

NULLSET2

NULLSET0

DMAMODE

LSTD3

LSTD2

LSTD0

TRCNTEN

TTCNTEN

00000000X00000XXB

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W



LSTDn(n: 0, 2, 3)

ActiveHighThe LSTDn bit is used to report writing of the last packet to end point n.This bit is set before writing the last data.

ODDn(n: 0, 2, 3)

ActiveHighThis bit is used to report writing of a short packet having an odd byte count.This bit is set before writing the last data.

TTCNTEN ActiveHigh This bit is used to enable the total send byte counter.

TRCNTEN ActiveHigh This bit is used to enable the total receive byte counter.

DMAMODE -Select a transfer method of DMA.1: Single transfer, 0: Block transfer

NULLSETn (n: 0, 2, 3)

ActiveHigh This bit is set to 1 for automatic transmission of a null packet.

DREQCNT -

Control DREQ assertion after the data transfer for number of total transfer byte is ended. 1: After the data transfer for number of total transfer byte is

ended, DREQ is not asserted until number of byte for next total transfer is set .

0: After the data transfer for number of total transfer byte is ended, DREQ is asserted.

405


byte packets in the status stage of control transfer.

The LSTD2 bit provides two sides of registers corresponding to the double-buffer configuration.The sides of the LSTD2 bit are switched at the same time as buffer switching. The side of theCONT10 register currently available for reading and writing by an application programcorresponds to the side of the FIFO registers currently available for reading and writing.

The LSTD2 has the above function. When the value of the LSTD2 bit changes from 1 to 0, itdoes not mean that transfer of the last packet ended.

If the NULLSET bit is 1, an interrupt by an ACK signal is asserted when transfer of null packetsends with an ACK signal (when an ACK signal is received). If the NULLSET bit is 0, an interruptby an ACK signal is asserted when transfer of the last packet ends with an ACK signal (when anACK signal is received).

Each bit of LSTD and 0DD is valid by writing 1. Writing 0 is disabled.

TTSIZE

The TTSIZE register is used to set and count the total send byte count for BULK IN transfer. Theaddress of the TTSIZE register is 0006_0036H.

Figure 17.2-25 shows the TTSIZE register.

Figure 17.2-25 TTSIZE Register

The TTSIZE register (counter) counts down each time send data is written to the FIFO buffer fortransmission.

To use the TTSIZE counter, set a value other than 0000H in the TTSIZE register, write 1 to theCONT10, TTCNTEN, then start write access to the FIFO buffer. Do not start write access to theFIFO buffer when 0000H is set in the TTSIZE register and the CONT10, TTCNTEN is 1.

TTSIZE sets MDREQ2 of CONT6 to 0 and DREQ2 to masked state.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0036H 0001000100010001B

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

406


TRSIZE

The TRSIZE register is used to set and count the total receive byte count for BULK OUT transfer.The address of the TRSIZE register is 0006_0038H.

Figure 17.2-26 shows the TRSIZE register.

Figure 17.2-26 TRSIZE Register

The TRSIZE register (counter) counts down each time receive data is read from the FIFO bufferfor reception.

To use the TRSIZE counter, set a value other than 0000H in the TRSIZE register, write 1 to theTRCNTEN bit of the CONT10 register, then start read access to the FIFO buffer. Do not startread access to the FIFO buffer when 0000H is set in the TRSIZE register and the TRCNTEN bit ofthe CONT10 is 1.

TRSIZE sets MDREQ1 of CONT6 to 0 and DREQ1 to masked state.

When the USB operation is started, the synchronization RESET is required to input 16 clocksmore than by the USB clock for RESET of USB, see "APPENDIX E Macro Reset".

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address:0006-0038H 0001000100010001B

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Address Register name0006_0000 FIFOo

0006_0002 FIFO0i

0006_0004 FIFO1

0006_0006 FIFO2

0006_0008 FIFO3

Reserved

0006_0022 CONT1

0006_0024 CONT2

0006_0026 CONT3

0006_0028 CONT4

0006_002A CONT5

0006_002C CONT6

0006_002E CONT7

0006_0030 CONT8

0006_0032 CONT9

0006_0034 CONT10

0006_0036 TTSIZE

0006_0038 TRSIZE

Reserved

0006_0040 RSIZE0

Reserved

0006_0044 RSIZE1

(Continued)

407


RESET

At starting USB, it is necessary to input more than 16 clocks as the synchronous RESET by USBblock. For detail of USB see "APPENDIX D USB Clock".

Reserved

0006_0062 ST1

Reserved

0006_0068 ST2

0006_006A ST3

0006_006C ST4

0006_006E ST5

Reserved

0006_007E RESET

(Continued)

Address Register name

408


17.3 Operation of the USB Function

This section describes the flow of data transfer, CPU access operation, and DMA operation by the USB function.

Operation of the USB Function

This section explains the following items of operation:

• Flow of data transfer

• Setup stage of control transfer (most standard commands)

• Setup stage of control transfer (class and vendor commands and some standardcommands [Get_Descriptor, Set_Descriptor, and Synch_Frame])

• Status stage of control transfer (most standard commands)

• Status stage of control transfer (class and vendor commands and some standardcommands [Get_Descriptor, Set_Descriptor, and Synch_Frame])

• Control transfer (data stage) or BULK OUT transfer

• Control transfer (data stage), bulk transfer, or INTERRUPT IN transfer

• CPU access operation

• CPU IN transfer

• CPU OUT transfer

• DMA operation

• DMA IN transfer

• DMA OUT transfer

• Read and write timing diagrams for DMA single transfer

• Read and write timing diagrams for DMA block transfer

• Interrupt sources

• Setting of end point buffer

• Examples of software control

• Setup

• Reception at CPU access

• Transmission at CPU access

• DMA reception

• DMA transmission

409


17.3.1 Flow of Data Transfer

This section describes the flow of data transfer by the USB function.

Setup Stage of Control Transfer (Most Standard Commands)

The protocol engine automatically processes almost all standard commands received from thehost to reduce the load on the CPU of the device. The CPU of the device need not perform anyprocessing of these commands. The protocol engine does not even report reception of thesecommands to the CPU of the device. The protocol engine automatically processes thecommands listed below.

Clear_Feature, Get_Configuration, Get_Interface, Get_Status, Set_Address, Set_Configuration,Set_Feature, and Set_Interface

Figure 17.3-1 shows the flow of the setup stage of control transfer (to process most standardcommands).

Figure 17.3-1 Flow of the Setup Stage of Control Transfer (to Process Most Standard Commands)

The flow shown by the figure is explained below.

(1) When a command for the setup stage of control transfer is received from the USB, theprotocol engine asserts the SETUP pin and sets the SETUP bit of the status register.

(2) If a standard command other than Get_Descriptor, Set_Descriptor, and Sync Frame isreceived and the setup stage ends, the protocol engine sets the NACKOS bit of the statusregister. In this case, the protocol engine performs the processing required for the commandand does not write data to any FIFO buffer for the end point.

Note:

The CPU (application program) need not perform any processing.

If the setup stage command is received normally, an ACK handshake signal is transferred to theUSB. If the setup stage command is not received normally, nothing is transferred to the USB (time-out occurs).

Protocol engine

Inte

rnal

bus

Inte

rnal

bus

I/F


Control and

status registers

CP

U I/

F(1)

(2)

CP

U B

US

USB

410


Setup Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame])

The class and vendor commands and some standard commands (Get_Descriptor,Set_Descriptor, and Synch_Frame) received from the host are written to the FIFO buffer for OUTtransfer at end point 0.

Figure 17.3-2 shows the flow of the setup stage of control transfer (to process class and vendorcommands and some standard commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]).

Figure 17.3-2 Flow of the Setup Stage of Control Transfer (to Process Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame])


(1) When the setup stage of control transfer is started by the USB, the protocol engine asserts theSETUP pin and sets the SETUP bit of the status register.

(2) If a Get_Descriptor, Set_Descriptor, Sync Frame, class, or vendor command is received, theprotocol engine writes the data in the setup stage to the FIFO0o register and increments thevalue of the write transfer size register.

(3) If the setup stage ends normally, the protocol engine transmits an ACK handshake signal tothe USB. At this time, the ACK0o bit of the ST1 register (status register) is set and the valueof the write transfer size register is loaded into the RSIZE0 register (status register). Theprotocol engine also asserts the IRQ pin to externally report that data in the setup stage wasreceived.If the setup stage does not end normally because of an error, the protocol engine does notreturn anything to the USB, discards the received data, and sets the NACK0o bit of the statusregister.

(4) Valid data is read from the FIFO0o register into the CPU interface.

Note:

A command received as data must be decoded and processed by an application program.

Protocol engine


Control and

status registers

CP

U I/

F

(1)

(2)

(3)

(4)

USB

Inte

rnal

bus C

PU

BU

S

Inte

rnal

bus

I/F

411


Status Stage of Control Transfer (Most Standard Commands)

The protocol engine automatically processes all the standard commands (except Get_Descriptor,Set_Descriptor, and Sync Frame) as listed below. When these commands are processed, thevalues of the status registers in the device do not change and any interrupt signal IRQ is notasserted.

Clear Feature, Get Configuration, Get Interface, Get Status, Set Address, Set Configuration, SetFeature, and Set Interface

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame])

For writing control data

The protocol engine transfers 0-byte data to the USB. If the transfer ends normally, the ACK0i bitof the status register is set and the IRQ pin is asserted.

To prepare for the next transfer, the IRQ pin must be deasserted (by resetting the ACK0i bit of thestatus register) and the BFOK0i bit of the control register must be set by the application program.

The application program need not make any setting for transfer of 0-byte data.

For reading control data

The protocol engine receives 0-byte data from the USB.

The RSIZE0 register indicates a receive transfer size of 0 bytes.

When the transfer ends normally, the ACK0o bit of the status register is set and the IRQ pin isasserted.

To prepare for the next transfer, the IRQ pin must be deasserted (by resetting the ACK0o bit ofthe status register) and the BFOK0o bit of the control register must be set by the applicationprogram.

412


Control Transfer (Data Stage) and BULK OUT Transfer

Transfer data is written to the FIFO buffer for OUT transfer at an end point and read via the localbus interface.

Figure 17.3-3 shows the flow of control transfer (data stage) and BULK OUT transfer.

Figure 17.3-3 Flow of Control Transfer (Data Stage) and BULK OUT Transfer


(1) When transfer in the OUT direction is started by the USB, the protocol engine outputs theaddress of the transfer-destination end point and transmits transfer data sequentially to theinternal bus while executing a CRC check, bit stripping, and serial-to-parallel conversion.

Notes:

1. If the BFOK bit of the control register corresponding to the transfer-destination end point is not setwhen the transfer in the OUT direction is started, the protocol engine outputs a NACK handshakesignal to the USB and terminates the transfer.

2. If the STALL bit of control register corresponding to the transfer-destination end point is set whentransfer in the OUT direction is started, the protocol engine outputs a STALL handshake signal tothe USB and terminates the transfer. Then, the NACK bit of the ST1 register (status register) andthe STSTALL bit of the ST5 register (status register) are set.

(2) Received data is written to the FIFO buffer for the transfer-destination end point via theinternal bus, and the value of the transfer size register is incremented.

(3) When transfer of one packet ends normally, the protocol engine outputs an ACK handshakesignal to the USB. Then, the ACK bit of the status register is set and the value of the transfersize register is loaded into the RSIZE0 or RSIZE1 register. The protocol engine also assertsthe IRQ pin to externally report that transfer of one packet has ended. If an error is detectedduring transfer, the NACK bit of the status register is set and the transfer is terminated.

(4) Valid data is read from the FIFO buffer for the end point via the CPU interface.

Protocol engine


Control and

status registers

(1)

(2)

(3)

(4)

USB In

tern

al b

us CP

U I/

F

CP

U B

US

Inte

rnal

bus

inte

rface

413


Notes:

3. For reading by the CPU, data is read from bit15 to bit0 of the DATAO register in units of 2 bytes.

4. If the data size of a packet normally received during BULK OUT transfer is 0 bytes, the macroprogram does not generate any interrupt.

Control Transfer (Data Stage), Bulk Transfer, or INTERRUPT IN Transfer

The data written from the local bus interface to the FIFO buffer for IN transfer at an end point istransferred by the protocol engine to the USB bus.

Figure 17.3-4 shows the flow of control transfer (data stage), bulk transfer, and INTERRUPT INtransfer.

Figure 17.3-4 Flow of Control Transfer (Data Stage), Bulk Transfer, and INTERRUPT IN Transfer


(1) Before the IN transfer to the USB, data is written from the CPU interface to the FIFO buffer foran end point by a write operation.

31 . . . . . 8 7 6 5 4 3 2 1 0

63 . . . . . 17 15 13 11 9 7 5 3 1

Writing by protocol

engine

62 . . . . . 16 14 12 10 8 6 4 2 0

FIFO pointer

FIFO buffer for

end point

Via CPU interface

Protocol engine


Controland

status registers

(1)

(2)

(3) (4)

USB

Inte

rnal

bus

Inte

rnal

bus

inte

rfac

e

CP

U I/

F

CP

U B

US

414


Notes:

1. Valid data is written from the CPU to bit15 to bit0 of the DATAI register in units of 2 bytes.

(2) If the BFOK bit of the control register corresponding to the transfer-destination end point is set,subsequent IN transfer requests from the USB to the end point are processed.

Notes:

2. If an IN transfer request from the USB is received at the end point before the BFOK bit is set, theNACK bit of the status register is set and an NACK handshake signal is returned to the USB.

3. If the STALL bit of control register is set when an IN transfer request from the USB is received, aSTALL handshake signal is returned to the USB.

Then, the NACK bit of the ST1 register (status register) and the STSTALL bit of the ST5register (status register) are set.

(3) When an IN transfer request is received from the USB, the protocol engine reads, from theFIFO buffer for the end point, as much transfer data as the number of bytes written to theFIFO buffer.

(4) The protocol engine executes parallel-to-serial conversion, CRC generation, and bit stuffingfor the data read from the FIFO buffer for the end point then outputs the processed data to theUSB. If the transfer ends normally (an ACK handshake is received), the ACK bit of the statusregister is set. If the transfer fails, the NACK bit of the status register is set.

63 . . . . . 8 7 6 5 4 3 2 1 0

63 . . . . . 17 15 13 11 9 7 5 3 1

Reading by the

protocol engine

62 . . . . . 16 14 12 10 8 6 4 2 0

FIFO pointer

Writing from the

CPU I/F

FIFO buffer for end point

415


17.3.2 CPU Access Operation

This section describes the CPU access operation by the USB function.

CPU IN Transfer

For CPU IN transfer, data is written to an FIFO buffer for IN transfer, then the BFOK bit of thecontrol register corresponding to the FIFO buffer is set to enable transfer. The USB functionmacro program has a counter function to count the total number of send bytes. This function canbe used to simplify the setting of the last packet transmission. IN transfer can also be donewithout using the counter function. The setting of the last packet transmission varies dependingon whether the counter function is used.

Total send byte counter (16 bits)

The total send byte counter counts the total number of bytes of the data to be transmitted. Thecounter counts down each time data is written to the FIFO buffer. To use the counter, the systemmust set a total send byte count in the TTSIZE register. The counter cannot be used for controltransfer.

Data transmission

For data transmission, one packet (Max 64 bytes) of data is written to an end point buffer, thenthe BFOK bit of the control register corresponding to the end point buffer is set by the system toenable transfer.

Last packet

The setting for transmission of the last packet varies depending on whether the total send bytecounter is used or not. The settings in both cases are explained below.

When using the total send byte counter:

Transmission is done according to the packet size of the last packet* as follows:

• Maximum-size packet

A null packet is sent automatically after packet transmission ends. Automatic transmission ofa null packet can be disabled by using the NULLSET bit of the control register.

• Even-byte short packet

Packet transmission is started when the BFOK bit (to enable transfer) of the control register isset.

• Odd-byte short packet

Transmission is the same as that for the even-byte short packet.

416


When the total send byte counter is not used:

The LSDT bit of the control register is used (it is set before writing of the last data) to reportwriting of the last data.



A null packet is sent automatically after packet transmission ends. Automatic transmission ofa null packet can be disabled by using the NULLSET bit of the control register.




The ODD bit of the control register is set to report writing of a packet having an odd number ofbytes before writing the last data.


* : Packet size of the last packet

Maximum-size packet: A packet whose packet size is the maximum limit (64 bytes)

Even-byte short packet: A packet whose packet size is less than the maximum limit andwhose number of bytes is even

Odd-byte short packet: A packet whose packet size is less than the maximum limit andwhose number of bytes is odd

Note:

If automatic transmission of a null packet is enabled, no interrupt occurs until transmission of the nullpacket ends normally after the last data has been written.

If automatic transmission of a null packet is disabled, no interrupt occurs until transmission of the lastpacket ends normally after the last data has been written.

417


Table 17.3-1 lists the register settings for CPU IN transfer.

CPU OUT Transfer

For CPU OUT transfer, received data is read from an FIFO buffer for OUT transfer, then theBFOK bit of the control register corresponding to the FIFO buffer is set to enable transfer. TheUSB function macro program has a counter function to count the total number of receive bytes.This function can be used to know when reading of all received data is completed. OUT transfercan also be done without using the counter. The interrupt indicating completion of the totaltransfer is generated only when the counter is used. Therefore, if the counter is not used, theCPU must determine the completion of transfer from the ACK interrupt indicating the completionof transmission.

Data reception

When readable data is stored in an end point buffer, the USB function macro program throws theinterrupt request IRQ. The size of received data is set in the RSIZE register (receive data sizeregister). After the size of received data is read from the RSIZE register, data of that size is readfrom the end point buffer. After the data is read from the end point buffer, the BFOK bit of thecontrol register corresponding to the end point buffer is set by the system to enable transfer.

Total receive byte counter (16 bits)

The USB function macro program has a counter function to count the total number of receivebytes.

The total receive byte counter counts down each time the CPU reads received data from therelevant FIFO buffer. The initial value of the counter is set in the TRSIZE register. Interrupt IRQis generated when the count reaches 0. This indicates that reading of all received data has beencompleted. The counter cannot be used for control transfer.

Note:

If the data size of a packet normally received during BULK OUT transfer is 0 bytes, the macroprogram does not generate any interrupt.

Table 17.3-1 Register Settings for CPU IN Transfer (O: Setting Required)

TTSIZE (register)

BFOK (register)

LSTD (register)

ODD (register)

Packet other than last packet

Used

O

Last packet

Maximum-size packet

Even-byte packet

Odd-byte packet

Packet other than last packet

Not usedLast packet

Maximum-size packet O

Even-byte packet O

Odd-byte packet O O

418


17.3.2.1 DMA Operation

This section describes the DMA operation by the USB function. The DMA transfer by the USB function is available in two modes: single transfer and block transfer.One of the DMA transfer modes (single transfer or block transfer) can be selected using the DMAMODE bit of the CONT10 register (control register).DMA transfer can be applied to BULK IN transfer and BULK OUT transfer.Data other than 0-byte data can be transferred by DMA transfer.

DMA IN Transfer

For DMA IN transfer, data is written to an FIFO buffer for IN transfer, then the BFOK bit of thecontrol register corresponding to the FIFO buffer is automatically set to enable transfer. The USBfunction macro program has a counter function to count the total number of send bytes. Usingthis counter function enables automatic transmission of the last packet.

Total send byte counter (16 bits)

The total send byte counter counts the total number of bytes of the data to be transmitted. Thecounter counts down each time data is written to the FIFO buffer. For the counter, a total sendbyte count is set in the TTSIZE register by the system. The counter cannot be used for controltransfer or interrupt transfer.

Data transmission

Data transmission is started automatically when the relevant FIFO buffer (64 bytes) becomes fullor writing of the last packet ends.

Transmission of the last packet is explained below.

Transmission of the last packet



Packet transmission is started automatically when the amount of data indicated by the totalsend byte count in the TTSIZE register has been written. A null packet is sent automaticallyafter packet transmission ends. Automatic transmission of a null packet can be disabled byusing the NULLSET bit of the control register.


Packet transmission is started automatically when the amount of data indicated by the totalsend byte count in the TTSIZE register has been written.

419



Transmission is the same as that for the even-byte short packet.

* : Packet size of the last packet

Maximum-size packet: A packet whose packet size is the maximum limit (64 bytes)

Even-byte short packet: A packet whose packet size is less than the maximum limit andwhose number of bytes is even

Odd-byte short packet: A packet whose packet size is less than the maximum limit andwhose number of bytes is odd

Note:

If automatic transmission of a null packet is enabled, a subsequent DREQ is not generated untiltransmission of the null packet ends normally after the last data has been written.

If automatic transmission of a null packet is disabled, a subsequent DREQ is not generated untiltransmission of the last packet ends normally after the last data has been written.

DMA OUT Transfer

For DMA OUT transfer, received data is read from an FIFO buffer for OUT transfer, then the USBfunction macro program automatically sets the BFOK bit of the control register corresponding tothe FIFO buffer to enable transfer. The USB function macro program has a counter function tocount the total number of received bytes. This function can be used to know when reading of allreceived data is completed. OUT transfer can also be done without using the counter. Theinterrupt indicating completion of the total transfer is generated only when the counter is used.Therefore, if the counter is not used, completion of transfer must be determined by anothermethod.

Data reception

When readable data is stored in an end point buffer, the USB function macro program throwsDREQ. After all the data is read from the FIFO buffer, the USB function macro programautomatically sets the BFOK bit of the control register to enable transfer.

Total receive byte counter (16 bits)

The USB function macro program has a counter function to count the total number of receivebytes.

The total receive byte counter counts down each time the DMAC reads received data from therelevant FIFO buffer. The initial value of the counter is set in the TRSIZE register. Interrupt IRQis generated when the count reaches 0. This indicates that reading of all received data has beencompleted. The counter cannot be used for control transfer.

Note:

To perform BULK OUT transfer by the CPU after DMA OUT transfer ends, the INI1 bit of the CONT2register must be set to initialize the ACK and NACK bits (interrupt source bits) on both sides of theST1 register.

420


Read and Write Timing Diagrams for DMA Block/Step Transfer

FR corresponds to that of block of step transfer.

Figure 17.3-5 shows the read and write timing diagrams for DMA single transfer.

Figure 17.3-5 Read and Write Timing Diagrams for DMA Single Transfer

(Writing)

DREQ2

FMCLK0

DACK2

WR

DATAI[15:0]

Valid dataValid data

Last data

DACK and DATAI must not be changed while WR is at the low level.

DREQ is negated at the first rising edge of FMCLK0 after DACK is asserted.

DREQ is negated at the first rising edge of FMCLK0 after DACK is asserted.

Note 1: Frequency of FMCLK0 is 13 MHz or more.

RD

DREQ1

FMCLK0

DACK1

DATAOE

DACK must not be changed while RD is at the low level.

Output of valid data

Note 2:Data is written to the FIFO buffer at the last rising edge of FMCLK0 while WRis at the low level.

(Reading)


Note 2:The same signal input timing is applicable to the DACK1 and RD signals or the DACK2 and WR signals

421


Read and Write Timing Diagrams for DMA Demand Transfer

FR corresponds to that of demand transfer.

Figure 17.3-6 shows the read and write timing diagrams for DMA block transfer.

Figure 17.3-6 Read and Write Timing Diagrams for DMA Block Transfer

(Writing)

DREQ2

FMCLK0

DACK2

WR

DATAI[15:0]

Valid dataValid data

Last data

Note 2:Data is written to the FIFO buffer at the last rising edge of FMCLK0 while WR is at the low level.

DATAI must not be changed while WR is at the low level.



WR requires a deassertion period of two or more FMCLK0 cycles.

RD

DREQ

FMCLK

[DATA[15:0]

DACK

DATAOE

DREQ is negated at the first rising edge of FMCLK0 after the last RD for reading of one packet is asserted.

Output of valid data

DREQ is negated at the first rising edge of FMCLK0 after the last WR for writing of one packet is asserted.

(Reading)

RD requires a deassertion period of one or more FMCLK0 cycles.

Note 2:The same signal input timing is applicable to the DACKn signal and RD or WR signal.

422


17.3.3 Interrupt Sources

Table 17.3-2 lists the sources of interrupts to the USB function.

Interrupt Sources

Table 17.3-2 Interrupt Sources

Interrupt sourceCPU

accessDMA

accessStatus bit Mask bit

The end point entered the write-enabled status during IN transfer.

O -See the explanation of ST1 register.

See the explanation of CONT7 register.

The end point entered the read-enabled status during OUT transfer.

O -See the explanation of ST1 register.


The macro sent or received NACK. O OSee the explanation of ST1 register.


Transmission of total send data from the end point for transmission was completed.

O OTTRSEND bit of ST5 register

Reading of total received data from the end point for reception was completed.

O OTRCVEND bit of ST5 register

The device entered the stalled status. O OSTALLn of ST5 register


USB bus reset occurred. O OUSBRESET bit of ST5 register


(O: Interrupt IRQ is asserted.)

423


17.3.4 Setting of End Point Buffer

At power-on or after reset, the protocol engine of the USB function must write the settings related to the end points to the end point buffer in the protocol engine. A total of 20 bytes are required to store the settings related to the end points (5 bytes for each end point).

Setting of End Point Buffer

Figure 17.3-7 shows the flow of setting the end point buffer.

Figure 17.3-7 Flow of Setting the End Point Buffer

The flow in the figure is explained below.

(1) The USB function macro program is released from the reset status at the signal timing ofhardware or software reset.

(2) The CPU writes 20-byte data to the FIFO2 buffer.For the contents of the 20-byte data, see the explanation below.

(3) After the operation in step 2) is completed, the CFGEN bit of the CONT1 register (controlregister) is set.

(4) When the CFGEN bit is set as described in step 3), the protocol engine automatically readsthe 20-byte data from the FIFO2 buffer. As a result, the end point buffer in the protocol engineis set up.

(5) When the setting is completed, the CFEND bit of the ST3 register (status register) is set.

Protocol engine

Inte

rnal

bus

Inte

rnal

bus

inte

rfac

e

FIFO (FIFO2) buffer for end point buffer

Control and

status registers

CP

U I

/F

(2)

(3)

(4)

(5) C

PU

BU

S

End

poi

nt b

uffe

r

424


Note:

After the CFGEN bit is set in step 3), it takes about 3.4 µs until the CFEND bit is set in step 5).

Setting Contents

Figure 17.3-8 shows the data the CPU writes to the FIFO2 buffer to initialize the device.

Data is written in the order of lines shown in Figure 17.3-8 (the top line is written first, and thetenth line is written last).

On each line, the bit at the left end is the MSB.

Figure 17.3-8 Contents of End Point Buffer Settings

Data set in end point buffer Hexadecimal data

[15] [0]

0000000000000000

0001000010000000

0000000000010100

0010000010000000

1000000000000001

0010010000101000

1000000010000000

0000001000110100

0011100000010000

1000000000000011

0x0000

0x1080

0x0014

0x2080

0x8001

0x2428

0x8080

0x0234

0x3810

0x8003

425


17.3.5 Examples of Software Control

This section describes examples of controlling the USB function software.

Example of Controlling the Setup Operation

Figure 17.3-9 shows an example of controlling the setup operation.

Figure 17.3-9 Example of Controlling the Setup Operation

Release hardware and software from reset status

Write setup data to FIFO2 buffer for initialization

Set the SFGEN bit of CONT1 (control register)

Read the CFEND bit of ST3 (status register)

CFEND=1

YES NO

Start of setup

End of setup

Set the mask bits of CONT7 and CONT8

(control registers) (to reset masks)

426


Example of Controlling Reception at CPU Access

Figure 17.3-10 shows an example of controlling reception at CPU access.

Figure 17.3-10 Example of Controlling Reception at CPU Access

Write total receive byte count to TRSIZE (control register)

Set the TRCNTEN bit of CONT10 (control register)

To use the total receive byte counter, perform these operations before reading data from the FIFO buffer.

To 1)

Start of reception operation

427


SETUP=1

ACK0o = 1

BULK OUT transfer data

Is interrupt request IRQ generated

and asserted?

Read ST1 (status register)

NACK

NO

ACK

YES

Read the setup bit of ST3 (status register)

YES

NO

Read data from FIFO0o register

Process data by application program

(Perform this processing if necessary.)

(Next packet reception is enabled.)

Set the transfer enable bit of CONT3 (control register)

Clear the interrupt source bit of ST1 (status register)

YES

NO

Read the transfer size (RSIZE) for end point 0 from RSIZE0 (status register)

Read the transfer size (RSIZE) for end point 0 from RSIZE0 (status register)

Read data from FIFOn register


From 1)

End of reception operation

Is there an interrupt source?

Read data from FIFO0o register

Read the transfer size (RSIZE) for end point n from RSIZEn (status register)

A setup stage of control transfer is received as data.The data must be decoded because it is a class or vendor command or the Get_Descriptor, Set_Descriptor, or Synch_Frame command.

Data transfer to end point 0 (data stage of control transfer, etc.)

428


Example of Controlling Transmission at CPU Access

Transmission operation

Figure 17.3-11 shows an example of controlling transmission at CPU access.

Figure 17.3-11 Example of Controlling Transmission at CPU Access

Set the TTCNTEN bit of CONT10 (control register)

To use the total send byte counter, perform these operations before writing data to the FIFO buffer.

To 1)

Start of transmission operation

Write total receive byte count to TTSIZE (control register)

429


(Perform this processing if it is required after an interrupt.)

Transmission endsnormally.

Transfer was requested to an end point where transfer was not enabled by the host (where transfer data was not prepared).

Write data to the FIFO buffer for transmission


(Perform this processing if necessary.) Process data by application program.

Has transfer been enabled for the end point?

(Perform this processing when transmission of the next packet is enabled.)

Is interrupt request IRQ generated

and asserted?

Read ST1 (status register)

NACK ACK

Is there an interrupt source?

YES

YES

NO

The same datais transmitted again.

Set the transfer enable bit (BFOK) of CONT3 (control register)


From 1)

End of transmission operation

NO

430


Writing of send data of the last packet

Figure 17.3-12 shows an example of controlling writing of send data of the last packet duringtransmission at CPU access.

Figure 17.3-12 Example of Controlling Writing of Send Data of the Last Packet During Transmission at CPU Access

YES

Is data to be written the last data? * NO

Write last data to FIFO buffer for transmission

Set the LSTD bit of CONT10 (control register)

NO YES

Does data to be written have an odd

number of bytes?

Set the ODD bit of CONT10 (control register)

Write data to the FIFO buffer for transmission

*: Judgment is made by the system outside the macro program.

YES

Is total send byte counter (TTSIZE)

used? (*1)

NO

Last packet

End of writing of last packet

431


Example of Controlling DMA Reception

Figure 17.3-13 shows an example of controlling DMA reception.

Figure 17.3-13 Example of Controlling DMA Reception

Write total receive byte count to TRSIZE (control register)

Set the TRCNTEN bit of CONT10 (control register) to 1

*: No interrupts occur if the total receive byte counter is not used. The end of total data transfer must be determined by a method other than the macro program.

To use the total receive byte counter, perform these operations before reading data from the FIFO buffer.

Is DREQ asserted? NO

Read receive data (2 bytes) from FIFO buffer for reception

Is IRQ asserted?

YES

NO

YES

Read the TRCVEND bit of ST5 (status register)(*1)

Set the MDREQ1 bit of CONT6 (control register) to 1

End of reception operation

Start of reception operation

Clear the FIFOBUSY1 bit of CONT4 (control register) to 0

Set the DFIFOBUSY1 bit of CONT5 (control register) to 1

432


Example of Controlling DMA Transmission

Transmission operation

Figure 17.3-14 shows an example of controlling DMA transmission.

Figure 17.3-14 Example of Controlling DMA Transmission

Write total send byte count to TTSIZE (control register)

Set the TTCNTEN bit of CONT10 (control register) to 1

Clear the FIFOBUSY2 bit ofCONT4 (control register) to 0

To use the total send byte counter, perform these operations before writing data to the FIFO buffer.

*: No interrupts occur if the total send byte counter is not used. The end of total data transfer must be determined by a method other than the macro program.

Start of transmission operation

YES

Is IRQ asserted?

YES

Is DREQ asserted? NO

NO

Write send data (2 bytes) to FIFO buffer for transmission

Read the interrupt source bit(TTRSEND) of ST5 (status register)(*1)

End of transmission operation

Set the DFIFOBUSY2 bit of CONT5 (control register) to 1

Set the MDREQ2 bit ofCONT6 (control register) to 1

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Writing of send data of the last packet

Figure 17.3-15 shows an example of controlling writing of send data of the last packet duringDMA transmission.

Figure 17.3-15 Example of Controlling Writing of Send Data of the Last Packet during DMA Transmission

*: Judgment is made by the system outside the macro program.

YES

Is data to be written the last data? *

NO

Write last data to FIFO buffer for transmission

Write data to FIFO buffer for transmission

Use total send byte counter (TTSIZE)

Last packet

End of writing of last packet

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17.4 Supplementary Notes on the USB Function

This section gives supplementary notes on using the USB function macro program.

Supplementary Notes on the USB Function

This section gives notes on the following items:

• Double buffer

• Controlling the D+ terminating resistor on the board

• Automatic response of macro program to USB standard request commands

• USB function macro program operation in the default status

• USB clock control in the suspended status

• Detection of USB connector connection and disconnection

• Accuracy of UCLK48

• Setting of transfer enable bit (BFOK) during control transfer

• Precautions for control transfer

• Macro program status after USB bus reset

435


17.4.1 Double Buffer

This section gives supplementary notes on the double buffer of the USB function.

Double Buffer

• The USB function has double buffers (64 bytes × 2) for the end points for bulk transfer.

• During USB data transmission for IN transfer, the next packet data can be written by thesystem to the FIFO buffer for transmission.

• During OUT transfer, the next packet can be received while data is being read from thesystem.

• Buffers in the double buffer configuration are switched to each other in units of packets.

Timing Diagram for BULK IN Transfer (Writing by CPU and Reading by USB)

Figure 17.4-1 shows the timing diagram for double-buffer operation during BULK IN transfer andthe operation diagram.

In the example below, the MNACK bit of the CONT8 register (control register) is set so that anIRQ signal is not asserted by NACK.

436


Figure 17.4-1 Timing Diagram for BULK IN Transfer (Writing by CPU and Reading by USB)

* After the last data has been written, no interrupt occurs until transmission of the last packet ends. The end of transmission of the last packet must be determined from an interrupt because it cannot be determined from polling of the LSTD2 bit of the CONT10 register.

FIFO (a)

FIFO (b)

PACKET N PACKET N+1 PACKET N+1 LAST PACKET

Reading by USB

Writing by CPU

Writing by CPU

Reading by USB

ACK1

Reading by USB

Reading by USB

Writing by CPU

NACK1 ACK2

IRQ

FIFO (b)

FIFO (a)

FIFO (a)

FIFO (b)

FIFO (b)

FIFO (a)

FIFO (b)

FIFO (a)

FIFO (a)

PACKET N+1

ACK1

NACK

ACK2

CPU bus side

FIFO (b)

PACKET N Transmission disabled

FIFO (b)

PACKET N PACKET N+1

Transmission enabled

Writing disabled

PACKET N+1

FIFO (a)

PACKET N+1

Writing enabled

LAST PACKET

Writing enabled

Writing disabled

1)

5)

4)

2)

3)

6)

Shading indicates existence of data.

1) 2) 6)

3) 4)

5)

7)

7)

*

USB bus side

437


The operation shown in the figure is explained below.

1. Data is written from the CPU to FIFO buffer (a) for transmission.

2. When FIFO buffer (a) (64 bytes) becomes full and the transfer enable bit (BFOK) is set,transmission to the USB is started. At the same time, FIFO buffer (b) becomes visible fromthe CPU and the next send data can be written to FIFO buffer (b).

3. When data writing to FIFO buffer (b) ends, the transfer enable bit (BFOK) is set. At the sametime, FIFO buffer (a) becomes visible from the CPU. However, data writing from the CPU toFIFO buffer (a) cannot be started because data transmission from FIFO buffer (a) to the USBis not completed.If data transmission from FIFO buffer (a) ends without an error, an ACK signal (ACK1) isreturned.

4. When the ACK signal (ACK1) is returned, FIFO buffer (a) enters the write-enabled status. Thenext data is written from the CPU. FIFO buffer (b) becomes visible from the USB.Transmission to the USB is started because transmission-enabled data has already beenwritten to FIFO buffer (b).

5. When data writing to FIFO buffer (a) ends, the transfer enable bit (BFOK) is set. At the sametime, FIFO buffer (b) becomes visible from the CPU. However, data writing from the CPU toFIFO buffer (b) cannot be started because data transmission from FIFO buffer (b) to the USBis not completed.If data transmission from FIFO buffer (b) ends with an error, a NACK signal is returned.

6. If a NACK signal is returned, data is retransmitted from FIFO buffer (b) to the USB. Datawriting from the CPU to FIFO buffer (b) cannot be started because data transmission fromFIFO buffer (b) to the USB is not completed.If data retransmission from FIFO buffer (b) ends without an error, an ACK signal (ACK2) isreturned.

7. When the ACK signal (ACK2) is returned, FIFO buffer (b) enters the write-enabled status.However, no interrupt occurs until transmission of the last packet is completed.

Timing Diagram for BULK OUT Transfer (Reading by CPU and Writing by USB)

Figure 17.4-2 shows the timing diagram for double-buffer operation during BULK OUT transferand the operation diagram.

In the example below, the MNACK bit of the CONT8 register (control register) is set so that anIRQ signal is not asserted by NACK.

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Figure 17.4-2 Timing Diagram for BULK OUT Transfer (Reading by CPU and Writing by USB)

FIFO (a)

FIFO (a)

FIFO (b)

FIFO (b)

FIFO (b)

Shading indicates existence of data.

FIFO (b)

FIFO (b)

PACKET N

PACKET N+1

Reading disabled

Reading enabled

CPU bus side

FIFO (a) Reading disabled

PACKET N

Reading enabled

ACK1

NACK

ACK2

FIFO (a) Reading disabled

PACKET N+1

PACKET N+1

FIFO (a) PACKET N+1 PACKET N+2

1)

5)

4)

2)

3)

PACKET N PACKET N+1 PACKET N+1 PACKET N+2

FIFO (a)

FIFO (b)

IRQ

Reading by CPU

Writing by USB

Writing by USB

Reading by CPU

Writing by USB

Writing by USB

Reading by CPU

ACK1

NACK1 ACK2

1)

2)

3) 4) 5)

USB bus side

439


The operation shown in the figure is explained below.

1. Receive data is written from the USB to FIFO buffer (a).One packet of receive data is stored in FIFO buffer (a). If there is no error, the macro programreturns an ACK signal (ACK1).

2. When the ACK signal (ACK1) is returned, FIFO buffer (a) enters the read-enabled status andreading by the CPU is started. FIFO buffer (b) becomes visible from the USB, and writing ofthe next packet from the USB to FIFO buffer (b) is started.

3. When data reading by the CPU from FIFO buffer (a) ends, the transfer enable bit (BFOK) isset. FIFO buffer (b) becomes visible from the CPU. However, data reading by the CPU fromFIFO buffer (b) cannot be started because data writing from the USB to FIFO buffer (b) is notcompleted.One packet of receive data is stored in FIFO buffer (b). If there is an error, the macro programreturns a NACK signal.

4. If a NACK signal is returned, writing of the same packet to FIFO buffer (b) is retried again.Data reading by the CPU from FIFO buffer (b) is still disabled.If storing the packet of receive data in FIFO buffer (b) ends without an error, the macroprogram returns an ACK signal (ACK2).

5. When the ACK signal (ACK2) is returned, FIFO buffer (b) enters the read-enabled status.Data reading by the CPU from FIFO buffer (b) is started. FIFO buffer (a) becomes visible fromthe USB. Writing of the next receive packet to FIFO buffer (a) is started.

440


17.4.2 Controlling the D+ Terminating Resistor on the Board

This section describes those points related to the USB function, which must be noted when controlling connection or cutting of the on-board terminating resistor for the USB D+ signal. This control is performed to reserve the time required for the application (firmware) initialization routine.

Controlling the D+ Terminating Resister on the Board

The hub detects connection of a function device to a downstream USB port when either of thefollowing conditions is met:

• The power of a function device already connected to the USB is turned on.

• A function device whose power has already been turned on is connected to the USB.

The USB specifications require a function device to be able to accept a transaction within 100 msafter the hub has detected its connection to a USB port.

If either of the above conditions for the hub's detection of the connection of a function device to aUSB port is met, this macro program must execute a sequence to set up the end point buffer afterreset processing.

If the firmware requires 100 ms or more for the initialization routine, including reset and setup ofthe end point buffer, there is a method to defer the detection of the connection. The method is tocut the terminating resistor for the USB D+ signal to temporarily prevent the hub from detecting aport connection . When using this method, take the following precautions for the macro program:

Notes:

• Setup of the end point buffer must be started after the hardware and software are released fromthe reset status.

• Control to connect the terminating resistor must be started after end point buffer setup by thefirmware is completed.

USB D+ terminating resistor control1: Connected

Software reset(Negative logic)

Hardware reset(Negative logic)

Moment of power-on or USB connection

Period in which end point buffer setup is enabled

The hub detects connection to the USB.

The hub does not recognize a connection although the device is physically connected to the USB.

441


17.4.3 Automatic Response of Macro Program to USB Standard Request Commands

The USB function automatically responds to most USB standard request commands to reduce the load on the application program.However, the following USB standard request commands must be processed by the application program:Set_Descriptor, Get_Descriptor, and Synch_Frame commands

Automatic Response of Macro Program to USB Standard Request Commands

Table 17.4-1 lists the USB standard request commands that this macro program automaticallyresponds to and the details of the automatic responses.

The USB standard request commands conform to those supported by USB Function Ver1.1.

Table 17.4-1 USB Standard Request Commands and Details of Automatic Responses (1 / 2)

USB standard request command automatically responded to by this macro program

Details of automatic response

Data stage Status stage

CLEAR_FEATURE

Device: DEVICE_REMOTE_WAKEUP

- Returns null data

End point: ENDPOINT_STALLEnd point number supported by this macro program

- Returns null data

End point: ENDPOINT_STALLEnd point number not supported by this macro program

-Responds with STALL signal

GET_CONFIGURATIONReturns the current value of Configuration

Receives null data

GET_INTERFACE

Interface number supported by this macro program

Returns the current value of Alternate

Receives null data

Interface number not supported by this macro program

Responds with STALL signal

-

442


GET_STATUS

Device

Returns the current power supply status of the device and whether the REMOTE_WAKEUP function is enabled

Receives null data

End point:End point number supported by this macro program

Returns the current status of ENDPOINT_STALL

Receives null data

End point:End point number not supported by this macro program

Responds with STALL signal

-

SET_ADDRESS - Returns null data

SET_CONFIGURATION

Configuration number supported by this macro program

- Returns null data

Configuration number not supported by this macro program


SET_FEATURE

Device: DEVICE_REMOTE_WAKEUP

- Returns null data

End point: ENDPOINT_STALLEnd point number supported by this macro program (except end point 0)

- Returns null data

End point: ENDPOINT_STALLEnd point number not supported by this macro program or end point 0


SET_INTERFACE

Interface or Alternate number supported by this macro program

- Returns null data

Interface or Alternate number not supported by this macro program


Table 17.4-1 USB Standard Request Commands and Details of Automatic Responses (2 / 2)

USB standard request command automatically responded to by this macro program

Details of automatic response

Data stage Status stage

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17.4.4 USB Function Macro Program Operation in the Default Status

The USB function enters the default status after being released from the reset status.The USB function macro program can be set to the configuration status defined by Configuration = 1.

USB Function Macro Program Operation in the Default Status

If the device receives a Set_Configuration command with Configuration = 1 specified from theUSB host, the USB function macro program is set to the configuration status.

Only end point 0 can be used in the default status. Other end points cannot be used in thedefault status. If a transfer request to an end point other than end point 0 is received, the macroprogram does not respond to the request and time-out occurs.

All end points can be used in the configuration status.

Table 17.4-2 lists the responses of the macro program to transfer requests to end points 0 to 3 inthe default and configuration status.

Table 17.4-2 Responses of Macro Program to Transfer Requests to End Points 0 to 3 in the Default and Configuration Status

Default status Configuration status

End point 0UsableA response is made to a transfer request.

UsableA response is made to a transfer request.

End points 1 to 3

Not usableNo response is made to a transfer request, and time-out occurs.

UsableA response is made to a transfer request.

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17.4.5 USB Clock Control in the Suspended Status

The USB function asserts the SUSPEND signal when it enters the suspended status. Then, the SUSP bit of the ST3 register is set to 1.To reduce power consumption, the USB clock can be stopped by operation of the SUSPEN bit when this macro program is set to the suspended status.

Example of USB Clock Control in the Suspended Status

The following shows an example procedure for controlling the USB clock in the suspended status:

The specifications of USB Function Ver1.1 require that the USB function must be ready to receivetransfer from the host within 10 ms after the USB function has been released from the suspendedstatus.

For this reason, if the USB clock has been stopped, stable USB clock must be input to the USBfunction within 10 ms after the USB function has been released from the suspended status.

1) The macro program asserts the SUSPEND signal.

2) UCLK48 is stopped.

3) The SUSPEND signal is deasserted.

4) UCLK48 is restarted, and the 48 MHz clock is input to the USB function macro program.

5) The device waits for transfer from the host.

445


17.4.6 Detection of USB Connector Connection and Disconnection

The USB function cannot detect whether the USB connector is connected . Connection and disconnection of USB connector must be detected by the method described below.

Detection of USB Connector Connection and Disconnection

The USB function cannot use the D+ or D- signal to determine whether the USB connector isconnected.

Whether the USB connector is connected must be determined by detecting VBUS outside of themacro program.

• When the connector is connected: VBUS = 5 V

• When the connector is not connected: VBUS = 0 V

A possible method is to detect changes of VBUS on the board and generate interrupts to theMPU.

When connection of the USB connector is detected, the USB function macro program must bereset.

446


17.4.7 Accuracy of UCLK48

This section describes the accuracy of the UCLK48 clock.

Accuracy of UCLK48

USB Function Ver1.1 has two standards for D+ data and D- data signals.

A crystal oscillator module must be used as the 48 MHz clock input source of the UCLK48 clock.

If PLL is used, take special care regarding clock frequency accuracy.

Data rate standard (long-term standard)

The device (entire circuit not limited to an LSI circuit) must satisfy the following: accuracy of -2,500 ppm to +2,500 ppm (-0.25% to +0.25%).

The USB standards require an accuracy of -2,500 to +2,500 ppm for the 12 MHz clock. However,the USB function macro program requires the 48 MHz clock to have a higher accuracy than -2,500 ppm to +2,500 ppm. This is because it selects the clock edges synchronized with datafrom the clock edges of the 48 MHz clock and uses the selected clock edges as the 12 MHzclock.

For this reason, the UCLK48 clock needs a higher accuracy than -2,500 ppm to +2,500 ppm.

Short-term standard

The device (entire circuit not limited to an LSI circuit) must satisfy the following jitter requirements:

• Jitter within -1 ns to +1 ns until the first crossing point

• Jitter within -2 ns to +2 ns until the second crossing point

Accuracy within -1 ns to +1 ns from each edge of the 48 MHz clock is required because the D+and D- signals may alter at every edge.

447


17.4.8 Setting of Transfer Enable bit (BFOK) during Control Transfer

To enable the macro program to receive a command and respond to it with ACK in the setup stage of control transfer, the BFOK0o bit of the CONT3 register must be set to 1. If the BFOK0o bit is 0, the command is ignored and time-out occurs. The same condition also applies to the commands that are automatically processed by the macro program in the setup stage.

Setting of Transfer Enable (BFOK) Bits during Control Transfer

The settings of the BFOK0i and BFOK0o bits during control transfer are explained below.

For a request the macro program processes automatically

• Setup stage

The BFOK0o bit must be set to 1 to enable an ACK response.

If the BFOK0o bit is 0, a time-out occurs.

• Data stage

IN: No request is processed automatically by the macro program.

OUT: ACK response is made regardless of the setting of BFOK0o.

• Status stage

IN: ACK response is made regardless of the setting of BFOK0i.

OUT: ACK response is made regardless of the setting of BFOK0o.

For a request the macro program does not process automatically

• Setup stage

The BFOK0o bit must be set to 1 to enable an ACK response.

• Data stage

IN: The BFOK0i bit must be set to 1 to enable an ACK response.

OUT: The BFOK0o bit must be set to 1 to enable an ACK response.

• Status stage

IN: The BFOK0i bit must be set to 1 to enable an ACK response.

OUT: The BFOK0o bit must be set to 1 to enable an ACK response.

448


17.4.9 Precautions for Control Transfer

This section describes the precautions for control transfer.

Precautions for Control Transfer

Precaution 1: Priority of setting the BFOK0o bit

USB specifications allow the USB function to respond to requests with ACK only in the setupstage. If the USB function cannot make an ACK response to a request, a time-out occurs.

If a time-out occurs three times successively in the setup stage, the USB host disconnects thefunction device. For this reason, the USB function should always make an ACK response torequests.

If the status stage ends with an ACK response, the BOK0o bit is cleared to 0. To enable the USBfunction to make an ACK response in the next setup stage, the BFOK0o bit must be set to 1before the next setup stage. For this reason, the priority of setting the BFOK0o bit must be set ashigh as possible.

This requirement applies only to commands the macro program does not process automatically.Even if an ACK response is made to a command that the macro program processesautomatically, the BFOK0o bit is not cleared to 0.

Precaution 2: Cancellation of the data stage by a Get_Descriptor command

When a Get_Descriptor command, which is not automatically responded to by the macroprogram, is processed, the host may cancel the data stage in the middle. This may occur even ifthe byte count of data for IN transfer initially requested by the host is not reached. If thiscancellation occurs, the host may not receive all the data previously written to the FIFO buffer forIN transfer as follows:

If the above event occurs, data B, which has already been written to the FIFO buffer, must bediscarded and the FIFO buffer must be initialized before the next IN transfer request is received.The above event in which the host stops receiving data in the middle may be detected bydetecting a USB reset interrupt. Another possible detection method is to check the ACK interruptsources as follows:

• Data stage: The interrupt source bit (ACK0i) is set.

Setup stage (16 bytes requested)

Data stageThe CPU writes 8 bytes (data A) to the FIFO buffer for IN transfer.The host requests IN transfer. The USB function transmits 8 bytes and receives ACK.The CPU writes 8 bytes (data B) to the FIFO buffer for IN transfer.Note: The host may cancel the data stage at this point.

Status stage0-byte data is received at OUT transfer.

449


• Status stage: The interrupt source bit (ACK0o) is set.(If the data stage is continued, the ACK0i bit is set.)

Transition from the data stage to the status stage can be determined from the change of interruptsource (from the ACK0i bit to the ACK0o bit).

450


17.4.10 Macro Program Status after USB Bus Reset

This section describes the macro program status after USB bus reset.

Macro Program Status after USB Bus Reset

The register values and FIFO buffer status in the macro program are not reset even when a USBbus reset occurs. To start transfer on the USB after a USB bus reset, the registers and FIFObuffers must be reset to the initial status by the application program.

Also, the initial settings of the end point buffer are not reset by a USB bus reset. The initialsettings are retained even after a USB bus reset. Therefore, the end point buffer need not be setup again.

Note that the macro program enters the USB default status when a USB bus reset occurs.

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452

CHAPTER 18OSDC

This chapter explains the features, block diagram, display function, control function, and display control command of the on-screen display controller (OSDC).

18.1 ON-SCREEN DISPLAY CONTROLLER (OSDC)

18.2 Display Functions

18.3 Control Functions

18.4 Display Control Commands

18.5 Display Control Command (CC)

18.6 FONT RAM Interface

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CHAPTER 18 OSDC

18.1 ON-SCREEN DISPLAY CONTROLLER (OSDC)

This chapter explains the features, block diagram, display functions, control functions, and display control commands of the on-screen display controller (OSDC).

18.1.1 Features

18.1.2 Block Diagram

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CHAPTER 18 OSDC

18.1.1 Features

The on-screen display controller (OSDC) can display up to 80 characters by 32 lines at a high resolution of up to 24-by-32 dots per character. The OSDC contains a palette circuit that enables the display of 16 colors of 512 colors to be displayed.The OSDC provides sprite display, screen background text display, and graphics display functions, enabling a variety of GUI displays.

Features of the OSDC

The features of the OSDC are as follows:

Screen display capacity

Main screen: Up to 80 characters × 32 lines (Max 2560 characters)

CC screen: Up to 42 characters × 16 lines (Max 672 characters)

Font sizes

L size: 24 × 2h* dots (horizontal × vertical)

M size: 18 × 2h* dots (horizontal × vertical)

S size: 12 × 2h* dots (horizontal × vertical)

*: h = 9 to 16

The L, M, or S size can be set for each character.

Note: The character configuration in CC screen is fixed at M size.

• Two values of "h" can be set for each screen, either of which is selected for each line.

Character types

4096 different characters integrated (16 characters of 4096 characters are font RAM.)

Note: A graphic character consists of four continuous characters.

Display modes

Normal character/graphic character display* (Set for each character)

Trimmed display (horizontal trimming/pattern background) (Set for each screen)

Character background (solid-filled/shaded background*) (Set for each character)

Italic display (Set for each character)

Underline display (Set for each character)

Line background (solid-filled/shaded background*) (Set for each line)

Enlarged display (normal, double width, double height, double height × double width, quadruplewidth, quadruple height, quadruple height × quadruple width, and others) (Set for each line)

Blink display:

Blink character specification (Set for each character)

Blink mode setting (Set for each character)

Blink cycle and duty ratio (Set for each screen)

*: It is a display mode used in the main screen.

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CHAPTER 18 OSDC

Sprite character display (Only in graphics display mode)

Capable of displaying one block (of up to 2 × 2 characters, movable vertically or horizontally in 2-dot units) on the main /CC screen

Screen background character display (Only in graphics display mode)

Capable of displaying a repetitive pattern (consisting of up to 2 × 2 characters) below the main/CC screen

Only the first 256 characters (character codes 000 to 0FFH) can be set.

Display colors

Character color/background color: 16 colors of 512 colors (Set for each character)

Line background color/character trimming color: 16 colors of 512 colors (Set for each line)

Screen background color: 16 colors of 512 colors (Set for each screen)

Graphic character dot color: 16 colors of 512 colors (Set for each dot)

Shaded background frame color (highlight/shadow): 16 colors of 512 colors (Set for eachscreen)

Display position control

Horizontal display position on the main screen: Settable in 4-dot units

Vertical display position on the main screen: Settable in 2-dot units

Horizontal display position on the CC screen: Settable in 4-dot units

Vertical display position on the CC screen: Settable in 2-dot units

Horizontal display position on the sprite screen: Settable in 2-dot units

Vertical display position on the sprite screen: Settable in 2-dot units

Line spacing control: Settable in 2-dot units (Set for each line)

Character/color signal output

R[2:0], G[2:0], B[2:0]: OSD color digital output signal

ROUT, GOUT, BOUT (OSD color analog output signal) *1

VOB1 (OSD display period output signal) *2

VOB2 (OSD translucent color period output signal) *2

*1: DAC output signal. The DAC outputs R, G, and B at 8 levels each.

*2: VOB1 and VOB2 are common to digital/analog.

Interrupt functions (MAIN is connected to the external interrupt ch5, cc is connected to the external interrupt ch6)

Line display end interrupt

Vertical sync signal detection interrupt

VRAM fill end interrupt

Clock frequency

Maximum frequency: 90 MHz

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CHAPTER 18 OSDC

18.1.2 Block Diagram

This section shows the OSDC block diagram.

Block Diagram

Figure 18.1-1 shows the block diagram of the OSDC and peripheral units.

Figure 18.1-1 Block Diagram

OSDC register control signal

DAC control signal

InterruptTo CPU

PLLA control signal

PLLB control signal

PLLC control signal

Digital RGB

Display period signal

Font I/F

RAM

F-bus

DAC

PLLA

OSDCM209

CPOAVGSAVDDIA (8: For PLL)

PLLBCPOBVGSBVDDIB (8: For PLL)

PLLCCPOCVGSCVDDIC (8: For PLL)

R[2:0]G[2:0]B[2:0]VOB1VOB2DCKODOCKIFHSLYCLKASLYCLKBVSYNCHSYNCAHSYNCBHSYNCC

GOUTBOUT

VREFVROVDDR

VSSRVDDG

VSSGVDDB

VSSBROUT

FLASH

VRAM I/F

VRAM I/F

RAM

RAM

VRAM data(MAIN)

Font data(MAIN/CC)

VRAM data(CC)

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CHAPTER 18 OSDC

18.2 Display Functions

This section explains the OSDC display functions.

18.2.1 Screen Configuration

18.2.2 Screen Display Modes

18.2.3 Screen Output Control

18.2.4 Screen Display Position Control

18.2.5 Font Memory Configuration

18.2.6 Display Memory (VRAM) Configuration

18.2.7 Writing to Display Memory (VRAM)

18.2.8 Palette Configuration

18.2.9 Character Display

18.2.10 Character Background Display

18.2.11 Line Background Display

18.2.12 Screen Background Display

18.2.13 Sprite Character Display

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CHAPTER 18 OSDC

18.2.1 Screen Configuration

The display screen consists of various screen elements.

Screen Configuration

The display screen consists of the screen elements shown in Table 18.2-1.

*: The priority order of upper and lower layer for the main and CC screen can be replaced.

Table 18.2-1 Display Screen Elements

Display screen name Screen configurationDisplay position

control

Top layer

Bottom layer

Sprite character1 sprite character(consisting of 2 × 2 characters max.)

Horizontal/vertical:in 2 dots

Main screen*

Character (+ trimming)

80 characters × 32 linesHorizontal: in 2 dots/vertical: in 4 dots

Character background

80 characters × 32 lines(Character/background concurrent control)

Line background

32 lines(Character/background concurrent control)

CC screen*

Character (+ trimming)

42 characters × 16 linesHorizontal: in 2 dots/vertical: in 4 dots


42 characters × 16 lines(Character/background concurrent control)

Line background

16 lines(Character/background concurrent control)

Screen background character1 type (Repeatedly displayed pattern of 2 × 2 characters)

Fixed

Screen background(Full screen display in single color)

Fixed

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CHAPTER 18 OSDC

Screen Configuration Drawing

Figure 18.2-1 shows the screen configuration diagram (whole).

Figure 18.2-1 Screen Configuration Drawing (whole)

Note:

When a line is displayed on a line, the shaded background shadow frame for the line backgroundoverrides the character display.

The shaded background shadow frame for the character background overrides the character displayand the shaded background shadow frame for the line background.

Note: The priority order of the main / CC screen can be changed.

80 characters

123456789101112131415

293031

10

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

1

0

0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

25

27 38 39 40 41

73 74 75 76 77 78 790

23456789101112131415

Main screen

CC screen

Source video for synchronization

Screen background characters

Screen background (screen background color)

Sprit character

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CHAPTER 18 OSDC

Screen Configuration Drawing 2

Figure 18.2-2 shows the main screen configuration diagram.

Figure 18.2-2 Main Screen Configuration Drawing

Screen Configuration Drawing 2

Figure 18.2-3 shows the CC screen configuration diagram.

Figure 18.2-3 CC Screen Configuration Drawing

Note:

When a line is displayed on a line, the shaded background shadow frame for the line background overrides the character display.

Line 0

Line 1

Line 2

Line 3

Line 4

Line 5

Line 6

Line 7

Line 8

Line 9

Line 10

Line 29

Line 30

Line 31

1

2

3

4

5

6

7

8

9

10

29

30

31

1

0

0

2

3

4

5

6

7

8

9

10

29

30

31

Character + trimming

Line background (line background color)

Character background (character background color)

The shaded background shadow frame for the character background overrides the character display and the shaded background shadow frame for the line background.

Line 0

Line 1

Line 2

Line 3

Line 4

Line 5

Line 6

Line 7

Line 8

Line 9

Line 10

Line 11

Line 12

Line 13

Line 14

Line 15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1

0

0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Character + trimming

Line background (line background color)

Character background (character background color)

Note:

When a line is displayed on a line, the shaded background shadow frame for the line background overrides the character display.

The shaded background shadow frame for the character background overrides the character display and the shaded background shadow frame for the line background.

461

CHAPTER 18 OSDC

18.2.2 Screen Display Modes

This section explains the display modes of the display screen elements.

Screen Display Modes

Table 18.2-2 shows the display modes of the display screen elements.

Table 18.2-2 Screen Display Modes (1 / 2)

Display screen name Display mode

Screen backgroundUndisplay

Display

Screen background character

Undisplay

Display*: Only graphic character can be

used.Character pattern

Consisting of a single character

Consisting of 2 horizontally aligned characters

Consisting of 2 vertically stacked characters

Consisting of 2 × 2 characters

Main screen

Line back-ground

Undisplay

Line spacing 0 to 14 dots

Solid-fill display

Shaded background concaved display Shaded back-ground succeed-ing line merge

Indepen-dent

Shaded background convexed display Merge

Charac-ter back-ground

Undisplay

Solid-fill display

Character background extended (enabled with line spacing control on)

Normal

Shaded background convexed display

Shaded back-ground succeed-ing charac-ter merge

Indepen-dent Shaded

back-ground succeed-ing line merge

Indepen-dent

ExtendedShaded background convexed display Merge Merge

462

CHAPTER 18 OSDC

Main screen

Charac-ter

Graphic character

Normal charac-ter

Undisplay (blank character)

Display

Trim-ming output control

Undisplay

Trim-ming mode

Horizon-tal trim-ming 1

Trim-ming type

Undis-play

Display with no character background

Horizon-tal trim-ming 2

Right trimming

Undisplay only within shaded background

Pattern back-ground 1

Left trimming

Full displayPattern back-ground 2

Both-side trimming

Italic output control

Undisplay

Italic display

Under-line output control

Undisplay

Underline display

CC screen

Line back-ground

UndisplayLine spacing 0 to 14

dotsSolid-fill display

Charac-ter back-ground

Undisplay

Solid-fill display

Character background extended (enabled with line spacing is set other than 0)

Normal

Extended

Charac-ter

Normal charac-ter

Undisplay (blank character)

Display Same as main screen

Sprite character

Undisplay

Display*: Only graphic characters can be

used.Character attribute

Consisting of a single character

Consisting of 2 horizontally aligned characters

Consisting of 2 vertically stacked characters

Consisting of 2 × 2 characters

Table 18.2-2 Screen Display Modes (2 / 2)

Display screen name Display mode

463

CHAPTER 18 OSDC

18.2.3 Screen Output Control

This section explains the relationship between elements subject to screen output control and the control bits.

Screen Output Control

Table 18.2-3 shows the relationship between the elements subject to screen output control andthe control bits.

Table 18.2-3 Screen Output Control

Display screen control

Elements to be controlledControl bit name (unit of

control)

Character + trimming + character background + line background

DSP (screen)

Character + trimming + character background

LDS (line)

Character M8 to M0 (character)

Character trimming

LFD to LFA (line)

Character background MIT, MVL (character)

Line background LM1, LM0 (line)

Screen background character PDS (screen)

Screen background color UDS (screen)

Sprite character SDS (screen)

464

CHAPTER 18 OSDC

18.2.4 Screen Display Position Control

The OSDC can control the display positions on the main screen, CC screen, screen background characters, screen background colors, and sprite characters independently.

Display Position Control on the Main/CC Screen

The MB91319 controls the display start positions of a character (or a line of characters),character trimming, character background, and line background simultaneously.

Vertical display position: Vertical display position control (command 5-2), Bits Y8 to Y0

Set the vertical display start position relative to the VSYNC position.

The position can be set between 0 and 2046 dots in 2-dot units.

Horizontal display position: Horizontal display position control (command 5-3), Bits X8 to X0

Set the vertical display start position relative to the HSYNC position.


Line spacing: Line control data set 1 (command 3), Bits LW2 to LW0

Set the number of dots to specify the width of the areas to be kept above and below thecharacters on each line.

The spacing specified by the set value will be kept both above and below the characters.

The line spacing can be set between 0 and 14 dots in 2-dot units for each line.

(Note: When line double-height display is on, the line spacing is doubled as well.)

Figure 18.2-4 shows the display positions on the main/CC screen.

465

CHAPTER 18 OSDC

Figure 18.2-4 Display Positions on the Main/CC Screen

←VSYNC position

HSYNC position

↓ Line spacing Vertical display position

Line 0

Horizontaldisplay position

Line spacing

Line 1

Line background (horizontal) display positionLine 2

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. . .CharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacter

. . .CharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacter

. . .

. . .

CharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacter*3

*2

*1

466

CHAPTER 18 OSDC

*1: Vertical display position

Counting for the vertical display position is started 1Hsync after the sync pulse of the vertical syncsignal (VSYNC pin input signal) as shown below.

Figure 18.2-5 shows the count timing for the vertical display position on the main/CC screen.

Figure 18.2-5 Count Timing for the Vertical Display Position on the Main/CC Screen

Note: If VSYNC and HSYNC are as shown above in Figure 18.2-5, the display start positionremains unchanged due to the setting of the vertical synchronization detection HSYNCedge selection control (bit VHE) of input-output control 2 (command 13-1).

*2: Horizontal display position

The horizontal display position is the set value + several dot clocks (see "18.2.4.1 Screen DisplayPosition Offset") after the sync pulse significant edge (controlled by bit HE of command 13-1) ofthe horizontal sync signal (HSYNC pin input signal).

The calculation for the set value of horizontal display position in the main/CC screen characters isas follows.

Set value of horizontal display position = (X8, X7, X6, X5, X4, X3, X2) × 12 + (X0, X1) × 4 [dot]

Note: However, setting of (X1, X0) = (1,1) is disabled.

VSYNC

HSYNC

Display output timing

Sync signal input timing

↑Note: Display start position when vertical display start position on the main screen is set to 0

RGB (digital/analog)

VOB1,VOB2

X8 X7 X6 X5 X4 X3 X2 X1 X0Set value of horizontal display

position for main/CC characters

0 0 0 0 0 0 0 0 0 0 dot (0+0)

0 0 0 0 0 0 0 0 1 4 dots (0+4)

0 0 0 0 0 0 0 1 0 8 dots (0+8)

0 0 0 0 0 0 1 0 0 12 dots (12+0)

0 0 0 0 0 0 1 0 1 16 dots (12+4)

0 0 0 0 0 0 1 1 0 20 dots (12+8)

0 0 0 0 0 1 0 0 0 24 dots (24+0)

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1 1 1 1 1 1 1 1 0 1532 dots (1524+8)

467

CHAPTER 18 OSDC

*3: Line background display position

The horizontal display position of the line background is several dot clocks (see "18.2.4.1 ScreenDisplay Position Offset") after the horizontal sync pulse significant edge (controlled by bit HE ofcommand 13-1).

Reference:

The vertical display position of the line background is controlled by bits Y8 to Y0 of the verticaldisplay position control (command 5-2) to enable the display position to be moved concurrently withcharacters on the main screen.

Notes:

• Vertical display position control varies depending on the setting of the interlace control (bit IN) ofsynchronous control (command 11-0). (For details, see "18.3.5 Synchronization Control")

• Display output of display signal outputs (RGB, VOB1, and VOB2) are off during the specifiedperiod after input of the sync pulse of the vertical sync signal (VSYNC pin input signal) and thesync pulse of the horizontal sync signal (HSYNC pin input signal).

468

CHAPTER 18 OSDC

Display Position Control of Screen Background Characters

Figure 18.2-6 shows the display positions of screen background characters.

Figure 18.2-6 Display Positions of Screen Background Characters


The vertical display position is fixed to 1Hsync after the sync pulse of the vertical sync signal(VSYNC pin input signal) and is shown in Figure 18.2-5.


The horizontal display position is several dot clocks (see "18.2.4.1 Screen Display PositionOffset") after the sync pulse significant edge (controlled by bit HE of command 13-1) of thehorizontal sync signal (HSYNC pin input signal).

Note:

Display output of display signal outputs (RGB, VOB1, and VOB2) are off during the specified periodafter input of the sync pulse of the vertical sync signal (VSYNC pin input signal) and the sync pulseof the horizontal sync signal (HSYNC pin input signal).
















• • • •

• • • •

• • • •

• • • •

• • • •

• • • •

• • • •

• • • •

HSYNC positionVSYNC position

Horizontaldisplay position*2

Vertical display position*1

469

CHAPTER 18 OSDC

Display Position Control of Screen Background Color

Figure 18.2-7 shows the display position of the screen background color.

Figure 18.2-7 Display Position of Screen Background Color


The vertical display position is immediately after the trailing edge of the sync pulse of the verticalsync signal (VSYNC pin input signal).

Figure 18.2-8 shows the vertical display position of the screen background color.

Figure 18.2-8 Display Start Position of Screen Background Color

←VSYNC position

HSYNC position Vertical display position↓

Horizontal display position*2

*1

VSYNCHSYNC

Display output PO[15: 0], VOB output timing

Sync signal input timing

↑* Display start position of screen background color

RGB (digital/analog)VOB1,VOB2

470

CHAPTER 18 OSDC


The horizontal display position is several dot clocks (see "18.2.4.1 Screen Display PositionOffset") after the sync pulse significant edge (controlled by bit HE of command 13-1) of thehorizontal sync signal (HSYNC pin input signal).

Note:

Display output of display signal outputs (RGB, VOB1, and VOB2) are off during the specified periodafter input of the sync pulse of the vertical sync signal (VSYNC pin input signal) and the sync pulseof the horizontal sync signal (HSYNC pin input signal).

Display Position Control of Sprite Characters

The ODSC controls the display start positions of a sprite character and its trimming.

Sprite character vertical display position: Sprite character control 4 (command 9-0), Bits SY9 to SY0

Set the vertical display position relative to the sync pulse of the vertical sync signal (VSYNC pininput signal).


Sprite character horizontal display position: Sprite character control 5 (command 9-1), Bits SX10 to SX0

Set the horizontal display position relative to the sync pulse of the horizontal sync signal (HSYNCpin input signal).


Figure 18.2-9 shows the display position of sprite characters.

Figure 18.2-9 Display Position of Sprite Characters


The vertical display position reference is the same as on the main screen; it is 1H after the syncpulse signal of the vertical sync signal (VSYNC pin input signal). See Figure 18.2-5.

↓

HSYNCposition

Vertical display position*

Horizontal display position*2

←VSYNC position

1

Sprite character

471

CHAPTER 18 OSDC


The horizontal display position is several dot clocks (details are undefined) after the sync pulsesignificant edge (controlled by bit HE of command 13-1) of the horizontal sync signal (HSYNC pininput signal).

The calculation for the set value of horizontal display position in the sprite character is as follows.

Set value of horizontal display position = (SX10, SX9, SX8, SX7, SX6, SX5, SX4, SX3) × 12 + (SX2, SX1, SX0) × 2 [dot]

Notes:

• However, setting of (SX2, SX1, SX0) = (1,1,0) or (1,1,1) is prohibited.

• See "18.2.13 Sprite Character Display".

• Display output of display signal outputs (RGB, VOB1, and VOB2) are off during the specifiedperiod after input of the sync pulse of the vertical sync signal (VSYNC pin input signal) and thesync pulse of the horizontal sync signal (HSYNC pin input signal.

472

CHAPTER 18 OSDC

18.2.4.1 Screen Display Position Offset

There is a display offset for each display position of the main screen, CC screen, screen background colors, and sprite characters. Also, when the screen background character and the sprite character display is not performed, the offset value of the main screen display is allowed to reduce.

Screen Display Position Offset

The horizontal display position offset value is shown in Table 18.2-4, Table 18.2-5 and Table18.2-6.

The display position offset becomes the dot clock number from the effective edge (command 13-1controlled by the HE bit) of the horizontal synchronous signal (HSYNC pin input signal)synchronous pulse.

Also, each operation control is stopped by the PCUT bit of the screen background characteroperation control stop (command 7-1) and the SCUT bit of the sprite character operation controlstop (command 8-1), the offset value of the main screen is allowed to reduce.

• When the main/CC screen, sprite characters, and screen background characters aredisplayed concurrently the offset value is shown as follow.

• When either of the operation control for the sprite characters or the screen backgroundcharacters is stopped, the offset value is shown as follow.

Table 18.2-4 Horizontal Display Position Offset Value 1

Display screen Offset value

Sprite character 120

Main/CC screen (character) 150/84

Main/CC screen (line background) 50/50

Screen background characters 122

Screen background colors 50

Note: The unit of the offset value is the dot clock number.


Display screenOffset value

(PCUT=1)Offset value

(SCUT=1)

Sprite character 72 -

Main/CC screen (character) 102/84 102/84

Main/CC screen (line background) 50/50 50/50

Screen background characters - 74

Screen background colors 50 50


473

CHAPTER 18 OSDC

Notes:

• When the screen background character operation control is stopped (PCUT=1), setting the PDSof the screen output control 1 (command 5-0) to 0, and do not perform the screen backgroundcharacter display.

• When the sprite character operation control is stopped (SCUT=1), setting the SDS bit of thescreen output control 1 (command 5-00) to "0", and do not perform the screen backgroundcharacter display.

• When the main/CC screen are displayed, the offset value is shown as follow.

Notes:

• When the screen background character operation control is stopped (PCUT=1), setting the PDSof the screen output control 1 (command 5-0) to 0, and do not perform the screen backgroundcharacter display.

• When the sprite character operation control is stopped (SCUT=1), setting the SDS bit of thescreen output control 1 (command 5-00) to "0", and do not perform the screen backgroundcharacter display.


Display screen Offset value

Sprite character -

Main/CC screen (character) 69/87

Main/CC screen (line background) 50/50

Screen background characters -

Screen background colors 50


474

CHAPTER 18 OSDC

18.2.5 Font Memory Configuration

The font memory has a capacity of 4096 characters of 24 × 32 dots each.• The user can set any of the 4096 characters.

Note:A blank character is not reserved. Set a blank character in any character code if necessary.

• Any graphic character/normal character can be set.(However, a graphic character uses the same amount of data as four normal characters.)

Font Memory Configuration

Figure 18.2-10 shows the font memory configuration.

Figure 18.2-10 Font Memory Configuration

Note: Address 0FF0H to 0FFFH is for font RAM.

Font ROM configuration

24 dots

32 dots

(Character configuration example)

0000H (User area)

0001H (User area)

0002H (User area)

077FH (User area)

0880H (User area)

0881H (User area)

0FFDH (User area)

0FFEH (User area)

0FFFH (User area)

Character code

475

CHAPTER 18 OSDC

18.2.6 Display Memory (VRAM) Configuration

The display memory (VRAM) consists of the character RAM for setting individual characters and the line RAM for setting individual lines. (Each of main and CC screen consists of VRAM individually.)• Character RAM: Main [80 characters × 32 lines (2560 characters in total)] and

CC [42 characters × 16 lines (672 characters in total)]• Line RAM: Main [32 lines] and CC [16 lines]

Display Memory and Display Screen

Areas of character RAM and those of line RAM correspond to displayed characters and lines on aone-to-one basis, respectively.

Figure 18.2-11 shows the display memory configuration.

Figure 18.2-11 Display Memory Configuration

Main Column addresses

Main Row addresses

Main Character RAM Main Line RAM

CC Column addresses

CC Row addresses

CC Character RAM CC Line RAM

1

0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 75 76 77 78 79

2

3

4

5

6

26

27

28

29

30

31

1

0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 37 38 39 40 41

2

3

4

5

6

10

11

12

13

14

15

476

CHAPTER 18 OSDC

18.2.7 Writing to Display Memory (VRAM)

The OSDC command is set at OSDC control addresses 00H to 08H for writing to display

memory.• Writing a single character to character RAM• Writing multiple characters to character RAM collectively• Writing to line RAM

Writing to Display Memory

The OSDC command is issued to OSDC control addresses 00H to 08H for writing to displaymemory.

Writing a Single Character to Character RAM

Use the following commands to write data on an arbitrary character to an arbitrary address incharacter RAM:

Figure 18.2-12 shows the procedure for writing to character RAM.

Figure 18.2-12 Procedure for Writing to Character RAM

*1: When writing to consecutive addresses continuously, you can omit this command for the lattercharacter RAM write.

*2: You can also omit this command if the current character data is the same as the one set by thepreceding "character data set 1" command.

*1

VRAM write address set (Command 0) Set the row and column addresses

*2

Character data set 1 (Command 1)

Write the character data to character RAM. The VRAM write address is then incremented.


477

CHAPTER 18 OSDC

Writing Multiple Characters Collectively (VRAM Fill)

Use the following commands to write data on an arbitrary character to an area of character RAMfrom an arbitrary address to the last address, filling the area with that data:

Figure 18.2-13 shows the procedure for writing multiple characters collectively to character RAM(VRAM fill).

Figure 18.2-13 Procedure for Writing Multiple Characters Collectively to Character RAM (VRAM Fill)

*3: When VRAM fill ends, the cause of VRAM fill end interrupt is set.

The VRAM fill execution time depends on the dot clock frequency. The reference value for VRAMfill of an entire screen is as follows:

Dot clock 90 MHz: Main: about 0.4 ms and CC: about 0.1 ms

During execution of VRAM fill, commands 1 to 4 cannot be issued.

Issuing command 0 (FL =0) during execution of VRAM fill aborts the VRAM fill.

To set a VRAM write address after VRAM fill has aborted, reissue command 0.

VRAM write address set (Command 0) Set the row and column addressesand specify "VRAM fill."


The character RAM write executesVRAM fill.Character data set 2 (Command 2) *3

478

CHAPTER 18 OSDC

Writing to Line RAM

Use the following commands to write data on an arbitrary line to an arbitrary address in line RAM:

Figure 18.2-14 shows the procedure for writing to line RAM.

Figure 18.2-14 Procedure for Writing to Line RAM

*4: The line RAM fill function is not available. (It is prohibited to specify file.)

*5: You can omit this command if the current line control data is the same as the one set by thepreceding "line control data set 1" command.

*6: Any line RAM write does not increment the VRAM write address. You must therefore set a lineaddress for each line.

*4

VRAM write address set (Command 0) Set the row address.

*5

*6

Line control data set 1(Command 3)

Line control data set 2 (Command 4) Write the line data to line RAM.(The VRAM write address remainsunchanged.)

479

CHAPTER 18 OSDC

18.2.8 Palette Configuration

The palette converts the 4-bit color code output by the OSDC to a 9-bit color code.

Palette RAM Configuration

The palette converts the 4-bit color code to be set in the OSDC to the 3-bit color codes for theRGB signal.

Figure 18.2-15 shows the correspondence between palette-set addresses and OSDC-set colorcodes.

Figure 18.2-15 Palette Configuration

*: OSDC-set color codes refer to the following settings:

Character (MC3 to MC0), character background color (MB3 to MB0), trimming color (LF3 to LF0),line background color (L3 to L0), shaded background frame color (BH3 to BH0, BS3 to BS0),graphic color control (GF3 to GF0, GC3 to GC0), screen background color (U3 to U0), andgraphic character color are displayed.

3CH 3EH 40 H

5AH

42 H

44 H

46 H

48 H

4AH

4CH

4EH

50 H

52 H

54H

56H

58H

Red (3 bits) Green (3 bits) Blue (3 bits)

OSDC control palette write address

Palette configuration

(9 bits)

[10:8]

: : :

: : :

: : :

: : :

: : :

: : :

: : :

: : :

: : :

: : :: : :

: : :

: : :

: : :

: : :

0H

1H

2H

FH

3 H

4 H

5H

6H

7H

8H

9H

A H

B H

CH

DH

E H

OSDC read palette address = OSDC-set color code

Bit [6:4] [2:0]

480

CHAPTER 18 OSDC

18.2.9 Character Display

The vertical and horizontal sizes of each character to be displayed can be set.Each character is displayed by clipping the specified size of the specified character data from the font memory, starting at the upper leftmost dot.

Character Horizontal Size Control (Setting for Each Character)

Table 18.2-7 shows the character horizontal sizes of character data set 1 (command 1): Bits MS1and MS0.

Line Character Vertical Size Type Control (Setting for Each Line)

Table 18.2-8 shows the line character vertical size types of line control data set 1 (command 3):Bit LHS.

Table 18.2-7 Character Horizontal Size Control

MS1 MS0 Character horizontal size

0 0 S size: 12 dots

0 1 M size: 18 dots

1 0 L size: 24 dots

1 1 (Setting prohibited)

Table 18.2-8 Line Character Vertical Size Type Control

LHS Line character vertical size type

0 Character vertical size A

1 Character vertical size B

481

CHAPTER 18 OSDC

Character Vertical Size A/B

Table 18.2-9 shows the character vertical sizes A and B of character vertical size control(command 6-0): Bits HA2 to HA0/HB2 to HB0.

Display Examples

A character stored in the font ROM

Figure 18.2-16 shows an example of displaying a character stored in the font memory.

Figure 18.2-16 Example of Displaying a Character Stored in the Font ROM

Table 18.2-9 Character Vertical Sizes A and B

HA2/HB2 HA1/HB1 HA0/HB0 Character vertical size A/B

0 0 0 18 dots

0 0 1 20 dots

0 1 0 22 dots

0 1 1 24 dots

1 0 0 26 dots

1 0 1 28 dots

1 1 0 30 dots

1 1 1 32 dots

24 dots

32 dots

482

CHAPTER 18 OSDC

Display example 1 (vertical character size = 32 dots)

Figure 18.2-17 shows an example of displaying a character with vertical size = 32 dots.

Figure 18.2-17 Example of Displaying a Character With Vertical Size = 32 Dots

Display example 2 (vertical character size = 22 dots)

Figure 18.2-18 shows an example of displaying a character with vertical size = 22 dots.

Figure 18.2-18 Example of Displaying a Character with Vertical Size = 22 Dots

24 dots 18 dots 12 dots 18 dots

32 dots

L size M size S size M size

24 dots 18 dots 12 dots 18 dots

22 dots

L size M size S size M size

483

CHAPTER 18 OSDC

Applied Display Examples

Example of displaying characters all in the L size

Figure 18.2-19 shows an example of displaying all characters in L size.

Figure 18.2-19 Example of Displaying All Characters in L Size

Example of displaying characters in the L, M, and S sizes

Figure 18.2-20 shows an example of displaying characters in L, M, and S sizes.

Figure 18.2-20 Example of Displaying Characters in L, M, and S Sizes

Example of displaying characters in L/M/S vertical sizes

Figure 18.2-21 shows an example of displaying characters in L/M/S vertical sizes.

Figure 18.2-21 Example of Displaying Characters in L/M/S Vertical Sizes

32 dots

L L L L L L (←Size)

32 dots

L M M S S M (←Size)

18 dots

32 dots

32 dots

18 dots

484

CHAPTER 18 OSDC

18.2.9.1 Character Colors

Character colors can be selected from among 16 colors and set for each character.

Character Colors (setting for Each Character, Selected from among 16 Colors)

Character colors can be set for each character by setting color codes in bits MC3 to MC0 ofcharacter data set 1 (command 1).

Note:

If OSDC display color output control (DCX) is set to 0, the set color code is used. If DCX is set to 1,the color code with the bit inverted from 0 to 1 or vice versa becomes the palette read address.

485

CHAPTER 18 OSDC

18.2.9.2 Italic Display

The italic display function displays character dots tilted. Italic display can be set for each character.

Italic Display Control

The italic attribute can be set for each character by setting bit MIT of character data set 1(command 1).

Italic Display Rules

• A nonitalic character following an italic character is displayed in italics ((1) in Figure 18.2-22).

• If italic character dots protrude from a nonitalic character displayed in italics by italic display tothe subsequent nonitalic character, the protruded dots are not displayed ((2) in Figure 18.2-22).

• The dot colors that protrude because of italic display depend on the color setting of theprotruding character area ((3) in Figure 18.2-22).

• If an italic character has a right frame of shaded character background display, the protrudeddots of the italic character are not displayed ((4) in Figure 18.2-22).

• Italic display is disabled for character attributes, character colors, character backgroundcolors, graphic characters, underlines, and shaded character backgrounds.

Table 18.2-10 Italic Character Control (Setting for Each Character)

MIT Italic character control

0 Normal character

1 Italic character

486

CHAPTER 18 OSDC

Display Example

Figure 18.2-22 shows examples of displaying italic characters.

Figure 18.2-22 Example of Displaying Italic Characters

Example of displaying italic characters




*MM: Character background control (command 1)*MR: Shaded background succeeding character merge control (command 2)

MIT=1MM=10MR=1

MIT=0MM=11MR=0

MIT=0

MIT=0 MIT=0 MIT=0

MIT=1MM=10MR=0

MIT=0MM=01MR=0

MIT=1

MIT=1 MIT=0 MIT=0

MIT=1 MIT=0 MIT=0


(4)

(3)

(1) (2)

487

CHAPTER 18 OSDC

Origin of Italic Character

The tilt origin of an italic character is at the lower left of 5th dots from the least significant dots.

Figure 18.2-23 and Figure 18.2-24 show the italic state.

Figure 18.2-23 Italic State in Which 32 Vertical Dots are Displayed

Figure 18.2-24 Italic State in Which 26 Vertical Dots are Displayed

Note:

The tilt origin of italic character display is at the lower left of 5th dots from the least significant dots.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

0

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488

CHAPTER 18 OSDC

18.2.9.3 Underline Display

The underline display function displays a horizontal line under a character. Underline display can be set for each character.

Underline Display Control

The underline attribute can be set for each character by setting bit MUL of character data set 1(command 1).

Underline Display Rule

An underline is dependent on character vertical size control and is displayed on the third andfourth dots from the bottom dot.

Display Example

Figure 18.2-25 shows an example of displaying an underline.

Figure 18.2-25 Example of Displaying an Underline

Table 18.2-11 Underline Control (Setting for Each Character)

MUL Underline control

0 Normal character

1 Underline display

489

CHAPTER 18 OSDC

18.2.9.4 Character Trimming

Horizontal synchronous operation can be synchronized with the leading edge or trailing edge.

Trimming Output Control

Trimming output control turns on or off the trimming of characters according to their characterbackground type.

One of the four character background types can be set for each line.

Table 18.2-12 shows the trimming output control of line control data set 1 (command 3): Bits LFDand LFC.

x: Off*O: On*: The display is "no pattern background" in pattern background 1 or 2 mode.

Table 18.2-12 Trimming Output Control (Setting for Each Line)

Trimming output control (Setting for

each line)

Character background type (Setting for each character) Trimming

output

LFD LFC MM1 MM0 Background display

0 0

0 0 Undisplay x

0 1 Solid background x

1 0 Concaved, shaded background x

1 1 Convexed, shaded background x

0 1

0 0 Undisplay O

0 1 Solid background x



1 0

0 0 Undisplay O

0 1 Solid background O



1 1

0 0 Undisplay O

0 1 Solid background O

1 0 Concaved, shaded background O

1 1 Convexed, shaded background O

490

CHAPTER 18 OSDC

Trimming Type Control

Trimming display is controlled by selecting the combination of one of the four trimming types setfor each screen and one of the four trimming outputs set for each line.

Trimming type control (Setting for each screen)

Trimming type control for each screen ensures that four types of display format, for example,horizontal trimming and pattern background, can be selected and used.

Pattern backgrounds 1 and 2 enable the representation of virtual trimming that cannot berepresented by 1-dot and 2-dot horizontal trimming. However, font data must be designed forpattern backgrounds 1 and 2. Displaying this font data in another format (e.g., 1-dot trimming)may distort the display shape.

Table 18.2-13 shows the trimming type control of screen output control 2 (command 5-1): BitsFM1 and FM0.

1-dot horizontal trimming

A character dot (original data) is displayed with 1-dot trimming added to the right and leftends* of the character dot.

2-dot horizontal trimming

A character dot (original data) is displayed with 2-dot trimming added to the right and leftends* of the character dot.

Pattern background 1

If font data 1 continues for two bits or more in the horizontal direction, the character dots forthe number of continuous bit 1s are displayed with a 1-dot pattern background added to theright and left ends (*1) of the character dots.

Pattern background 2

If font data 1 continues for two bits or more in the horizontal direction, the character dots forthe number of continuous bit 1s are displayed with a 2-dot pattern background added to theright and left ends* of the character dots.

*: Control by bits LFB and LFA turns off display of horizontal trimming and pattern backgroundand displays horizontal trimming and pattern background at the left or right end of a characterdot.

Table 18.2-13 Trimming Type Control (Setting for Each Screen)

Trimming type controlTrimming type

FM1 FM0

0 0 1-dot horizontal trimming

0 1 2-dot horizontal trimming

1 0 Pattern background 1

1 1 Pattern background 2

491

CHAPTER 18 OSDC

Trimming control (Setting for each line)

Trimming control for each line allows specification of whether a trimming dot is displayed on theright, left, or left and right.

Table 18.2-14 shows the trimming control of line control data set 1 (command 3): Bits LFB andLFA.

Table 18.2-14 Trimming Control (Setting for Each Line)

Trimming controlTrimming output

LFB LFA

0 0 Undisplay

0 1 Right trimming

1 0 Left trimming

1 1 Both-side trimming

492

CHAPTER 18 OSDC

Display Example

• Display example of single-dot horizontal trimming (FM1, FM0 = 0, 0) Figure 18.2-26 shows a display example of single-dot horizontal trimming (FM1, FM0 = 0, 0).

Figure 18.2-26 Display Example of Single-Dot Horizontal Trimming (FM1, FM0 = 0, 0)

Font ROM (original image data) No trimming (LFB, LFA = 0, 0)

Display

Right trimming(LFB, LFA = 0, 1)

Left trimming(LFB, LFA = 1, 0)

Both-side trimming(LFB, LFA = 1, 1)

493

CHAPTER 18 OSDC

• Display example of double-dot horizontal trimming (FM1, FM0 = 0, 1) Figure 18.2-27 shows a display example of double-dot horizontal trimming (FM1, FM0 = 0, 1).

Figure 18.2-27 Display Example of Double-dot Horizontal Trimming (FM1, FM0 = 0, 1)


DIsplay

Right trimming(LFB, LFA = 0, 1)



494

CHAPTER 18 OSDC

• Display example of pattern background 1 (FM1, FM0 = 1, 0) Figure 18.2-28 shows a display example of pattern background 1 (FM1, FM = 1, 0)

Figure 18.2-28 Display Example of Pattern Background 1 (FM1, FM = 1, 0)


Display

Right trimming(LGB, LFA = 0, 1)



495

CHAPTER 18 OSDC

• Display example of pattern background 2 (FM1, FM0 = 1, 1) Figure 18.2-29 shows a display example of pattern background 2 (FM1, FM0 = 1, 1)

Figure 18.2-29 Display Example of Pattern Background 2 (FM1, FM0 = 1, 1)


Display

Right trimming(LGB, LFA = 0, 1)



496

CHAPTER 18 OSDC

Trimming Colors

Trimming colors can be set for each line by setting color codes in bits LF3 to LF0 of line controldata set 1 (command 3).

Trimming Display Rules

• Trimming dots for a character can be displayed in the right-side or left-side adjacent characterarea only when the character background types of the two characters are the same.

• Trimming dots for the character at the left or right end of a line can be displayed beyond thecharacter area only when the character background type is "no character background."

• Trimming dots on a line are also enlarged when the line is displayed enlarged (if bits LG1 andLG0 of line control data set 2 [command 4] are set to other than 0, 0).

Note:


497

CHAPTER 18 OSDC

18.2.9.5 Line Enlarged Display

Line enlarged display control controls the display size of each line including the characters, character backgrounds, and line background on that line (as well as the line spacing portions). Line enlarged display can be set in the vertical or horizontal direction or in both directions.This also controls enlargement of the shadow frames of shaded backgrounds and trimming dots. Note that the lines following the line for which line enlarged display has been specified are shifted down accordingly.

Line Enlargement Control (Setting for Each Line)

Table 18.2-15 and Table 18.2-16 show the line enlarged control of line control data set 2(command 4): Bits LGX1, LGX0, LGY1, and LGY0.

Table 18.2-15 Line Enlarged Control (Setting for Each Line)

LGY1 LGY0 Display size

0 0 Normal size

0 1 Double-height size


1 1 Quadruple-height size

Table 18.2-16 Line Enlarged Control (Setting for Each Line)

LGX1 LGX0 Display size

0 0 Normal size

0 1 Double-width size


1 1 Quadruple-width size

498

CHAPTER 18 OSDC

Line Enlarged Display Examples

Figure 18.2-30 to Figure 18.2-32 show examples of line enlarged display in normal, double-width,quadruple-width, double-height, quadruple-height, double-width/height, and quadruple-width/height sizes.

Figure 18.2-30 Example of Line Enlarged Display

Line spacing

Line spacing

Character Character Character Character Character Character Character CharacterDisplayedline

Normal size

Line spacing

Line spacing

Character Character Character CharacterDisplayedline

Double-width size

Line spacing

Line spacing

Character CharacterDisplayedline

Quadruple-width size

499

CHAPTER 18 OSDC


Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

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er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

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er

Displayedline

Line spacing

Line spacing

Double-height size

Line spacing

Line spacing

Displayedline

Cha

ract

er

Cha

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er

Cha

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er

Cha

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er

Cha

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er

Cha

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Cha

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Cha

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er

Quadruple-height size

500

CHAPTER 18 OSDC


Line spacing

Line spacing

Character Character Character CharacterDisplayedline

Double-width/height size

Line spacing

Line spacing

Displayedline

Character Character

Double-height/quadruple-width size

501

CHAPTER 18 OSDC

18.2.9.6 Graphic Character Control

The graphic character display function displays 24 × 32 dots graphic characters in 16 colors based on the 4-character dot patterns set in the font RAM. Graphic characters can be displayed in 16 colors dot by dot.

Character/graphic Character Control (Setting for Each Character)

A graphic character uses four continuous characters in the font RAM. To execute graphiccharacter display, set the two rightmost bits to 0.

Table 18.2-17 shows the character code settings.

Note:

To create a graphic character, use the OSDC pattern editor (PED/WIN) that supports the graphiccharacter.

Table 18.2-18 and Figure 18.2-33 show the character/graphic character control of character dataset 2 (command 2): Bit MG.

Table 18.2-17 Specified Graphic Character Codes

Display layer

Character code

Arbitrarily set bitFixed bit

Set 0.

Main screen M11-M2 M1, M0


PM11-PM2 PM1, PM0

Sprite SM11-SM2 SM1, SM0

Table 18.2-18 Character/Graphic Character Control (Setting for Each Character)

MG Character/graphic character control

0 Normal character

1 Graphic character

502

CHAPTER 18 OSDC

Figure 18.2-33 Character/Graphic Character Control (Setting for Each Character)

Graphic display example

(MG = 1)

(MM1 = 1, MM0 = 1) (MM1 = 1, MM0 = 0)

*: Shaded background display is enabled even for graphic display.

503

CHAPTER 18 OSDC

Graphic Color/Trimming Color Replace Control (Setting for Each Screen)

Table 18.2-19 shows the graphic color/trimming color replace control of graphic color control(command 6-3): Bit GF.

This control replaces any color (color specified in bits GF3 to GF0) in a graphic character by thetrimming color (bits LF3 to LF0) set by line control data set 1 (command 3).

Code of the Color to be Replaced by the Trimming Color (Setting for Each Screen)

Figure 18.2-34 shows an example of color replacement of graphic color control (command 6-3):Bits GF3 to GF0.

Figure 18.2-34 Example of Replacing Code of the Color to be Replaced by the Trimming Color (Setting for Each Screen)

Table 18.2-19 Graphic Color/Trimming Color Replace Control (Setting for Each Screen)

GF Graphic color/trimming color replace control

0 The specified color is not replaced.

1 The specified color is replaced by the trimming color.

[Displayed according to color information in the font RAM]

[Displayed in the specified replacing color]

GF3 to GF0:Specified colorto be replaced

Trimming color:

(Specified by bits LF3 to LF0 in command 3)

Replaced by thetrimming color

GFC=1

GFC=0

504

CHAPTER 18 OSDC

Notes:

• When graphic color/trimming color replace control is on (bit GFC is set to 1), transparent colorcontrol is on (bit TCC of transparent color control [command 6-2] is set to 1), and the color to bereplaced by the graphic color/trimming color and transparent color (bits TC3 to TC0) oftransparent color control (command 6-2) are the same, priority is given to replacement bytrimming color.

• When graphic color/trimming color replace control is on (bit GFC is set to 1), transparent colorcontrol is on (bit TCC of transparent color control [command 6-2] is set to 1), and the trimmingcolor (bits LF3 to LF0) of line control data set 1 (command 3) and the transparent color (bits TC3to TC0) of transparent color control (command 6-2) are the same, priority is given to thetransparent color and the lower-layer color is displayed.

• When graphic color/character color replace control is on (bit GCC is set to 1) and graphic color/trimming color replace control is on (bit GFC is set to 1), set the difference colors for the colorreplaced by the character color (bits GC3 to GC0) and the color replaced by the trimming color(bits GF3 to GF0).

Graphic Color/Character Color Replace Control (Setting for Each Screen)

Table 18.2-20 shows the graphic color/character color replace control of graphic color control(command 6-3): Bit GCC.

This control replaces any color (color specified in bits GC3 to GC0) in a graphic character by thecharacter color (bits MC3 to MC0) set by character data set 1 (command 1).

Table 18.2-20 Graphic Color/Character Color Replace Control (Setting for Each Screen)

GCC Graphic color/character color replace control

0 The specified color is not replaced.

1 The specified color is replaced by the character color.

505

CHAPTER 18 OSDC

Color to be Replaced by the Character Color (Setting for Each Screen)

Figure 18.2-35 shows an example color replacement of graphic color control (command 6-3): BitsGC3 to GC0.

Figure 18.2-35 Example Replacement of the Code of the Color to be Replaced by the Character Color (Setting for Each Screen)

Notes:

• When graphic color/character color replace control is on (bit GCC is set to 1), transparent colorcontrol is on (bit TCC of transparent color control [command 6-2] is set to 1), and the color to bereplaced by the graphic color/character color and transparent color (bits TC3 to TC0) oftransparent color control (command 6-2) are the same, priority is given to replacement bycharacter color.

• When graphic color/character color replace control is on (bit GCC is set to 1), transparent colorcontrol is on (bit TCC of transparent color control [command 6-2] is set to 1), and the charactercolor (bits MC3 to MC0) of character data set 1 (command 1) and the transparent color (bits TC3to TC0) of transparent color control (command 6-2) are the same, priority is given to thetransparent color and the lower-layer color is displayed.

• When graphic color/character color replace control is on (bit GCC is set to 1) and graphic color/trimming color replace control is on (bit GFC is set to 1), set the difference colors for the colorreplaced by the character color (bits GC3 to GC0) and the color replaced by the trimming color(bits GF3 to GF0).

[Displayed according to color information in the font RAM]

[Displayed in the specified replacing color]

GF3 to GF0:Specified colorto be replaced

Trimming color:

(Specified by bits MC3 to MC0 in command 1)

GCC = 1

GCC = 0

Replaced by the character color

506

CHAPTER 18 OSDC

18.2.9.7 Blink Control

The OSDC can turn blinking of each character on or off. The blink cycle and duty ratio can also be set.

Blink Control (Setting for Each Character)

Table 18.2-21 shows the blink control of character data set 2 (command 2): Bits MBL and MBB.

Display Format

Figure 18.2-36 to Figure 18.2-41 show examples of a blinking character in different backgroundcolors.

Table 18.2-21 Blink Control (Setting for Each Character)

MBL MBB Blink control

0 0 Blink OFF (normal display)

1 0 Character blink ON

0 1 Character background blink ON

1 1Character + character background blink ON

507

CHAPTER 18 OSDC

Figure 18.2-36 Example of a Blinking Character with No Background (MM1, MM0 = 0, 0)

Figure 18.2-37 Example 1 of a Blinking Character with a Solid-Filled Background (MM1, MM0 = 0, 1)


MBL=1 MBB=0

[The solid-filled background remains

displayed during blinking when MBB = 0]

MBL=1 MBB=0

MBL=0 MBB=1

508

CHAPTER 18 OSDC


Figure 18.2-40 Example of a Blinking Character with a Shaded Background (MM1, MM0 = 1, 1)

Figure 18.2-41 Example of a Blinking Graphic with No Background (MM1, MM0 = 0, 0)

MBL=1MBB=0

[The solid-filled background is not displayed during blinking when MBB = 1]

[A shaded background also remains

displayed during blinking]

MBL=1 MBB=0

MBL=1 MBB=0

509

CHAPTER 18 OSDC

Blink Cycle

Table 18.2-22 shows the blink cycles of screen output control 2 (command 5-1): Bits BT1 andBT0.

Blink Duty Ratio

Table 18.2-23 shows the blink duty ratio control of screen output control 2 (command 5-1): BitsBD1 and BD0.

Table 18.2-22 Blink Cycle Control (Setting for Each Screen)

BT1 BT0 Blink cycle

0 0 16 × VSYNC

0 1 32 × VSYNC

1 0 48 × VSYNC

1 1 64 × VSYNC

Table 18.2-23 Blink Duty Ratio Control (Setting for Each Screen)

BD1 BD0 (On:Off) Blink duty ratio

0 0 1:0 (Always on)

0 1 1:1

1 0 1:3

1 1 3:1

510

CHAPTER 18 OSDC

18.2.9.8 Transparent/Translucent Color Control

Transparent/translucent color control allows display of the color on the lower layer than any display color. Translucent color control outputs the translucent display period to allow translucent color processing to be executed externally.

Transparent Color Control (Setting for Each Screen)

Table 18.2-24 shows the transparent color control using [command 6-2]: Bit TCC.

Figure 18.2-42 shows an example of setting a transparent color using transparent color control(command 6-2): Bits TC3 to TC0 (if the areas with the darkest color shown below are set as atransparent color).

Table 18.2-24 Transparent Color Control (Setting for Each Screen)

TCC Transparent color control

0 Disable transparent color control.

1 Enable transparent color control.

511

CHAPTER 18 OSDC

Figure 18.2-42 Example of Setting a Translucent Color

[Specified transparent color]


Main screen

Sprite character

(Specified transparent color) ↑ TCC=0↓ TCC=1 TC3-TC0:

Screen background color(or original video screen)

512

CHAPTER 18 OSDC

Translucent Color Control (Setting for Each Screen)

Table 18.2-25 shows the translucent color control (command 6-2): Bit HCC.

Figure 18.2-43 shows an example of setting a translucent color using translucent color control(command 6-2): Bits HC3 to HC0.

Table 18.2-25 Translucent Color Control (Setting for Each Screen)

HCC Translucent color control

0 Disable translucent color control.

1 Enable translucent color control.

513

CHAPTER 18 OSDC

Figure 18.2-43 Example of Setting a Translucent Color

[Specified translucent color]

Screen background color(or original video screen)


Main screen character


Sprite character

Example of VOB2 pin outputfor this raster line

VOB2

(Specified translucent color) ↑ HCC=0HCC=1 HC3-HC0:

514

CHAPTER 18 OSDC

18.2.10 Character Background Display

Four character background types and 16 character background colors can be set for each character.

Character Background Control (Setting for Each Character)

Table 18.2-26 shows the character background control of character data set 1 (command 1): BitsMM1 and MM0.

Shaded Background Highlight Color (Setting for Each Screen, Selected from Among 16 Colors)

Shaded background highlight colors can be set by setting color codes in bits BH3 to BH0 ofshaded background frame color control (command 6-1).

Shaded Background Shadow Color (Setting for Each Screen, Selected from Among 16 Colors)

Shaded background shadow colors can be set by setting color codes in bits BS3 to BS0 ofshaded background frame color control (command 6-1).

Character Background Color (Setting for Each Screen, Selected from Among 16 Colors)

Character background colors can be set by setting color codes in bits MB3 to MB0 of characterdata set 1 (command 1).

Note:


Table 18.2-26 Character Background Control (Setting for Each Character)

MM1 MM0 Character background

0 0 No background (undisplay)

0 1 Solid-filled background

1 0 Concaved, shaded background

1 1 Convexed, shaded background

515

CHAPTER 18 OSDC

Display Examples

Figure 18.2-44 shows examples at each background control display.

Figure 18.2-44 Example of Character Background Display

(1) No background (2) Solid-filled background

Screenbackground coloror synchronizationsource video

Character display

(3) Concaved, shaded background (4) Convexed, shaded background

Shaded backgroundshadow color

Shaded backgroundhighlight color

Shaded backgroundhighlight color

Shaded backgroundshadow color

Characterbackground color



[The shaded background frame fora character is displayed inside the circumference of the character area.]

516

CHAPTER 18 OSDC

18.2.10.1 Shaded Background Succeeding Character Merge Display

Specifying "shaded background succeeding character merge display" for a character undisplays the right line of the shadow frame of the character and the left line of the shadow frame of the next character. This enables two or more characters with shaded backgrounds to be joined horizontally.

Shaded Background Succeeding Character Merge Control (Setting for Each Character)

Table 18.2-27 shows the shaded background succeeding character merge control of characterdata set 2 (command 2): Bit MR.

Table 18.2-27 Shaded Background Succeeding Character Merge Control (Setting for Each Character)

MRShaded background succeeding character

merge control

0 OFF

1 ON

517

CHAPTER 18 OSDC

Display Examples

Independent characters with shaded backgrounds

Figure 18.2-45 shows display examples of independent characters with shaded backgrounds.

Figure 18.2-45 Display Examples of Independent Characters with Shaded Backgrounds

Display examples of merged characters with shaded backgrounds

Figure 18.2-46 shows display examples of merged characters with shaded backgrounds.

Figure 18.2-46 Display Examples of Merged Characters with Shaded Backgrounds

(Succeeding charactermerge = OFF)

(Suceeding charactermerge = OFF)

(Succeding charactermerge = OFF)

(Succeeding charactermerge = ON)



518

CHAPTER 18 OSDC

18.2.10.2 Shaded Background Succeeding Line Merge Display (Character Background)

Specifying both of "shaded background succeeding line merge display" and "character background extended display" for a line undisplays the lower lines of the shadow frames of the characters on that line and the upper lines of the shadow frames of the characters on the next line. (Shaded background succeeding line merge display and character background extended display must both be executed for the current line, and character background extended display must be executed for the next line.)This enables two or more lines of characters with shaded backgrounds to be joined vertically.

Shaded Background Succeeding Line Merge Control (Setting for Each Line)

Table 18.2-28 shows the shaded background succeeding line merge control of line control dataset 2 (command 4): Bit LD.

Table 18.2-28 Shaded Background Succeeding Line Merge Control (Setting for Each Line)

LDShaded background succeeding line

merge control

0 OFF

1 ON

519

CHAPTER 18 OSDC

Display Examples

Figure 18.2-47 shows display examples of merged lines of characters with shaded backgrounds.

Figure 18.2-47 Display Examples of Merged Lines of Characters with Shaded Backgrounds

Note:

If character background extended display is not specified, shaded background succeeding linemerge display is disabled for character backgrounds. (Shaded background succeeding line mergedisplay is enabled for line backgrounds.)

Suceeding linemerge = ONand Extended display= ON

Succeeding linemerge = OFFandExtended display= ON




520

CHAPTER 18 OSDC

18.2.10.3 Character Background Extended Display

Character background extended display extends character backgrounds to line spacing portions.(Note that this setting is required to apply shaded background succeeding line merge display to character backgrounds.)

Character Background Extended Display (Setting for Each Line)

Table 18.2-29 shows the character background extended display of line control data set 2(command 4): Bit LE.

Table 18.2-29 Character Background Extended Display (Setting for Each Line)

LE Character background extended display

0 OFF (Normal display)

1 ON (Extended display)

521

CHAPTER 18 OSDC

Display Examples

Character background extended display = OFF

Figure 18.2-48 shows a display example with character background extended display = OFF.

Figure 18.2-48 Display Example with Character Background Extended Display = OFF

Character background extended display = ON

Figure 18.2-49 shows a display example with character background extended display = ON.

Line spacing

Line spacing(No character background) (Solid-filled background) (Convexed, shaded background)

522

CHAPTER 18 OSDC

Figure 18.2-49 Display Example with Character Background Extended Display = ON

Line spacing

Line spacing(No character background) (Solid-filled background) (Convexed, shaded background)

523

CHAPTER 18 OSDC

18.2.11 Line Background Display

The background of a line is displayed in the line area of the characters on the line, the areas to the right and left of the area, and the line spacing areas above and below it.

Line Background Control (Setting for Each Line)

Table 18.2-30 shows the line background control of line control data set 2 (command 4): Bits LM1and LM0.

*1: Concaved, shaded background display displays the highlight color on two dots of the upperside in the line area and the shadow color on two dots of the lower side.

*2: Convexed, shaded background display displays the shadow color on two dots of the upperside in the line area and the highlight color on two dots of the lower side.

Line Background Color (Setting for Each Line, Selected From Among 16 Colors)

Line background colors can be set by setting color codes in bits L3 to L0 of line control data set 2(command 2).

Shaded Background Highlight Color (Setting for Each Screen, Selected from Among 16 Colors)

Shaded background frame color control (command 6-1): Bits BH3 to BH0

Note: Shared with shaded character background display.

Shaded Background Shadow Color (Setting for Each Screen, Selected from Among 16 Colors)

Shaded background frame color control (command 6-1): Bits BS3 to BS0

Note: Shared with shaded character background display.

Note:


Table 18.2-30 Line Background Control (Setting for Each Line)

LM1 LM0 Line background

0 0 No background (undisplay)

0 1 Solid-filled background

1 0 Concaved, shaded background*1

1 1 Convexed, shaded background*2

524

CHAPTER 18 OSDC

Display Examples

Figure 18.2-50 shows examples of line background display.

Figure 18.2-50 Line Background Display Examples

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

No line background

Solid-filled background

(Shaded background frame highlight color)Convexed, shaded background(Shaded background frame shadow color)

(Shaded background frame shadow color)Concaved, shaded background(Shaded background frame highlight color)

⇒

⇒

⇒

⇒

←

←

←

←

Character display area

525

CHAPTER 18 OSDC

18.2.11.1 Shaded Background Succeeding Line Merge Display (Line Background)

Specifying "shaded background succeeding line merge display" for a line enables the line to be displayed with the line background merged with that of the next line.This undisplays the lower line of the line background shadow frame of the current line and the upper line of the line background shadow frame of the next line.

Shaded Background Succeeding Line Merge Control (Setting for Each Line)

Table 18.2-31 shows the shaded background succeeding line merge control of line control dataset 2 (command 4): Bit LD.

Table 18.2-31 Shaded Background Succeeding Line Merge Control (Setting for Each Line)

LDShaded background

succeeding line merge control

0 OFF

1 ON

526

CHAPTER 18 OSDC

Display Examples

Figure 18.2-51 shows examples of shaded background succeeding line merge display.

Figure 18.2-51 Examples of Shaded Background Succeeding Line Merge Display

Note:

Specifying shaded background succeeding line merge display applies merge control to the characterand line backgrounds at the same time.

If character background extended display is off, however, merge control ignores shaded backgroundcharacters.

Figure 18.2-52 to Figure 18.2-56 show display examples of a combination of shaded characterbackground display and shaded line background display.

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

(Shaded background frame highlight color)

(Shaded background frame highlight color)

Convexed, shaded background withsucceeding line merge ON

(Shaded background frame shadow color)

Convexed, shaded background withsucceeding line merge OFF

⇒

←

←

←

(Shaded background frame shadow color)←

⇒

Concaved, shaded background withsucceeding line merge ON

⇒

Convexed, shaded background withsucceeding line merge OFF

⇒

527

CHAPTER 18 OSDC

Figure 18.2-52 Display Example of a Combination of Shaded Character Background Display and Shaded Line Background Display (1)

Shaded line background

Line spacingShaded character background

Shaded line background Line spacing

Shaded line background

Shaded character background

Shaded character background

Line spacing

Line spacing

Bit LD = 0Bit LE = 0


528

CHAPTER 18 OSDC



The shaded line backgroundframe at this position isundisplayed.

The shaded characterbackground frame at thisposition is displayed whenbit LE = 0.


529

CHAPTER 18 OSDC


The character backgroundat this position is extended.


Bit LE = 0Bit LE = 0

530

CHAPTER 18 OSDC



The shaded character backgroundframe at this position is undisplayed.


Shaded linebackground

531

CHAPTER 18 OSDC



The shaded character backgroundframe at this position is undisplayed.


Shaded linebackground

532

CHAPTER 18 OSDC

18.2.12 Screen Background Display

Screen background display has screen background character display and screen background color display functions.

Screen Background Display

Screen background character display

Screen background character display displays a graphic character on the entire screen byrepeating display of the same blocks of two by two, or four characters.

Screen background color display

Screen background color display displays the background color on the entire screen as thebottom layer output.

533

CHAPTER 18 OSDC

18.2.12.1 Screen Background Character Display

Screen background character display repeats display of the blocks of two by two characters on the entire screen. Screen background character display is only enabled for graphic characters.

Configuration of Screen Background Character Display

Figure 18.2-57 shows an example of screen background character display.

Figure 18.2-57 Example of Screen Background Character Display

534

CHAPTER 18 OSDC

Screen Background Character Display Control

Screen background character output control

Table 18.2-32 shows the screen background character output control of screen output control 1(command 5-0): Bit PDS.

Screen background character code

Screen background character control 1 (command 7-1): Bits PM11 to PM0

Set PM1 = 0 and PM0 = 0.

Note:

Only the L size of graphic characters can be used as screen background characters.

Screen background character vertical size control

Table 18.2-33 shows the screen background character vertical size control of screen backgroundcharacter control 4 (command 7-3): Bits PH2 to PH0.

Table 18.2-32 Screen Background Character Output Control

PDS Screen background character display

0 OFF

1 ON

Table 18.2-33 Screen Background Character Vertical Size Control

PH2 PH1 PH0 Display vertical size

0 0 0 18 dots

0 0 1 20 dots

0 1 0 22 dots

0 1 1 24 dots

1 0 0 26 dots

1 0 1 28 dots

1 1 0 30 dots

1 1 1 32 dots

535

CHAPTER 18 OSDC

Screen background character configuration control

Table 18.2-34 shows the screen background character configuration control of screen backgroundcharacter control 1 (command 7-1): Bits PD1 and PD0.

Figure 18.2-58 shows an example of screen background character configuration.

Figure 18.2-58 Example of Screen Background Character Configuration

Table 18.2-34 Screen Background Character Configuration Control

PD1 PD0Screen background

character configuration

0 1 1 character

0 1 Horizontal set of 2 characters

1 0 Vertical set of 2 characters

1 1 2 characters × 2 characters

- Screen background character code = nCharacter code

Example of 1-character configuration (PD1, PD0) = (0, 0)

nn

Example of a horizontal 2-character configuration (PD1, PD0) = (0, 1)n+1

n n+1

n+2 Example of a vertical 2-character configuration (PD1, PD0) = (1, 0)

n

n+3n+1

Example of a 4-character configuration (PD1, PD0) = (1, 1)

n n+1

n+2 n+3

536

CHAPTER 18 OSDC

18.2.12.2 Screen Background Color Display

Screen background color display displays the background color on the entire screen as the bottom layer output of the display screen.

Screen Background Output Control

Table 18.2-35 shows the screen background output control of screen output control 1 (command5-0): Bit UDS.

Screen Background Color Control

Screen background colors can be set by setting color codes in bits U3 to U0 of screenbackground character control 4 (command 7-3).

Note:


Table 18.2-35 Screen Background Output Control

UDS Screen background color output

0 OFF

1 ON

537

CHAPTER 18 OSDC

18.2.13 Sprite Character Display

Sprite characters are displayed on the top layer. The OSDC supports sprite display of only graphic characters.

Sprite Character Configuration

Figure 18.2-59 shows an example of displaying sprite characters.

Figure 18.2-59 Sprite Character Display Example

Sprite Character Display Control

Sprite character output control

Table 18.2-36 shows the sprite character output control of screen output control 1 (command 5-0): Bit SDS.

Sprite character code

Sprite character control 1 (Command 8-1): Bits SM11 to SM0

Set SM1 = 0, SM0 = 0.

Note:

Only the L size of graphic characters can be used as sprite characters.

Sprite character

Table 18.2-36 Sprite Character Output Control

SDS Sprite character output

0 OFF

1 ON

538

CHAPTER 18 OSDC

Sprite character vertical display position control

Sprite character control 3 (Command 9-0): Bits SY9 to SY0

Settable between 0 and 2046 dots in 2-dot units.

Sprite character horizontal display position control

Sprite character control 4 (Command 9-1): Bits SX10 to SX0

Settable between 0 and 3070 dots in 2-dot units.

The calculation for the set value of horizontal display position in the sprite characters is as follow.

Set value of horizontal display position = (SX8, SX7, SX6, SX5, SX4, SX3, SX2) × 12 + (SX0, SX1) × 4 [dot]

Note: However, setting of (SX2, SX1, SX0) = (1,1,0) or (1,1,1) is prohibited.

SX10 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 Set value of sprite horizontaldisplay position

0 0 0 0 0 0 0 0 0 0 0 0 dots (0+0)

0 0 0 0 0 0 0 0 0 0 1 2 dots (0+2)

0 0 0 0 0 0 0 0 0 1 0 4 dots (0+4)

0 0 0 0 0 0 0 0 0 1 1 6 dots (0+6)

0 0 0 0 0 0 0 0 1 0 0 8 dots (0+8)

0 0 0 0 0 0 0 0 1 0 1 10 dots (0+10)

0 0 0 0 0 0 0 1 0 0 0 12 dots (12+0)

0 0 0 0 0 0 0 1 0 0 1 14 dots (12+2)

0 0 0 0 0 0 0 1 0 1 0 16 dots (12+4)

0 0 0 0 0 0 0 1 0 1 1 18 dots (12+6)

0 0 0 0 0 0 0 1 1 0 0 20 dots (12+8)

0 0 0 0 0 0 0 1 1 0 1 22 dots (22+10)

0 0 0 0 0 0 1 0 0 0 0 24 dots (24+0)

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1 1 1 1 1 1 1 1 1 0 1 3070 dots (3060+10)

539

CHAPTER 18 OSDC

Sprite character vertical size control

Table 18.2-37 shows the sprite character vertical size control of sprite character control 3(command 8-2): Bits SH3 to SH0.

Sprite character configuration control

Table 18.2-38 shows the sprite character configuration control of sprite character control 2(command 8-1): Bits SD1 and SD0. Figure 18.2-60 shows an example of sprite characterconfiguration.

Table 18.2-37 Sprite Character Vertical Size Control

SH2 SH1 SH0 Sprite character vertical size control

0 0 0 18 dots

0 0 1 20 dots

0 1 0 22 dots

0 1 1 24 dots

1 0 0 26 dots

1 0 1 28 dots

1 1 0 30 dots

1 1 1 32 dots

Table 18.2-38 Sprite Character Configuration Control

SD1 SD0 Configuration

0 0 1 character

0 1 Horizontal set of 2 characters

1 0 Vertical set of 2 characters

1 1 2 characters × 2 characters

540

CHAPTER 18 OSDC

Figure 18.2-60 Sprite Character Configuration Example

- Sprite character code = nCharacter code

Example of a 1-character sprite character (SD1, SD0 = 0, 0)

nn

Example of a horizontal 2-character sprite character (SD1, SD0 = 0, 1)n+1

n n+1

n+2 Example of a vertical 2-character sprite character (SD1, SD0 = 1, 0)

n

n+3n+1

Example of a 4-character sprite character (SD1, SD0 = 1, 1)

n n+1

n+2 n+3

541

CHAPTER 18 OSDC

18.3 Control Functions

This section explains the OSDC control functions.

18.3.1 Dot Clock Control

18.3.2 Sync Signal Input

18.3.3 Display Signal Output

18.3.4 Display Period Control

18.3.5 Synchronization Control

18.3.6 Interrupt Control

18.3.7 OSDC Operation Control

542

CHAPTER 18 OSDC

18.3.1 Dot Clock Control

Dot clock control allows selection of external dot clock input or internal VCO generation dot clock input. Commands 17-0, 17-1 and 18-0 to 18-3 enable dot clock control.

Input Dot Clock Selection Control

Table 18.3-1 shows the dot clock selection control of dot clock control 1 (command 17-0): BitDCK. To use the internal VCO generation dot clock, specify VCO-related control of commands18-0 to 18-13 and then use this command to select the input dot clock.

External Dot Clock Input

The OSDC inputs a clock signal from an external oscillator.

The clock signal is assumed to be synchronized with the input horizontal sync signal.

Table 18.3-1 Dot Clock Selection Control

DCK Dot clock control

0 External dot clock input (initial state)

1 Internal VCO generation dot clock input

543

CHAPTER 18 OSDC

Internal VCO Generation Dot Clock Input

Dot clock circuit configuration

The clock generated by the internal VCO is used as a dot clock through the internal prescaler.(Dot clock circuit is configured by three types of PLLA, PLLB and PLLC.)

Figure 18.3-1 shows the dot clock circuit block diagram.

Figure 18.3-1 Dot Clock Circuit Block Diagram

Phasecomparator A

Phasecomparator B

Phasecomparator C

FH

DCKO

VCO A

CPOA

CPOB

CPOC

HSYNCA

Counter A

DKA[11:0] setting

SDOT[2:0]setting

DCK setting

DAP[4:0] setting

VSELA[2:0] settingVCDA setting

(HSYNC1/SLCLK)

HSYNCB(HSYNC2)

HSYNCC(HSYNC3)

HSPLA[1:0]setting

FHS[1:0] settingHSOSX setting

HSPLB[1:0] setting

HSPLC[1:0] setting

DBP[4:0] setting

Prescaler ACKA

FH1

PLLA

CKBPrescaler B

DHRSA setting

DCO setting

OSDHSYNC

VCO B

Counter B

DKB[11:0] setting

DCP[4:0] setting

VSELB[2:0] settingVCDB setting

DDP[4:0] setting

Prescaler CCKC

FH2

PLLB

CKD

SLYCLKA(SLYCLK1)

Internal DOTCLK

Internal HSYNC

Inaternal FH

SLYCLKB(SLYCLK2)Prescaler D

DHRSB setting

DHRSC setting

VCO C

Counter C

DKC[11:0] setting

DEP[4:0] setting

VSELD[2:0] settingVCDC setting

DFP[4:0] setting

Prescaler ECKE

FH3

PLLC

CKF

CKG

Prescaler F

S

electer

Selecter

Selecter

Selecter

Selecter

FH1

FH2FH3

FHO setting

DOCKI

SSLA[2:0]setting

SSLB[2:0]setting

544

CHAPTER 18 OSDC

Dot clock prescaler control

Table 18.3-2 shows the dot clock prescaler control of PLLA/B/C clock control 1-1/2 (command 18-0, 18-1, 18-4, 18-5, 18-8 and 18-9): Bits DAP4-0, DBP4-0, DCP4-0, DDP4-0, DEP4-0 and .DFP4-0.

Phase comparison edge selection control

Table 18.3-3 shows the phase comparison edge selection control of clock selection control 1(command 18-12): Bit DHRSA/DHRSB/DHRSC.

Note: When input HSYNC is negative logic

Dot clock control

A dot clock synchronized with the input horizontal sync signal HSYNC is generated by setting thenumber of clocks required for the horizontal synchronous width in PLLA/B/C clock control 2(command 18-2, 18-6 and 18-10): Bits DK10 to DK0.

Table 18.3-2 Dot Clock Prescaler Control

DAP4-0/DBP4-0/DCP4-0/DDP4-0/DEP4-0/DFP4-0 Dot clock prescaler configuration

0000 VCO oscillation clock

0001 VCO oscillation clock × 1/2




.

...



Table 18.3-3 Phase Comparison Edge Selection Control

DHRSADHRSBDHRSC

Phase comparison edge selection control

0 HSYNC rising edge

1 HSYNC falling edge

545

CHAPTER 18 OSDC

VCO oscillation control

Table 18.3-4 shows the VCO oscillation control of PLLA/B/C clock control 3 (command 11-3): BitVC.

Oscillating VCO selection control

Table 18.3-5 shows the VCO selection control of PLLA/B/C clock control 3 (command 18-3, 18-7,18-11): Bit VSLA[2:0], VSLB[2:0] and VSLC[2:0].

Note: The VCO oscillation guarantee band is different from the OSDC operation guaranteefrequency.

VCO phase comparator control

Table 18.3-6 shows the phase comparator control of PLLA/B/C clock control 3 (command 18-3,18-7 and 18-11): Bit PDEA, PDEB and PDEC.

Table 18.3-4 VCO Oscillation Control

VC VCO oscillation control

0 VCO oscillation stop state

1 VCO oscillation state

Table 18.3-5 Oscillating VCO Selection Control

VSLA2VSLB2VSLC2

VSLA1VSLB1VSLC1

VSLA0VSLB0VSLC0

VCO selection

configuration

VCO oscillation guarantee frequency band

MB91F318A/BMB91F319A

MB91316/316AMB91F318R/SMB91FV319R

0 0 0 VCO1 20 to 40 MHz 10 to 25 MHz20 to 50 MHz

0 0 1 VCO2 39 to 53 MHz 20 to 50 MHz

0 1 0 VCO3 51 to 70 MHz 30 to 60 MHz40 to 70 MHz

0 1 1 VCO4 65 to 91 MHz 55 to 95 MHz

1 0 0 VCO5 90 to 125 MHz 65 to 110 MHz

Setting prohibited

1 0 1 VCO6 124 to 160 MHz 105 to 160 MHz

1 1 0 - Setting prohibited

Setting prohibited1 1 1 -

Table 18.3-6 Phase Comparator Control

PDEAPDEBPDEC

Phase comparator control

0 Stop

1 Normal operation

546

CHAPTER 18 OSDC

VCO charge pump control

Table 18.3-7 shows the charge pump control of PLLA/B/C clock control 3 (command 18-3, 18-7and 18-11): Bit CPEA, CPEB and CPEC.

VCO charge pump bias current control

Table 18.3-8 shows the charge pump bias current control of PLLA/B/C clock control 3 (command18-3, 18-7 and 18-11): Bit CHGA[1:0], CHGB[1:0] and CHGC[1:0].

Output Dot Clock Control

Output dot clock control controls the dot clock output of the DCK0 pin.

Table 18.3-9 shows the output dot clock selection control of dot clock selection control (command18-12): Bit DC0.

Table 18.3-7 Charge Pump Control

CPEACPEBCPEC

Charge pump control

0 Stop

1 Normal operation

Table 18.3-8 Charge Pump Bias Current Control

CHGA1CHGB1CHGC1

CHGA0CHGB0CHGC0

Charge pump bias current control

0 0 About 100 µA

0 1 About 500 µA

1 0 About 1 mA


Table 18.3-9 Output Dot Clock Control

DC0 Output dot clock control

0 Dot clock output OFF

1 Dot clock output ON

547

CHAPTER 18 OSDC

18.3.2 Sync Signal Input

This section explains vertical synchronization detection and horizontal synchronization operation in sync signal input.

Sync Signal Input

Vertical synchronization detection

The level of vertical sync signal is sensed at the leading or trailing edge of the horizontal syncpulse to detect the transition.

Horizontal synchronous operation


Field detection

The field state for interlaced display is detected by monitoring the falling edge of the vertical syncsignal.

548

CHAPTER 18 OSDC

18.3.2.1 Vertical Synchronization Control

Vertical synchronization detection senses the level of the vertical sync signal at the leading or trailing edge of the horizontal sync pulse to detect the transition. The vertical display position on the screen depends on the vertical synchronization detection position.

Vertical Synchronization Detection

The vertical synchronization operation is required the setting of the vertical synchronizationdetection HSYNC edge selection control of the I/O pin control 2 (command 13-1) and the verticalsynchronization signal input logic control.

The vertical synchronization detection HSYNC edge selection control is set of the phase of theinput horizontal synchronous signal and the vertical synchronization signal.

Also, the VSYNC pin input logic control is set the logic of the input vertical synchronization signal.The control is shown in Table 18.3-10 and Table 18.3-11.

Table 18.3-10 Vertical Synchronization Detection HSYNC Edge Selection

VHEVertical synchronization detection

HSYNC edge

0Vertical synchronization is detected at leading edge of HSYNC.

1Vertical synchronization is detected at trailing edge of HSYNC.

Table 18.3-11 Vertical Synchronization Signal Input Logic Control

IHX Horizontal sync signal input logic

0 HSYNC pin is negative logic input.

1 HSYNC pin is positive logic input.

549

CHAPTER 18 OSDC

Examples of Vertical Synchronization Detection Operation

Figure 18.3-2 and Figure 18.3-3 show examples of vertical synchronization detection operation.

Figure 18.3-2 Detecting Vertical Synchronization at the Leading Edge of the Horizontal Sync Pulse (Operation When VHE is Set to 0)

Figure 18.3-3 Detecting Vertical Synchronization at the Trailing Edge of the Horizontal Sync Pulse (Operation When VHE is Set to 1)

Note:

When the following setting is performed to the vertical synchronization detection HSYNC edgeselection (VHE) and the horizontal synchronous operation edge (HE), the restriction is displayed inthe main screen, the sprite screen, and the screen background characters.

• Setting conditions

Vertical synchronization detection HSYNC edge selection: VHE=1 (vertical synchronization signal detection at trailing edge of the horizontal synchronous signal)

Horizontal synchronous operation edge selection: HE= 1 (horizontal synchronous control operation at leading edge of the horizontal synchronous)

• Restrictions

Main screen display: vertical display position control (command 5-2):When setting the Y/-Y0 bit to "000H", the main screen is disabled to display. The display isenabled when the setting value is "001H" or more.

Sprite screen display: Sprite character vertical display position control (command 9-0):When setting the SY9-Y0 bit to "000H", the sprite screen is disabled to display. The display isenabled when the setting value is "001H" or more.

Screen background character display: the display is disabled.

VSYNC input

HSYNC input

Internally detected VSYNC

VSYNC input

HSYNC input

Internally detected VSYNC

550

CHAPTER 18 OSDC

18.3.2.2 Horizontal Synchronous Operation


Horizontal Synchronous Operation

The horizontal synchronous operation is required the setting of the horizontal synchronousoperation edge selection of I/O pin control 2 (command 13-1) and the horizontal synchronoussignal input logic control.

Table 18.3-12 and Table 18.3-13 show the horizontal synchronous operation edge selection.

Example of Horizontal Synchronous Operation

Figure 18.3-4 and Figure 18.3-5 show examples of horizontal synchronous operation.

Figure 18.3-4 Horizontal Synchronous Operation at Trailing Edge (HE=0, IHX=0)

Figure 18.3-5 Horizontal Synchronous Operation at Leading Edge (HE=0, IHX=0)

Table 18.3-12 Horizontal Synchronous Operation Edge Selection

HE Horizontal synchronous operation edge

0 Trailing edge

1 Leading edge

Table 18.3-13 Horizontal Synchronous Signal Input Logic Control

IHX Horizontal sync signal input logic

0 HSYNC pin is negative logic input.

1 HSYNC pin is positive logic input.

HSYNC input

Internally detected HSYNC

HSYNC input

Internally detected HSYNC

551

CHAPTER 18 OSDC

Note:

When the following setting is performed to the vertical synchronization detection HSYNC edgeselection (VHE) and the horizontal synchronous operation edge (HE), the restriction is displayed inthe main screen, the sprite screen, and the screen background characters.

• Setting conditions

Vertical synchronization detection HSYNC edge selection: VHE=1 (vertical synchronization signal detection at trailing edge of the horizontal synchronous signal)

Horizontal synchronous operation edge selection: HE= 1 (horizontal synchronous control operation at leading edge of the horizontal synchronous)

• Restrictions

Main screen display: vertical display position control (command 5-2):When setting the Y/-Y0 bit to "000H", the main screen is disabled to display. The display isenabled when the setting value is "001H" or more.

Sprite screen display: Sprite character vertical display position control (command 9-0):When setting the SY9-Y0 bit to "000H", the sprite screen is disabled to display. The display isenabled when the setting value is "001H" or more.

Screen background character display: the display is disabled.

552

CHAPTER 18 OSDC

18.3.2.3 Field Control

When interlaced display is performed (the input sync signal is used for display at interlace timing), the field can be detected from the phase timings of the input vertical sync signal and input horizontal sync signal. The font display raster (even/odd) is selected, output, and controlled according to the result of detecting this field.To perform interlaced display during dot clock external input operation, set the number of clocks for the horizontal sync signal period in command 11-2 (bits DK10 to DK0).Control is not required for noninterlaced display.

Field Detection Control

Synchronous control (command 11-0):When setting the interlace of the IN bit, detects the field to perform the interlaced display fromthe phase state of the input horizontal/vertical sync signal.

• Field detection is controlled by observing the level of the vertical sync signal at timings H/4before and after the leading edge of the sync pulse of the vertical sync signal to detect theleading edge of the vertical sync pulse. If the level of the vertical sync signal changes in thevicinity of this detection position, normal field detection might not be performed. If the cycle ofthe horizontal sync signal changes in the vicinity of the sync pulse of the vertical sync signal,normal field detection might not be performed. Input the horizontal sync signal after stabilizingthe signal in the external circuit.

• The field detection timing "H/4", the dot clock control 2 (command 11-2): sets to DK10 to 0 bitand is calculated the clock number of the horizontal synchronous cycle as 1H.

Note:

The display raster of the font which is displayed in each field during interlacing, see "18.3.5Synchronization Control".

553

CHAPTER 18 OSDC

• Figure 18.3-6 shows the input timing of vertical synchronization signal (VSYNC pin inputsignal) and horizontal synchronization signal (HSYNC pin input signal) for interlacing display.

Figure 18.3-6 Field Detection Timing

Note:

The display raster of the font which is displayed in each field during interlacing, see "18.3.5Synchronization Control".

H/4H/4

Vertical synchronizationsignal

Horizontal synchronous signal

H/4 H/4

[Field A detection timing]

[Field B detection timing]

Vertical synchronizationsignal

Horizontal synchronous signal

554

CHAPTER 18 OSDC

Field Correction Control

Field correction control

Field correction control converts the display status of the even raster display field of the font to bedisplay the field detection control and the add raster display field. If normal display output to eachfield is not performed (the output field is abnormal) in interlaced display output mode, corrects thedisplay output.

The synchronous control (command 11-0): the field correction control of the FC bit can beallowed replacement of the output to each field.

Table 18.3-14 shows the field 0 correction control (FC) of synchronous control (command 11-0).

Table 18.3-14 Field Correction

FC Field correction

0 No correction

1 Correction

555

CHAPTER 18 OSDC

18.3.3 Display Signal Output

This section describes the timing of display signal output.

Display Signal Output Timing

Display signals (outputs)

• Output display period signal: VOB1 pin

• Translucent color display period signal: VOB2 pin

• Display color code: RGB

Example of Display Signal Output (1)

Figure 18.3-7 shows an example of display signal output (with character color display ON,character background color display ON, and trimming color display ON)

556

CHAPTER 18 OSDC

Figure 18.3-7 Example of Display Signal Output (with Character Color Display ON, Character Background Color Display ON, and Trimming Color Display ON)

Note:

While VOB1 output is inactive, the color code at palette address 0H is output by an OSDC macro(when DCX = 0).

Example display

Display line Output dot number

Output dot number

RGB output(Color information)

Character background color Character color Character background color VOB1 output Output data position

Note: In this example, I/O signals are set for positive logic.

0 1 2 3 4 5 6 7 8 9 A B

0 1 2 3 4 5 6 7 8 9 A B

Palette data output Palette data output

Trimming color Trimming color

557

CHAPTER 18 OSDC

Example of Display Signal Output (2)

The examples below show display-disabled periods due to input of horizontal synchronization(HSYNC) and vertical synchronization (VSYNC) signals.

Figure 18.3-8 and Figure 18.3-9 show examples of display-disabled periods due to input ofsynchronization signals.

Figure 18.3-8 Example of Masking Display Signal Output by HSYNC Signal Input

Figure 18.3-9 Example of Masking Display Signal Output by VSYNC Signal Input

VOB output-enabled period

VOB output-disabled period

VOB output-enabled period VOB output-enabled period

VOB output-disabled period

HSYNC input

VOB output timing

VOB output-disabled period VOB output-disabled period

VOB output-enabled period VOB output-enabled period VOB output-enabled period

VSYNC input

HSYNC input

VOB output period

558

CHAPTER 18 OSDC

18.3.4 Display Period Control

There are two display period control functions:• Vertical display period control• Horizontal display period controlThese functions enable horizontal blanking and vertical blanking to be controlled.

Vertical Display Period Control

Vertical display period control is used to generate vertical display periods for controlling theoutput of display signals. In a vertical display period, signals for display in vertical directions areoutput. Vertical display periods can be set by commands.

Figure 18.3-10 shows an example of vertical display period control.

Figure 18.3-10 Vertical Display Period Control

The start and end of a vertical display period can be specified as follows:

Vertical display start timing

Display period control 1 (command 14-0): bits DYS10 to DYS0 = number of Hsync signals = 0 to2047, set in units of 1 Hsync signals

Vertical display end timing

Display period control 2 (command 14-1): bits DYE10 to DYE0 = number of Hsync signals = 0 to2047, set in units of 1 Hsync signals

VSYNC input(VSYNC pin)Internal VSYNC pulseVertical display period Display signal

output disabledDisplay signal output disabled

Display signal output enabled

Display start timing

Display end timing

559

CHAPTER 18 OSDC

Horizontal Display Period Control

Horizontal display period control is used to generate horizontal display periods for controlling theoutput of display signals. In a horizontal display period, signals for display in horizontal directionsare output. Horizontal display periods can be set by commands. The following two types ofoperation are done according to the setting of the HSYNC edge selection bit (HE bit) of the I/Opin control command (command 13-0):

• Operation with the trailing edge selected for horizontal synchronization (HE bit = 0)

• Operation with the leading edge selected for horizontal synchronization (HE bit = 1)

Figure 18.3-11 shows an example of horizontal display period control.

Figure 18.3-11 Horizontal Display Period Control

The start and end of a horizontal display period can be specified as follows:

Horizontal display start timing

Display period control 3 (command 14-2): bits DXS10 to DXS0 = number of dot clock signals = 0to 2047, set in units of 1 dot clock signals

Horizontal display end timing

Display period control 4 (command 14-3): bits DXE10 to DXE0 = number of dot clock signals = 0to 2047, set in units of 1 dot clock signals

Note:

When the following setting is performed, the display end timing setting is invalid. The display outputenabled period is set until the synchronization signal inputs.

DXS [10:0] (horizontal display start timing) ≥ DXE [1:0] (horizontal display end timing)

- Operation with the trailing edge selected for horizontal synchronization (HE bit = 0)

- Operation with the leading edge selected for horizontal synchronization (HE bit = 1)

HSYNC input(HSYNC pin)

Horizontal display period

Horizontal display period

HSYNC input(HSYNC pin)

Display signal output disabled








Display end timing

Display end timing

560

CHAPTER 18 OSDC

18.3.5 Synchronization Control

You can specify interlaced or noninterlaced display by setting the interlace/non-interlace control bit (IN bit) of the synchronization control command (command 11-0).

Synchronization Control (Vertical Enlargement Control)

Table 18.3-15 shows the bit settings for synchronization control.

Display Example

Figure 18.3-12 shows the font memory original data.

Figure 18.3-12 Font Memory Original Data

• The examples of interlaced display (IN=0) is shown Figure 18.3-13.

• The interlaced display consists of the displayed image to display the different dots of the fontoriginal data in field A and field B that are detected by "18.3.2.3 Field Control".

Table 18.3-15 Synchronization Control

IN Vertical enlargement control

0 Interlaced display

1 Noninterlaced display

24 dots

32 dots

FontrasterNo.0123456

3031

561

CHAPTER 18 OSDC

Figure 18.3-13 Examples of Interlaced Display

Note:

When the display raster of the display font data in the interlaced display is inverted, the fieldcorrection control (command 11-0): the correction is allowed by controlling of the FC bit.

n

n+1

n+2

n+3

n+15

n

n+1

n+2

n+15

Field A: Font even raster displayFont raster

No.

0

2

4

6

30

Font rasterNo.

1

3

5

30

Field B: Font odd raster display

n+3

Horizontal display rasterNo.


(Note) n is an arbitrary display raster No.

562

CHAPTER 18 OSDC

• The example of noninterlaced display (IN = 1) is shown Figure 18.3-14.

The noninterlaced display consists of the image to output the font original data sequentially.

Figure 18.3-14 Example of Noninterlaced Display

nn+1n+2n+3n+4n+5n+6

n+30n+31

Font rasterNo.

0123456

3031


(Note) n is an arbitrary display raster No.

563

CHAPTER 18 OSDC

18.3.6 Interrupt Control

There are three factors of OSDC control interrupt:• Detection of line display end• Detection of vertical synchronization signal• Detection of VRAM fill endAn interrupt request is issued to the CPU when any of the three factors occurs.

Interrupt Control

Interrupt control is used to control the interrupts generated by the internal operation status.

Interrupt control is performed according to the interrupt factor flags and interrupt generationcontrol bits of the interrupt control command (command 15-0).

Interrupt Factor Flags

Each interrupt factor flag is set to 1 when the relevant factor occurs.

To clear a set interrupt factor flag, it is set to 0.

There are three interrupt factor flags:

• Line display end flag (bit LIF of command 15-0)

• Vertical synchronization signal input flag (bit VIF of command 15-0)

• VRAM fill end flag (bit FIF of command 15-0)

Line display end flag

The last raster of each line and a line end detection line for the top-line immediately start rasterpart as shown in Figure 18.3-15 becomes a factor of line display end.

564

CHAPTER 18 OSDC

Figure 18.3-15 Line Display End Detection

Vertical synchronization signal input flag

The trailing edge of the internal vertical synchronization signal is detected.

The point where a vertical synchronization signal as shown in Figure 18.3-16 is detectedbecomes a factor of vertical synchronization signal input.

Figure 18.3-16 Vertical Synchronization Signal Detection

VRAM fill end flag

The end of VRAM setting started by a VRAM fill command (command 0 to 2) becomes a factor ofVRAM fill end.

Line end detection line



Line widthNo line spacing

Upper line spacing

Lower line spacing

Line widthLine spacing specified



Line widthNo line spacing

Line address: AY=0×0 (top line)

Line address: AY=0×1

Line address: AY=0×2 to 0×E is omitted.

Line address: AY=0×F (last line)

∗

VSYNC input(VSYNC pin)

OSDCInternal VSYNC

Point of vertical synchronization signal detection

565

CHAPTER 18 OSDC

Interrupt Generation Control

The interrupt generation control bits are used to enable or disable interrupts.

There are three interrupt generation control bits:

Line display end interrupt (bit LIE of command 15-0)

Table 18.3-16 shows the bit settings for line display end interrupt control.

Vertical synchronization signal input interrupt (bit VIE of command 15-0)

Table 18.3-17 shows the bit settings for vertical synchronization signal input interrupt control.

VRAM fill end interrupt (bit FIE of command 15-0)

Table 18.3-18 shows the bit settings for VRAM fill end interrupt control.

Table 18.3-16 Line Display End Interrupt Control

LIE Line display end interrupt

0 Interrupt disabled

1 Interrupt enabled

Table 18.3-17 Vertical Synchronization Signal Input Interrupt Control

VIEVertical synchronization signal

input interrupt


1 Interrupt enabled

Table 18.3-18 VRAM Fill End Interrupt Control

FIE VRAM fill end interrupt


1 Interrupt enabled

566

CHAPTER 18 OSDC

18.3.7 OSDC Operation Control

The OSDC operation control function controls the operation of the OSDC.

OSDC Operation Control

Before OSDC operation control, the input dot clock selection, DAC, and output pin must be set asrequired and the OSDC must be activated.

Input dot clock selection control

Table 18.3-19 shows the settings of the DCK bit of the OSDC operation control 1 command(command 17-0) for input dot clock control.

To select the clock generated by VCO, make the VCO-related settings of clock control 1, clockcontrol 2, and clock control 3 before setting the DCK bit.

DAC control

Table 18.3-20 shows the settings of the DAC bit of the OSDC operation control 1 command(command 17-0) for DAC control.

Table 18.3-19 Input Dot Clock Selection Control

DCK Dot clock control

0 Input of external dot clock

1Input of the dot clock generated by internal VCO

Table 18.3-20 DAC Control

IN DAC control

0 Stopped

1 Operated

567

CHAPTER 18 OSDC

Output pin control

Table 18.3-21 shows the settings of bits ANO, DGO, FHO, FHS1 and FHS0 of the OSDCoperation control 2 command (command 17-1) for output pin control.

OSDC activation control

Table 18.3-22 shows the settings of the OSDEN bit of the OSDC operation control 2 command(command 17-1) for OSDC activation control.

CC Operation Control

Table 18.3-23 shows the settings of the CCEN bit of the OSDC operation control 2 (command 17-1) for CC operation control.When the display command of CC screen is issued, set this CCEN bit to "1" (the state which CCoperation is enabled). (When CCEN bit is 0, display control command of CC screen is not accepted.)

Table 18.3-21 Output Pin Control

AN0 Analog RGB output pin control

0 Analog RGB output turned off

1 Analog RGB output turned on

DG0 Digital RGB output pin control

0 Digital RGB output turned off

1 Digital RGB output turned on

FHO FHS1 FHS0 FH pin output

controls FH output selection

control

0 X X FH pin output OFF -

1

0 0

FH pin output ON

FH1 (PLLA-FH)

0 1 FH2 (PLLB-FH)

1 0 FH3 (PLLC-FH)

1 1 Setting disabled

Table 18.3-22 OSDC Activation Control

OSDEN OSDC

0 OSDC disabled

1 OSDC enabled

Table 18.3-23 CC Operation Control

CCEN CC operation control

0 CC disabled

1 CC enabled

568

CHAPTER 18 OSDC

18.4 Display Control Commands

This section describes the main display control commands of OSDC and OSDC operation control commands.

18.4.1 List of Display Control Commands

18.4.2 VRAM Write Address Set (Command 0)

18.4.3 Character Data Set (Commands 1 and 2)

18.4.4 Line Control Data Set (Commands 3 and 4)

18.4.5 Screen Output Control (Commands 5-00 and 5-1)

18.4.6 Display Position Control (Commands 5-2 and 5-3)

18.4.7 Character Vertical Size Control (Command 6-0)

18.4.8 Shaded Background Frame Color Control (Command 6-1)

18.4.9 Transparent/Translucent Color Control (Command 6-2)

18.4.10 Graphic Color Control (Command 6-3)

18.4.11 Screen Background Character Control (Commands 7-1 and 7-3)

18.4.12 Sprite Character Control (Commands 8-1, 8-2, 9-0 and 9-1)

18.4.13 Synchronization Control (Command 11-0)

18.4.14 I/O Pin Control (Commands 13-0 and 13-1)

18.4.15 Display Period Control (Commands 14-0 to 14-3)

18.4.16 Interrupt Control (Command 15-0)

18.4.17 Palette Control (Commands 16-0 to 16-15)

18.4.18 OSDC Operation Control (Commands 17-0 and 17-1)

18.4.19 PLLA Clock Control (Commands 18-0 to 18-3)

18.4.20 PLLB Clock Control (Commands 18-4 to 18-7)

18.4.21 PLLC Clock Control (Commands 18-8 to 18-11)

18.4.22 Clock Selection Control (Commands 18-12 to 18-13)

569

CHAPTER 18 OSDC

18.4.1 List of Display Control Commands

The display control commands are shown. Table 18.4-1 shows list of main/OSDC operation control command.

List of Display Control Commands

Table 18.4-1 List of Display Control Commands (1 / 2)

Low-order 9 bits of address

OSDCcommand

No.

DataFunction

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 00 0 FL AY4 AY3 AY2 AY1 AY0 AX6 AX5 AX4 AX3 AX2 AX1 AX0 VRAM address

0 02 1 MIT MUL MBL MBB MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0 Character data setting 1

0 04 2 MR MG M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Character data setting 2

0 06 3 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0 Line control data setting 1

0 08 4 LDS LGY1 LGY0 LGX1 LGX0 LD LE LM1 LM0 L3 L2 L1 L0 Line control data setting 2

0 0A 5-00 SDS UDS PDS DSP Display output control 1

0 0C 5-1 FM1 FM0 BT1 BT0 BD1 BD0 Display output control 2

0 0E 5-2 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Vertical display position control

0 10 5-3 X8 X7 X6 X5 X4 X3 X2 X1 X0 Horizontal display position control

0 12 6-0 HB2 HB1 HB0 HA2 HA1 HA0 Character vertical size control

0 14 6-1 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0 Background color control with shadow

0 16 6-2 TCC HCC TC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0 Transparency/translucent color control

0 18 6-3 GFC GCC GF3 GF2 GF1 GF0 GC3 GC2 GC1 GC0 Graphic color control

0 1A 7-1 PCUT PD1 PD0 PM11 PM10 PM9 PM8 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Screen background character control 1

0 1C 7-3 PH2 PH1 PH0 U3 U2 U1 U0 Screen background character control 2

0 1E 8-1 SCUT SD1 SD0 SM11 SM10 SM9 SM8 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0 Sprite character control 1

0 20 8-2 SBL SH2 SH1 SH0 Sprite character control 2

0 22 9-0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 Sprite character control 3

0 24 9-1 SX10 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 Sprite character control 4

0 26 11-0 IN FC Synchronous control

0 2E 13-0 OHX OBX OCX I/O terminal control 1

0 30 13-1 VHE HE IHX IVX I/O terminal control 2

0 32 14-0 DYS10 DYS9 DYS8 DYS7 DYS6 DYS5 DYS4 DYS3 DYS2 DYS1 DYS0 Control at display period 1

0 34 14-1 DYE10 DYE9 DYE8 DYE7 DYE6 DYE5 DYE4 DYE3 DYE2 DYE1 DYE0 Control at display period 2

0 36 14-2 DXS10 DXS9 DXS8 DXS7 DXS6 DXS5 DXS4 DXS3 DXS2 DXS1 DXS0 Control at display period 3

0 38 14-3 DXE10 DXE9 DXE8 DXE7 DXE6 DXE5 DXE4 DXE3 DXE2 DXE1 DXE0 Control at display period 4

0 3A 15-0 FIF LIF VIF FIE LIE VIE Interruption control

0 3C 16-0 PLR2 PLR1 PLR0 PLG2 PLG1 PLG0 PLB2 PLB1 PLB0 Palette 0

0 3E 16-1 PLR2 PLR1 PLR0 PLG2 PLG1 PLG0 PLB2 PLB1 PLB0 Palette 1

0 40 16-2 PLR2 PLR1 PLR0 PLG2 PLG1 PLG0 PLB2 PLB1 PLB0 Palette 2





0 4A 16-7 PLR2 PLR1 PLR0 PLG2 PLG1 PLG0 PLB2 PLB1 PLB0 Palette 7









0 5C 17-0 DCK DPD OSDC operation control 1

0 5E 17-1 FHS1 FHS0 CCEN OSDEN FH0 DG0 ANO OSDC operation control 2

0 60 18-0 DAP4 DAP3 DAP2 DAP1 DAP0 PLLA clock control 1-1

0 62 18-1 DBP4 DBP3 DBP2 DBP1 DBP0 PLLA clock control 1-2

0 64 18-2 DKA11 DKA10 DKA9 DKA8 DKA7 DKA6 DKA5 DKA4 DKA3 DKA2 DKA1 DKA0 PLLA clock control 2

0 66 18-3 VCOA VSLA2 VSLA1 VSLA0 CHGA1 CHGA0 CPEA PDEA PLLA clock control 3

0 68 18-4 DCP4 DCP3 DCP2 DCP1 DCP0 PLLB clock control 1-1

0 6A 18-5 DDP4 DDP3 DDP2 DDP1 DDP0 PLLB clock control 1-2

0 6C 18-6 DKB11 DKB10 DKB9 DKB8 DKB7 DKB6 DKB5 DKB4 DKB3 DKB2 DKB1 DKB0 PLLB clock control 2

0 6E 18-7 VCOB VSLB2 VSLB1 VSLB0 CHGB1 CHGB0 CPEB PDEB PLLB clock control 3

0 70 18-8 DEP4 DEP3 DEP2 DEP1 DEP0 PLLC clock control 1-1

570

CHAPTER 18 OSDC

Note:

Input of a reset signal (input of high-level signal to the RESET pin) clears bits SDS, UDS, PDS, andDSP of the screen output control 1A command and bits 0HX, 0BX, and 0CX of the I/O pin control 1command. Other register bits and VRAM contents are not affected by input of a reset signal.

After input of a reset signal, be sure to set up all register bits and all contents of VRAM (characterand line control data).

When the display control command of the CC screen is issued, it should be set it to bit1(CCoperation ON) of CCEN of command 17-1(OSDC operation control 2)(CC operation ENABLE).(When the bit of CCEN is 0, the display control command of the CC screen is not accepted. )

Neither OSDC operation nor operation (SLYCLK, FH, DCKO) concerning OSDC when the commandis changed the command when the command of 17-0 to command 18-13 is setting changed arewarrantable at the OSDC normality displaying.

0 72 18-9 DFP4 DFP3 DFP2 DFP1 DFP0 PLLC clock control 1-2

0 74 18-10 DKC11 DKC10 DKC9 DKC8 DKC7 DKC6 DKC5 DKC4 DKC3 DKC2 DKC1 DKC0 PLLC clock control 2

0 76 18-11 VCOC VSLC2 VSLC1 VSLC0 CHGC1 CHGC0 CPEC PDEC PLLC clock control 3

0 78 18-12 HSPLC1 HSPLC0 HSPLB1 HSPLB0 HSPLA1 HSPLA0 HSOSX DHRSC DHRSB DHRSA DCO Clock selection control 1

0 7A 18-13 SSLB2 SSLB1 SSLB0 SSLA2 SSLA1 SSLA0 SDOT2 SDOT1 SDOT0 Clock selection control 2

Table 18.4-1 List of Display Control Commands (2 / 2)

Low-order 9 bits of address

OSDCcommand

No.

DataFunction

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

571

CHAPTER 18 OSDC

18.4.2 VRAM Write Address Set (Command 0)

Command 0 specifies a write address of VRAM and a VRAM fill operation.

Command 0 (VRAM Write Address Set)

Address: 000H

Format

[Function]

Command 0 specifies a write address of VRAM and a VRAM fill operation.

Command 0 specifies row and column addresses before being set by commands 1 and 2(character data set commands) and row addresses before being set by commands 3 and 4 (linecontrol data set commands).

A VRAM fill operation is started by executing a character data set 2 command (command 2).

[Supplement]

• A normal write (writing single-character data or single-line control data) is performed with"VRAM fill" set to OFF (FL = 0).

• The VRAM write address specified by command 0 is incremented automatically afterexecution of a character data set 2 command (command 2). (The last column is incremented to the first column of the next line by line feed; the last row isincremented to the first row.)

• The VRAM fill function writes the same character data specified by character data setcommands (commands 1 and 2) to the character VRAM area from the row/column addressspecified by command 0 to the last column (column 80) on the last row (row 32). A VRAM filloperation is started by issuing of character data set 2 command (command 2).After a VRAM fill operation ends, a VRAM fill interrupt can be generated.Commands 1 to 4 must not be issued while a VRAM fill operation is in progress.

Notes:

• When commands 3 and 4 (line control data set) are set, column addresses (AX6 to AX0) areignored. Execution of command 3 or 4 (line control set command) does not automaticallyincrement the address.

• "VRAM fill" is valid only to commands 1 and 2 (character data set commands).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FL 0 0 AY3 AY2 AY1 AY0 0 AX4 AX3 AX2 AX1 AX0 AX5

AY4-AY0: Row address (0-1FH)AX6 to AX0: Column address (0-4FH)

FL: Specify VRAM fill (0: OFF, 1: ON)

AY4 AX6

572

CHAPTER 18 OSDC

18.4.3 Character Data Set (Commands 1 and 2)

This command sets character data. Executing command 2 (character data set 2) sets VRAM to reflect it on the screen.

Command 1 (Character Data Set 1)

Address: 002H

Format

[Function]

Command 1 sets character data. Executing command 2 (character data set 2) sets VRAM toreflect it on the screen.

[Supplement]

• The character color, character background color, character background type, characterhorizontal size, italic display, and underline display can be set in an arbitrary combination foreach character.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIT MUL MBL MBB MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0

MC3 to MC0:

MB3 to MB0:

MM1, MM0:

MBL, MBB:

MIT:

Character color(From among 16 colors)

Character background color(From among 16 colors)

Character background control(0, 0: OFF)(0, 1: Solid-fill display)(1, 0: Concaved, shaded display)(1, 1: Convexed, shaded display)

Blinking control(0, 0: Blinking OFF)(0, 1: Character background blinking ON)(1, 0: Character and trimming dots blinking ON)(1, 1: Character, trimming dots, and character background blinking ON)

Italic display control(0: Italic display OFF)(1: Italic display ON)

MS1, MS0: Character horizontal size control0, 0: 12 dots0, 1: 18 dots1, 0: 24dots1, 1: Setting prohibited

MUL: Underline control(0: Underline OFF)(1: Underline ON)

573

CHAPTER 18 OSDC

• Shaded background display enables vertical or horizontal merge display according to thecombination of the MR bit of the character data set 2 command (command 2) and bits LD andLE of the line control data set 2 command (command 4).

• The shaded background frame color is set by command 6-1.

• When blinking control is turned on (MBL = 1), blinking display is executed according to bitsBT1, BT0, BD1, and BD0 of the screen output control 2 command (command 5-1).

Command 2 (Character Data Set 2)

Address: 004H

Format

[Function]

Command 2 writes the above setting data to the area of VRAM specified by command 0 (VRAMwrite address set 1), along with the character data set by command 1 (character data set 1).After this command is executed, the VRAM write address is incremented automatically.

[Supplement]

• The shaded background succeeding character merge control bit (MR) has an effect only onthe character specified as being shaded by command 1 (MM1 = 1).

Note:

Since reset input makes the contents of the entire area of VRAM undefined, be sure to set VRAMbefore display.

MR MG 0 0 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

MR:

M11 to M0:

Shaded background succeedingcharacter merge control(0: Do not merge)(1: Merge with the character to theright)

Character code(000H to FFFH: 4,096 character types)

MG: Character/graphic character control(0: Character, 1: Graphic character)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M11

574

CHAPTER 18 OSDC

18.4.4 Line Control Data Set (Commands 3 and 4)

This command sets line control data. Executing command 4 (line control data set 2) sets line VRAM to reflect it on the screen.

Command 3 (Line Control Data Set 1)

Address: 006H

Format

[Function]

Command 3 sets line control data. Executing command 4 (line control data set 2) sets line VRAMto reflect it on the screen.

[Supplement]

• The actual size, whose type is specified by the line character vertical size type control bit(LHS), is specified by command 6-0 (character vertical size control).

• The trimming mode is specified by command 5-1 (trimming mode control bits FM1 and FM0).

0 0 0 LHS 0 LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LHS:

LW2 to LW0:

LF3 to LF0:

Line character vertical size typecontrol(0: Character vertical size A)(1: Character vertical size B)

Line spacing control(0 to 14 dots in 2-dot units)

Trimming color(From among 16 colors)

LFD, LFC:

LFB, LFA:

Trimming output control(0, 0: All OFF)(0, 1: Trimming ON for characterwith no character background)(1, 0: Trimming ON for characterwith no solid-filled characterbackground)(1, 1: Trimming output ON)

Trimming control(0, 0: Trimming OFF)(0, 1: Right trimming)(1, 0: Left trimming)(1, 1: Before-side trimming)

575

CHAPTER 18 OSDC

Command 4 (Line Control Data Set 2)

Address: 008H

Format

[Function]

Command 4 writes the above setting data to the area of line VRAM specified by command 0(VRAM write address set 1), along with the line control data set by command 3 (line control dataset 1).

[Supplement]

The shaded background succeeding line merge control bit (LD) has different effects on thecharacter shaded backgrounds and line shaded backgrounds. For details, see "18.2.11.1Shaded Background Succeeding Line Merge Display (Line Background)".

Notes:

• Since reset input makes the contents of the entire area of VRAM undefined, be sure to set VRAMbefore display.

• Issuing this command does not automatically increment the VRAM write address. For each line tobe set, set the address using command 0.

0 0 0 LDS LGY1 LGY0 LGX1 LGX0 LD LE LM1 LM0 L3 L2 L1 L0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LDS:

LGY1, LGY0:

LGX1, LGX0:

Line character output control(0: Off, 1: ON)

Line vertical enlargement control(0, 0: Normal)(0, 1: Double height)(1, 0: Setting prohibited)(1, 1: Quadruple height)

Line horizontal enlargement control(0, 0: Normal)(0, 1: Double width)(1, 0: Setting prohibited)(1, 1: Quadruple width)

LE:

LD:

LM1, LM0:

L3 to L0:

Character background extensioncontrol(0: Normal, 1: Extended)

Shaded background succeeding line merge control(0: Independent, 1: Merge with the next line)

Line background control(0, 0: OFF)(0, 1: Solid-fill display)(1, 0: Concaved, shaded display)(1, 1: Convexed, shaded display)

Line background color(From among 16 colors)

576

CHAPTER 18 OSDC

18.4.5 Screen Output Control (Commands 5-00 and 5-1)

Commands 5-00 and 5-1 control the screen display output.

Command 5-00 (Screen Output Control 1)

Address: 00AH

Format

[Function]

Command 5-00 controls screen display output.

0 0 0 0 0 0 0 0 SDS UDS PDS DSP 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDS:

UDS:

Sprite character output control(0: OFF, 1: ON)

Screen background output control(0: OFF, 1: ON)

PDS:

DSP:

Screen background character output control(0: OFF, 1: ON)

Display output control(Control of character + trimming +character background + linebackground) (0: OFF, 1: ON)

577

CHAPTER 18 OSDC

Command 5-1 (Screen Output Control 2)

Address: 00CH

Format

[Function]

Command 5-1 controls screen display output.

[Supplement]

The blink cycle and blink duty ratio are controlled for the characters for which blinking control isspecified (MBL = 1) by the character data set 2 command (command 2). They are also controlledfor the sprite characters for which sprite character blinking control is specified (SBL = 1) by thesprite character control 2 command (command 8-2).

0 0 0 0 0 0 FM1 FM0 BT1 BT0 BD1 BD0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BT1, BT0:

BD1, BD0:

Blink cycle control(0, 0 : 16V)(0, 1 : 32V)(1, 0 : 48V)(1, 1 : 64V)

Blink duty ratio control(0, 0: On-to-off ratio = 1:0, always displayed)(0, 1: On-to-off ratio = 1:1)(1, 0: On-to-off ratio = 1:3)(1, 1: On-to-off ratio = 3:1)

FM1, FM0: Trimming type control(0, 0: 1-dot horizontal trimming(0, 1: 2-dot horizontal trimming)(1, 0: Pattern background 1)(1, 1: Pattern background 2)

578

CHAPTER 18 OSDC

18.4.6 Display Position Control (Commands 5-2 and 5-3)

Command 5-2 controls the vertical display position of the screen, and command 5-3 controls the horizontal display position of the screen.

Command 5-2 (Vertical Display Position Control)

Address: 00EH

Format

[Function]

Command 5-2 controls the vertical display position of the main screen.

Command 5-3 (Horizontal Display Position Control)

Address: 010H

Format

[Function]

Command 5-3 controls the horizontal display position of the main screen.

Horizontal display position setting value = (X8, X7, X6, X5, X4, X3, X2) × 12 + (X1, X0) × 4 [dots]

Note: Setting of (X1, X0) = (1, 1) is prohibited.

0 0 0 0 0 0 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Y9 to Y0: Vertical display position control(0-2046 in 2-dot units)

Y9

0 0 0 0 0 0 0 X8 X7 X6 X5 X4 X3 X2 X1 X0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X8 to X0: Horizontal display position control(0-1532 in 4-dot units)

579

CHAPTER 18 OSDC


This command controls the vertical display size A/B of each character.

Command 6-0 (Character Vertical Size Control)

Address: 012H

Format

[Function]

Command 6-0 controls the vertical display size A or B of each character.

[Supplement]

Character vertical size A or B can be selected for each line on the main screen. Select charactervertical size A or B with the LHS (line character vertical size type control) bit of the line data set 1command (command 3), and specify the number of dots by specifying character vertical size A orB using command 6-0.

0 0 0 0 0 0 0 0 0 HB2 HB1 HB0 0 HA2 HA1 HA0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HB2 to HB0:

HA2 to HA0:

Character vertical size control B(18 to 32 dots in 2-dot units)

Character vertical size control A(18 to 32 dots in 2-dot units)

580

CHAPTER 18 OSDC

18.4.8 Shaded Background Frame Color Control (Command 6-1)

This command controls the frame color of a shaded background.

Command 6-1 (Shaded Background Frame Color Control)

Address: 014H

Format

[Function]

Command 6-1 controls the frame color of a shaded background.

[Supplement]

• This command sets the frame colors of the character for which shaded character backgrounddisplay has been specified (MM1 = 1) by command 1 and of the shaded background for whichshaded background display has been specified (LM1 = 1) by command 4.

• Table 18.4-2 shows the sections of the shaded background frame to be displayed in highlightand shadow colors.

0 0 0 0 0 0 0 0 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BH3 to BH0:

BS3 to BS0:

Shaded background frame highlight color(From among 16 colors)Shaded background frameshadow color(From among 16 colors)

Table 18.4-2 Shaded Background Frame Sections to be Displayed in Highlight and Shadow Colors

Character background Shaded background convexed display

Line background

Shaded background concaved display

Line background

Shaded background concaved display

Highlight color on shaded background frame

Bottom and right edges

Top and left edges Bottom edge Top edge

Shadow color on shaded background frame

Top and left edges

Bottom and right edges

Top edge Bottom edge

581

CHAPTER 18 OSDC

18.4.9 Transparent/Translucent Color Control (Command 6-2)

Command 6-2 controls transparent and translucent colors.

Command 6-2 (Transparent/Translucent Color Control)

Address: 016H

Format

[Function]

Command 6-2 controls transparent and translucent colors.

[Supplement]

• If an arbitrary color code is specified as a transparent color code (in bits TC3 to TC0) andtransparent color control is set to ON (TCC = 1), the display areas in the specified color can bemade void. The display on the lower layer is output in place of the display areas in thespecified color.

• If an arbitrary color code is specified as a translucent color code (in bits HC3 to HC0) andtranslucent color control is set to ON (HCC = 1), the display areas in the specified color can bemade void. At the same time, the translucent color display period signal can be output fromthe VOB2 pin. The display on the lower layer is output in place of the display areas in thespecified color.

Note:

The translucent color display period signal from the VOB2 pin is output for areas other than thecharacters, trimming, and graphics on the main screen.

0 0 0 0 0 0 TCC HCC TC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TCC:

HCC:

Transparent color control(0: OFF, 1: ON)

Translucent color control(0: OFF, 1: ON)

TC3 to TC0:

HC3 to HC0:

Transparent color code(From among 16 colors)

Translucent color code(From among 16 colors)

582

CHAPTER 18 OSDC

18.4.10 Graphic Color Control (Command 6-3)

This command replaces the code-specified graphic color by the character color or character trimming color.

Command 6-3 (Graphic Color Control)

Address: 018H

Format

[Function]

Command 6-3 replaces the specified color of graphic characters by the character color orcharacter trimming color.

[Supplement]

• When bit GFC is set to 1, this command replaces the color (specified with bits GF3 to GF0) ofgraphic characters by the trimming color specified with bits LF3 to LF0 of the line control dataset 1 command (command 3).

• When bit GCC is set to 1, this command replaces the color (specified with bits GC3 to GC0) ofgraphic characters by the character color specified with bits MC3 to MC0 of the line data set 1command (command 1).

• Replacement by the specified trimming color has priority over transparent color control if:graphic color/trimming color replace control is ON (bit GFC = 1) and transparent color controlis ON (bit TCC of transparent/translucent color control command [command 6-2] = 1) and thecode of the color to be replaced by the graphic color/the trimming color is the same as thetransparent color code specified with bits TC3 to TC0 of the transparent/translucent colorcontrol command (command 6-2).

• Transparent color control has priority over replacement by the specified trimming color and thecolor on the lower layer is displayed if: graphic color/trimming color replace control is ON (bitGFC = 1) and transparent color control is ON (bit TCC of the transparent/translucent colorcontrol command [command 6-2] = 1) and the code of the trimming color (specified with bitsLF3 to LF0 of the line control data set 1 command [command 3]) to be replaced is the sameas the transparent color code specified with bits TC3 to TC0 of the transparent/translucentcolor control command (command 6-2).

0 0 0 0 0 0 GFC GCC GF3 GF2 GF1 GF0 GC3 GC2 GC1 GC0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GFC:

GCC:

Graphic color/trimming color replace control(0: OFF, 1: ON)

Graphic color/character color replace control(0: OFF, 1: ON)

GF3 to GF0:

GC3 to GC0:

Code of character to be replaced by trimming color(From among 16 colors)

Code of character to be replaced by character color(From among 16 colors)

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CHAPTER 18 OSDC

• Replacement by the specified character color has priority over the transparent color control if:graphic color/character color replace control is ON (bit GCC = 1) and transparent color controlis ON (bit TCC of the transparent/translucent color control command [command 6-2] = 1) andthe code of the color to be replaced by the graphic color/ the character color is the same asthe transparent color code specified with bits TC3 to TC0 of the transparent/translucent colorcontrol command (command 6-2).

• Transparent color control has priority over replacement by the specified character color andthe color on the lower layer is displayed if: graphic color/character color replace control is ON(bit GCC = 1) and transparent color control is ON (bit TCC of the transparent/translucent colorcontrol command [command 6-2] = 1) and the code of the character color (specified with bitsMC3 to MC0 of the character data set 1 command [command 1]) to be replaced is the sameas the transparent color code specified with bits TC3 to TC0 of the transparent/translucentcolor control command (command 6-2).

• Specify the codes of colors to be replaced by the character color (bits GC3 to GC0) that aredifferent from the codes of colors to be replaced by the trimming color (bits GF3 to GF0) if:graphic color/character color replace control is ON (bit GCC = 1) and graphic color/trimmingcolor replace control is ON (bit GFC = 1).

Note:

This command applies only to the colors of graphic characters on the main screen.

The colors of sprite characters and those of screen background character dots are not affected bythis command.

584

CHAPTER 18 OSDC

18.4.11 Screen Background Character Control (Commands 7-1 and 7-3)

Commands 7-1 and 7-3 control screen background characters and the screen background color.

Command 7-1 (Screen Background Character Control 1)

Address: 01AH

Format

[Function]

Command 7-1 controls screen background characters.

[Supplement]

• Screen background characters specified by command 7-1 are displayed when screenbackground character output control is set to ON (PDS = 1) in the screen output control 1Acommand (command 5-00).

• The vertical size of screen background characters can be specified with the screenbackground character vertical size control bits (bits PH2 to PH0) of the screen backgroundcharacter control 2 command (command 7-3).

• The screen background character operation control is stopped the operation (PCUT=1), thehorizontal display position offset value of the main screen etc. is allowed to reduce.

PCUT 0 PD1 PD0 PM10 PM9 PM8 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD1, PD0: Screen background character configuration control(0, 0: One character)(0, 1: Two characters horizontally)(1, 0: Two characters vertically)(1, 1: Two characters vertically by two characters horizontally)

PM11 to PM0: Screen background character code(000H to FFCH for 1024 different characters)

PCUT: Screen background character operation control(0: screen background character display is enabled)(1: screen background character display is stopped)

PM11

585

CHAPTER 18 OSDC

Notes:

• Only graphic characters can be displayed as screen background characters.

• The graphic color/trimming color replace control and graphic color/character color replace controlby graphic color control command (command 6-3) are not effective for the graphic colors ofscreen background characters.

• When the display control is stopped by the screen background character operation control, thescreen background character output control of the screen output control 1 (command 5-00) is setto OFF (PDS=0).

Command 7-3 (Screen Background Character Control 2)

Address: 01CH

Format

[Function]

Command 7-3 controls screen background characters and the screen background color.

[Supplement]

• The screen background color specified by command 7-3 is displayed when screenbackground output control is set to ON (UDS = 1) in the screen output control 1A command(command 5-00).

• Screen background characters are displayed when screen background character outputcontrol is set to ON (PDS = 1) in the screen output control 1A command (command 5-00).

0 0 0 0 0 0 0 0 0 PH2 PH1 PH0 U3 U2 U1 U0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PH2 to PH0:

U3 to U0:

Screen background character vertical size control(18-32 dots in 2-dot units)

Screen background color(From among 16 colors)

586

CHAPTER 18 OSDC

18.4.12 Sprite Character Control (Commands 8-1, 8-2, 9-0 and 9-1)

Commands 8-1, 8-2, 9-0, and 9-1 control sprite characters.

Command 8-1 (Sprite Character Control 1)

Address: 01EH

Format

[Function]

Command 8-1 controls sprite characters.

[Supplement]

• Sprite characters are displayed when sprite character output control is set to ON (SDS = 1) inthe screen output control 1A command (command 5-00).

• Sprite character display positions are specified by the sprite character control 3 command(command 9-0) and sprite character control 4 command (command 9-1).

• The vertical size of sprite characters is specified with the sprite character vertical size controlbits (bits SH2 to SH0) of the sprite character control 2 command (command 8-2).

• Whether to turn on blinking of sprite characters is specified by the sprite character blink controlbit (bit SBL) of the sprite character control 2 command (command 8-2).

• The sprite character blink cycle and blink duty ratio depend on the settings of bits BT1, BT0,BD1, and BD0 of command 5-1.

• The sprite operation control is stopped the operation(SCUT=1), the horizontal display positionoffset value of the main screen etc. is allowed.

SCUT 0 SD1 SD0 SM10 SM9 SM8 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SD1, SD0: Sprite character configuration control(0, 0: 1 character)(0, 1: Horizontal set of 2 characters)(1, 0: Vertical set of 2 characters)(1, 1: 2 × 2 characters)

SM11 to SM0: Sprite character code(000H to FFCH for 1024 different characters)

SCUT: Sprite operation control(0: sprite display is enabled.)(1: sprite control operation is stopped.)

SM11

587

CHAPTER 18 OSDC

Notes:

• Only graphic characters can be displayed as sprite characters.

• Graphic color/trimming color replace control and graphic color/character color replace control bythe graphic color control command (command 6-3) are not effective for the graphic colors of spritecharacters.

• When the display is stopped by the sprite operation control, the sprite character output control ofthe screen output control 1 (command 5-00) is set to OFF (SDS=0).


Address: 020H

Format

[Function]

Command 8-2 controls sprite characters.

[Supplement]

For sprite settings, see [Supplement] for command 8-1.


Address: 022H

Format

[Function]

Command 9-0 controls the sprite character vertical display position.

[Supplement]


0 0 0 0 0 0 0 SBL 0 SH2 SH1 SH0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SBL: Sprite character blink control(0: OFF, 1: ON)

SH2 to SH0: Sprite character vertical size control (18-32 dots in 2-dot units)

0 0 0 0 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SY9 to SY0: Sprite character vertical display position control(0 to 2046 in 2-dot units)

588

CHAPTER 18 OSDC


Address: 024H

Format

[Function]

Command 9-1 controls the sprite character horizontal display position.

Set value of horizontal display position = (SX10, SX9, SX8, SX7, SX6, SX5, SX4, SX3) × 12 + (SX2, SX1, SX0) × 2 [dot]

Note: However, setting of (SX2, SX1, SX0) = (1, 1, 0) or (1, 1, 1) is prohibited.

[Supplement]


0 0 0 0 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SX10 to SX0: Sprite character horizontal display position control(0 to 3070 in 2-dot units)

SX10

589

CHAPTER 18 OSDC

18.4.13 Synchronization Control (Command 11-0)

Command 11-0 controls synchronization of display.

Command 11-0 (Synchronization Control)

Address: 026H

Format

[Function]

Command 11-0 controls the synchronization system (for interlaced or noninterlaced display).

[Supplement]

Setting of the field correction control bit (bit FC) is valid only for interlaced display (IN = 0).

00 0 0 0 0 0 0 0 0 IN 0 FC 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IN: Synchronization control(0: Interlaced)(1: Noninterlaced)

FC: Field correction control(0: No correction, 1: Correction)

590

CHAPTER 18 OSDC

18.4.14 I/O Pin Control (Commands 13-0 and 13-1)

Commands 13-0 and 13-1 control input/output pins.

Command 13-0 (I/O Pin Control)

Address: 02EH

Format

[Function]

Command 13-0 controls input/output pins.

[Supplement]

• The HSYNC edge selection bit for vertical synchronization detection (VHE) can avoid verticaldancing due to the input timing of vertical and horizontal sync signals. For details, see"18.3.2.1 Vertical Synchronization Control".

• The logic control for display color signal output by the OSDC inverts the color information logicset before palette input. This control does not apply to the color information that is convertedby the palette.

0 0 0 0 0 0 0 0 0 0 0 0 0 OHX OBX OCX

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OCX:

OBX:

OHX:

Logic control for display color signal output(0: Positive logic, 1: Negative logic)

Logic control for display output period signal output(0: Positive logic, 1: Negative logic)

Logic control for translucent display period signal output(0: Positive logic, 1: Negative logic)

591

CHAPTER 18 OSDC

Command 13-1 (I/O Pin Control 2)

Address: 030H

Format

[Function]

This command controls the input/output pins.

[Supplement]

0 0 0 0 0 0 0 VHE HE 0 0 0 0 IHX IVX 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VHE:

HE:

HSYNC edge selection for vertical synchronization detection(0: Rising edge, 1: Falling edge)

Edge selection for horizontal synchronization operation(0: Falling edge, 1: Rising edge)

IHX:

IVX:

Logic control for horizontal synchronization signal input(0: Negative logic, 1: Positive logic)

Logic control for vertical synchronization signal input(0: Negative logic, 1: Positive logic)

592

CHAPTER 18 OSDC

18.4.15 Display Period Control (Commands 14-0 to 14-3)

Commands 14-0 to 14-3 control the display periods.

Command 14-0 (Display Period Control 1)

Address: 032H

Format

[Function]

Command 14-0 controls the timing at which to start vertical display.

0 0 0 0 0 DYS10 DYS9 DYS8 DYS7 DYS6 DYS5 DYS4 DYS3 DYS2 DYS1 DYS0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DYS10 to DYS0: Vertical display start control(0 to 2,047, in 1-dot units)

593

CHAPTER 18 OSDC


Address: 034H

Format

[Function]

Command 14-1 controls the timing at which to end vertical display.


Address: 036H

Format

[Function]

Command 14-2 controls the timing at which to start horizontal display.

0 0 0 0 0 DYE10 DYE9 DYE8 DYE7 DYE6 DYE5 DYE4 DYE3 DYE2 DYE1 DYE0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DYE10 to DYE0: Vertical display end control(0 to 2,047, in 1-dot units)

0 0 0 0 0 DXS10 DXS9 DXS8 DXS7 DXS6 DXS5 DXS4 DXS3 DXS2 DXS1 DXS0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DXS10 to DXS0: Horizontal display start control(0 to 2,047, in 1-dot units)

594

CHAPTER 18 OSDC


Address: 038H

Format

[Function]

Command 14-3 controls the timing at which to end horizontal display.

0 0 0 0 0 DXE10 DXE9 DXE8 DXE7 DXE6 DXE5 DXE4 DXE3 DXE2 DXE1 DXE0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DXE10 to DXE0: Horizontal display end control(0 to 2,047, in 1-dot units)

595

CHAPTER 18 OSDC


Command 15-0 controls the interrupts.

Command 15-0 (Interrupt Control)

Address: 03AH

Format

[Function]

Command 15-0 controls the interrupts.

To clear a set flag (FIF, LIF, or VIF), write 0 to the flag.

0 0 0 0 0 FIF LIF VIF 0 0 0 0 0 FIE LIE VIE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIF:

LIF:

VIF:

FIE:

LIE:

VIE:

VRAM fill end flag(0: VRAM fill end not detected, 1: VRAM fill end detected)

Line display end flag(0: Line display end not detected, 1: Line display end detected)

VSYNC detection flag(0: VSYNC not detected, 1: VSYNC detected)

VRAM fill end interrupt control(0: Interrupt disabled, 1: Interrupt enabled)

Line display end interrupt control(0: Interrupt disabled, 1: Interrupt enabled)

VSYNC detection interrupt control(0: Interrupt disabled, 1: Interrupt enabled)

596

CHAPTER 18 OSDC

18.4.17 Palette Control (Commands 16-0 to 16-15)

Commands 16-0 to 16-15 control the values of palettes.

Commands 16-0 to 16-15 (Palette Control)

Address: See the table below.

Format

PLR2 to PLR0: Values of red color palette

PLG2 to PLG0: Values of green color palette

PLB2 to PLB0: Values of blue color palette

[Function]

These commands control the values of palettes.

[Supplement]

• RGB colors can be assigned to 4-bit color codes (0 to F) of the OSDC by specifying palettevalues in commands 16-0 to 16-15.

Table 18.4-3 Palette Control

Address (Low-order

9 bits)

Command No.

Data

15-11 10 9 8 7 6 5 4 3 2 1 0

0 3C 16-0 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0

0 3E 16-1 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0

0 40 16-2 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0





0 4A 16-7 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0









597

CHAPTER 18 OSDC

• There are the following types of color codes:Character colors (MC3 to MC0)Character background colors (MB3 to MB0)Trimming colors (LF3 to LF0)Line background colors (L3 to L0)Shaded background frame colors (BH3 to BH0 and BS3 to BS0)Graphic color control (GF3 to GF0 and GC3 to GC0)Screen background colors (U3 to U0)Graphic colors

598

CHAPTER 18 OSDC

18.4.18 OSDC Operation Control (Commands 17-0 and 17-1)

Commands 17-0 and 17-1 control the initial operation of the OSDC.

Command 17-0 (OSDC Operation Control 1)

Address: 05CH

Format

[Function]

Command 17-0 controls access to OSDC-related resources.

[Supplement]

The OSDC enable bit of command 17-1 must be set to 1 before setting the DAC enable bit ofcommand 17-0.

0 0 0 0 0 0 0 0 0 0 0 DCK 0 0 0 DPD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DCK:

DPD:

Input dot clock selection control(0: Input of external clock, 1: Input of dot clock generated by internal PLL)

DAC ENABLE(0: OSDC DAC access OFF, 1: OSDC DAC access ON)

599

CHAPTER 18 OSDC

Command 17-1 (OSDC Operation Control 2)

Address: 05EH

Format

[Function]

Command 17-1 controls the operation of the OSDC.

[Supplement]

• When analog output control or digital output control is set to ON, the VOB1 and VOB2 signals,which are common to the analog and digital systems, are output.

• To turn off the output of the VOB1 and VOB2 signals, analog output control and digital outputcontrol must both be set to OFF.

• The OSDC enable bit and CC operation bit must be set to 1 if and only if the external clock isnormally input or the internal PLL clock is normally generated.

• When issuing the display control command of CC screen, it is necessary to set the CCEN bit(CC operation ENABLE) to 1. (When CCEN bit is 0, the display control command of CCscreen is not accepted.)

0 0 0 0 0 0 FHS1 0 0 CCEN OSDEN 0 FHO DGO ANO FHS0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ANO:

FHO:

OSDEN:

Analog output control(0: Output OFF, 1: Output ON)

FH output control(0: Output OFF, 1: Output ON)

OSDC enable(0: OSDC operation OFF, 1: OSDC operation ON)

DGO: Digital output control(0: Output OFF, 1: Output ON)

CCEN: CC operation ENABLE(0: CC operation OFF, 1: CC operation ON)

FHS1, FHS0: FH output selection control(00: FH1 [PLLA-FH], 01: FH2 [PLLB-FH], 10: FH3 [PLLC-FH], 11: Setting prohibited)

600

CHAPTER 18 OSDC

18.4.19 PLLA Clock Control (Commands 18-0 to 18-3)

Command 18-0, command 18-1, command 18-2 and command 18-3 are the commands that control the clock of PLLA.

Command 18-0 (PLLA Clock Control 1-1)

Address: 060H

Format

[Function]

This command controls the clock of PLLA (prescaler A[1/(2 × DAP):CKA]).

Command 18-1 (PLLA Clock Control 1-2)

Address: 062H

Format

[Function]

This command controls the clock of PLLA (prescaler B[1/(2 × DBP):CKB]).

0 0 0 0 0 0 0 0 0 0 0 DAP4 DAP3 DAP2 DAP1 DAP0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DAP4-DAP0: Number of PLLA clock dividing frequency 1(Unit of dividing frequency: MIN=1 dividing frequency, MAX=62 dividing frequency)

0 0 0 0 0 0 0 0 0 0 0 DBP4 DBP3 DBP2 DBP1 DBP0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DBP4-DBP0: Number of PLLA clock dividing frequency 2(Unit of dividing frequency: MIN=1 dividing frequency, MAX=62 dividing frequency)

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CHAPTER 18 OSDC

Command 18-2(PLLA Clock Control 2)

Address: 064H

Format

[Function]

This command adjusts the frequency of the using dot clock.

[Supplement]

This command sets the value divided until the horizontal synchronizing signal cycle to the clockgenerated with prescaler 1 (command 18-0:DAP4-DAP0).

Command 18-3(PLLA Clock Control 3)

Address: 066H

Format

[Function]

This command controls the oscillation of PLLA.

0 0 0 0 DKA4DKA5 DKA3 DKA2 DKA1DKA9DKA10DKA11 DKA8 DKA7 DKA6 DKA0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DKA11-DKA0: Number of clock dividing frequency(1 clock unit: MIN=129 clocks, MAX=4096 clocks)

0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLLA VCO selection control(0,0,0: VC01)(0,0,1: VC02)(0,1,0: VC03)(0,1,1: VC04)(1,0,0: VC05)(1,0,1: VC06)(Other setting prohibited.)PLLA charge pump control(0: OFF, 1: ON) BIAS current control of PLLA charge pump(0,0: Approx. 100 µA)(0,1: Approx. 500 µA)(1,0: Approx. 1mA)(1,1: Setting prohibited.)

VCOA: VSLA2-VSLA0:

CPEA:

CHGA1, CHGA0:

PDEA:

0 0 0 0 VSLA0VSLA1 CHGA1 CHGA0 CPEAVCOA VSLA2 PDEA

PLLA phase comparator control(0: OFF, 1: ON)

PLLA VC0 oscillation control(0: OFF, 1: ON)

602

CHAPTER 18 OSDC

18.4.20 PLLB Clock Control (Commands 18-4 to 18-7)

Command 18-4, command 18-5, command 18-6 and command 18-7 are the commands that control the clock of PLLB.

Command 18-4(PLLB Clock Control 1-1)

Address: 068H

Format

[Function]

This command controls the clock of PLLB (prescaler C[1/(2 × DCP):CKC]).

Command 18-5(PLLB Clock Control 1-2)

Address: 06AH

Format

[Function]

This command controls the clock of PLLB (prescaler D[1/(2 × DDP):CKD]).

0 0 0 0 0 0 0 0 0 0 0 DCP4 DCP3 DCP2 DCP1 DCP0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DCP4-DCP0: Number of PLLB clock dividing frequency 1(Unit of dividing frequency: MIN=1 dividing frequency, MAX=62 dividing frequency)

0 0 0 0 0 0 0 0 0 0 0 DDP4 DDP3 DDP2 DDP1 DDP0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DDP4-DDP0: Number of PLLB clock dividing frequency 2(Unit of dividing frequency: MIN=1 dividing frequency, MAX=62 dividing frequency)

603

CHAPTER 18 OSDC

Command 18-6(PLLB Clock Control 2)

Address: 06CH

Format

[Function]


[Supplement]

This command sets the value divided until the horizontal synchronizing signal cycle to the clockgenerated with prescaler C (command 18-4:DCP4-DCP0).

Command 18-7(PLLB Clock Control 3)

Address: 06EH

Format

[Function]

This command controls the oscillation of PLLB.

0 0 0 0 DKB4DKB5 DKB3 DKB2 DKB1DKB9DKB10DKB11 DKB8 DKB7 DKB6 DKB0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DKB11-DKB0: Number of clock dividing frequency(1 clock unit: MIN=129 clocks, MAX=4096 clocks)

0 0 0 0 0 0 0 0 VSLB0VSLB1 CHGB1 CHGB0 CPEBVCOB VSLB2 PDEB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLLB VCO selection control(0,0,0: VC01) (0,0,1: VC02)(0,1,0: VC03)(0,1,1: VC04)(1,0,0: VC05)(1,0,1: VC06)(Other setting prohibited.)PLLB charge pump control(0: OFF, 1: ON) BIAS current control of PLLB charge pump(0,0: Approx. 100 µA)(0,1: Approx. 500 µA)(1,0: Approx. 1mA)(1,1: Setting prohibited.)

VSLB2-VSLB0:

CPEB:

CHGB1,CHGB0:

VCOB:

PDEB: PLLB phase comparator control(0: OFF, 1: ON)

PLLB VC0 oscillation control(0: OFF, 1: ON)

604

CHAPTER 18 OSDC

18.4.21 PLLC Clock Control (Commands 18-8 to 18-11)

Command 18-8, command 18-9, command 18-10 and command 18-11 are the commands that control the clock of PLLC.

Command 18-8(PLLC Clock Control 1-1)

Address: 070H

Format

[Function]

This command controls the clock of PLLC (prescaler E[1/(2 × DEP):CKE]).

Command 18-9(PLLC Clock Control 1-2)

Address: 072H

Format

[Function]

This command controls the clock of PLLC (prescaler F[1/(2 × DFP):CKF]).

Command 18-10(PLLC Clock Control 2)

Address: 074H

0 0 0 0 0 0 0 0 0 0 0 DEP4 DEP3 DEP2 DEP1 DEP0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DEP4-DEP0: Number of PLLC clock dividing frequency 1(Unit of dividing frequency: MIN=1 dividing frequency, MAX=62 dividing frequency)

0 0 0 0 0 0 0 0 0 0 0 DFP4 DFP3 DFP2 DFP1 DFP0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DFP4-DFP0: Number of PLLF clock dividing frequency 2(Unit of dividing frequency: MIN=1 dividing frequency, MAX=62 dividing frequency)

605

CHAPTER 18 OSDC

Format

[Function]


[Supplement]

This command sets the value divided until the horizontal synchronizing signal cycle to the clockgenerated with prescaler E (command 18-8:DEP4-DEP0).

Command 18-11(PLLC Clock Control 3)

Address: 076H

Format

[Function]

This command controls the oscillation of PLLC.

0 0 0 0 DKC4DKC5 DKC3 DKC2 DKC1DKC9DKC10DKC11 DKC8 DKC7 DKC6 DKC0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DKC11-DKC0: Number of clock dividing frequency(1 clock unit: MIN=129 clocks, MAX=4096 clocks)

0 0 0 0 0 0 0 0 VSLC0VSLC1 CHGC1 CHGC0 CPECVCOC VSLC2 PDEC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLLC VCO selection control(0,0,0: VC01) (0,0,1: VC02)(0,1,0: VC03)(0,1,1: VC04)(1,0,0: VC05)(1,0,1: VC06)(Other setting prohibited.)PLLC charge pump control(0: OFF, 1: ON) BIAS current control of PLLC charge pump(0,0: Approx. 100 µA)(0,1: Approx. 500 µA)(1,0: Approx. 1mA)(1,1: Setting prohibited.)

VSLC2-VSLC0:

CPEC:

CHGC1,CHGC0:

VCOC:

PDEC: PLLC phase comparator control(0: OFF, 1: ON)

PLLC VC0 oscillation control(0: OFF, 1: ON)

606

CHAPTER 18 OSDC

18.4.22 Clock Selection Control (Commands 18-12 to 18-13)

Command 18-12 and command 18-13 are the commands that control the clock.

Command 18-12(Clock Selection Control 1)

Address: 078H

Format

[Function]

This command controls PLL input clock selection and the dot clock output pin.

0 0 0 0 0 HSPLC1 HSPLC0 HSPLB1 HSPLB0 HSPLA1 HSPLA0 HSOSX DHRSC DHRSB DHRSA DCO

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DC0: Dot clock output pin control(0: OFF, 1: ON)

DHRSA: PLLA phase comparison edge selection(0: Rising edge of horizontal synchronizing signal)* Back porch side edge(1: Falling edge of horizontal synchronizing signal)* Front porch side edge

DHRSB: PLLB phase comparison edge selection(0: Rising edge of horizontal synchronizing signal)* Back porch side edge(1: Falling edge of horizontal synchronizing signal)* Front porch side edge

DHRSC: PLLC phase comparison edge selection(0: Rising edge of horizontal synchronizing signal)* Back porch side edge(1: Falling edge of horizontal synchronizing signal)* Front porch side edge

HSOSX: HSYNC selection 1 of PLLA input(0: OSDC HSYNC selection)* HSYNC of selected by HSPLA set HSYNC of output from OSDC into PLLA.(1: HSPLA HSYNC selection)* HSYNC of selected by HSPLA is input directly to PLLA.

HSPLA1, HSPLA0: HSYNC selection of PLLB input(00: HSYNCA selection)(01: HSYNCB selection)(10: HSYNCC selection)(11: Setting prohibited.)

HSPLB1, HSPLB0: HSYNC selection of PLLA input(00: HSYNCA selection)(01: HSYNCB selection)(10: HSYNCC selection)(11: Setting prohibited.)

HSPLC1, HSPLC0: HSYNC selection of PLLC input(00: HSYNCA selection)(01: HSYNCB selection)(10: HSYNCC selection)(11: Setting prohibited.)

607

CHAPTER 18 OSDC

Command 18-3(Clock Selection Control 2)

Address: 07AH

Format

[Function]

This command controls PLL output clock selection.

0 0 0 0 0 SSLB2 SSLB1 SSLB0 SSLA2 SSLA1 SSLA0 SDOT2 SDOT1 SDOT00 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDOT2, SDOT1, SDOT0: OSDC(DOTCLK)PLL clock selection(0,0,0: 1/(2*DPA)[CKA] output)(0,0,1: 1/(2*DPB)[CKB] output)(0,1,0: 1/(2*DPC)[CKC] output)(0,1,1: 1/(2*DPD)[CKD] output)(1,0,0: 1/(2*DPE)[CKE] output)(1,0,1: 1/(2*DPF)[CKF] output)(1,1,0: HSYNCA[CKF] output)(1,1,1: Setting prohibited.)

SSLA2, SSLA1, SSLA0: Slicer A(SLYCLKB)PLL clock selection(0,0,0: 1/(2*DPA)[CKA] output)(0,0,1: 1/(2*DPB)[CKB] output)(0,1,0: 1/(2*DPC)[CKC] output)(0,1,1: 1/(2*DPC)[CKC] output)(1,0,0: 1/(2*DPE)[CKE] output)(1,0,1: 1/(2*DPF)[CKF] output)(1,1,0: HSYNCA[CKF] output)(1,1,1: Setting prohibited.)

SSLB2, SSLB1, SSLB0: Slicer A(SLYCLKA)PLL clock selection(0,0,0: 1/(2*DPA)[CKA] output)(0,0,1: 1/(2*DPB)[CKB] output)(0,1,0: 1/(2*DPC)[CKC] output)(0,1,1: 1/(2*DPD)[CKD] output)(1,0,0: 1/(2*DPE)[CKE] output)(1,0,1: 1/(2*DPF)[CKF] output)(1,1,0: HSYNCA[CKF] output)(1,1,1: Setting prohibited.)

608

CHAPTER 18 OSDC

18.5 Display Control Command (CC)

This chapter explains the display control command of the OSDC CC screen.

Display Control Command

18.5.1 CC Screen and Display Control Command List

18.5.2 VRAM Write Address Setting (Command 0)

18.5.3 Character Data Setting (Command 1, Command 2)

18.5.4 Line Control Data Setting (Command 3, Command 4)

18.5.5 Display Output Control (Command 5-00, Command 5-1)

18.5.6 Display Position Control (Command 5-2, Command 5-3)


18.5.8 Transparent Color Control (Command 6-2)

18.5.9 Display Period Control (Command 14-0, 14-1, 14-2, 14-3)


18.5.11 Palette Control (Command 16-0 to Command 16-15)

609

CHAPTER 18 OSDC

18.5.1 CC Screen and Display Control Command List

Table 18.5-1 shows the list of the display control command.

Display Control Command List

Note:

Each bit of DSP and MCC for display output control 1 and OHX, OBX, and OCX bit of I/O pin control1 are initialized to "0" by the reset input (high level signal input to RESET pin). Other register bits andcontent of VRAM are undefined.

Please set all the register bits and all VRAM (character data and line control data) after reset input.

When the display control command of the CC screen is issued, it is necessary to set CCEN (CCoperation ENABLE) bit of the main/OSDC operation control: 17 (OSDC operation control 2) to 1. (IfCCEN bit is equal to 0, the display control command of the CC screen is not accepted.)

Table 18.5-1 Display Control Command List

Address lower 9bit

OSDCcommand

No.

DataFunction

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 00 0 FL AY3 AY2 AY1 AY0 AX5 AX4 AX3 AX2 AX1 AX0 VRAM address

1 02 1 MIT MUL MBL MBB MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0 Character data setting 1

1 04 2 MR MG M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Character data setting 2

1 06 3 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0 Line control data setting 1

1 08 4 LDS LGY1 LGY0 LGX1 LGX0 LD LE LM1 LM0 L3 L2 L1 L0 Line control data setting 2

1 0A 5-00 SDS UDS PDS DSP Screen output control 1

1 0C 5-1 FM1 FM0 BT1 BT0 BD1 BD0 Screen output control 2

1 0E 5-2 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0Vertical display position control

1 10 5-3 X8 X7 X6 X5 X4 X3 X2 X1 X0Horizontal display position control

1 12 6-0 HB2 HB1 HB0 HA2 HA1 HA0 Character vertical size control

1 16 6-2 TCC HCC TC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0Transparency/translucent color control

1 32 14-0 DYS10 DYS9 DYS8 DYS7 DYS6 DYS5 DYS4 DYS3 DYS2 DYS1 DYS0 Display period control 1

1 34 14-1 DYE10 DYE9 DYE8 DYE7 DYE6 DYE5 DYE4 DYE3 DYE2 DYE1 DYE0 Display period control 2

1 36 14-2 DYS10 DYS9 DYS8 DYS7 DYS6 DYS5 DYS4 DYS3 DYS2 DYS1 DYS0 Display period control 3

1 38 14-3 DXE10 DXE9 DXE8 DXE7 DXE6 DXE5 DXE4 DXE3 DXE2 DXE1 DXE0 Display period control 4

1 3A 15-0 FIF LIF VIF FIE LIE VIE Interrupt control

















610

CHAPTER 18 OSDC

18.5.2 VRAM Write Address Setting (Command 0)

Command 0 is a command that specifies the setting of the writing address of VRAM and VRAM filter.

Command 0 (VRAM Write Address Setting)

Address: 100H

Format

[Function]

Command 0 is a command that specifies the setting of the writing address of VRAM and VRAMfilter.This command sets line/row address before the character data setting (issuring command 1, 2)and sets the line address before the line control data setting (issuring command 3, 4).

VRAM filter starts by executing the character data setting 2 (command 2)

[Supplement]

• In a usual writing (write of one character data or one-line control data), please set the VRAMfilter specification to OFF(FL=0).

• After executing the character data setting 2 (command 2), the VRAM writing address set bythis command issue is automatically incremented.(The following of the final row is incremented to next line first row. The following of the finalline final row is incremented to the top of first row.)

• The VRAM filter function is a function to set the same character data that specifies characterdata setting by 1 and 2 (command 1 and 2) to the character VRAM from line and row addressspecified by command 0 to the final line (16 lines) and the final rows (42 rows). VRAM filterstarts by issuing the character data setting 2 (command 2). After execution ends, the VRAMfilter interruption can be generated. Please do not issue command 1-4 while executing VRAMfilter.

Notes:

• Row address (AX5-AX0) is disregarded at the line control data setting (command 3 and fourissues). After the line control data set, the automatic address increment is not done.

• The VRAM filter specification is effective only at the character data setting (command 1 and 2).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FL 0 0 0 AY3 AY2 AY1 AY0 0 AX4 AX3 AX2 AX1 AX0 AX5AX6

AY3-AY0: Line address (0-FH)

AX5 to AX0: Row address (0-29H)

FL: VRAM filter setting (0: OFF, 1: ON)

611

CHAPTER 18 OSDC

18.5.3 Character Data Setting (Command 1, Command 2)

VRAM is set by executing command 2 after setting the character data by command 1, and it displays it on the screen.

Command 1(Character Data Setting 1)

Address: 102H

Format

[Function]

This command sets the character data. VRAM is set by executing the character data setting 2(command 2), and it displays it on the screen.

[Supplement]

• A character color, a character background color, a character background type, a characterhorizontal size, italics display, and an underline display can be set by combining respectivelyfreely in each character.

• A character horizontal size is fixed 18 dots.• The blink is displayed by setting blink control ON according to the content of BT1 of screen

output control 2(command 5-1), BT0, BD1, and the BD0 bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIT MUL MBL MBB 0 0 0 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0

MC3 - MC0:

MB3 - MB0:

MM1, MM0:

MBL, MBB:

MIT:

Character color(16 colors)

Character background color(16 colors)

Character background control( 0: OFF)(1: solid display)

Blink control(0, 0: Blink OFF)(0, 1: Character background blink ON)(1, 0: Character/framing dot blink ON)(1, 1: Character/framing dot/character background blink ON)

Italics control(0: Italics OFF)(1: Italics ON)

Note: Character horizontal size (Fixed 18 dots)

MUL: Underline control(0: Underline OFF)(1: Underline ON)

612

CHAPTER 18 OSDC

Command 2(Character Data Setting 2)

Address: 104H

Format

[Function]

This command writes this data setting in VRAM specified by the VRAM writing address setting(command 0) with the character data that sets the character data setting 1 (command 1).

After this command is executed, the VRAM writing address is automatically incremented.

Note:

When the power supply is turned on, the content of VRAM becomes undefine. Please set all VRAMdata before it begins to display it.

0 00 0 M10M11 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

M11 to M0: Character code(000H to FFFH: 4096 character type)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

613

CHAPTER 18 OSDC

18.5.4 Line Control Data Setting (Command 3, Command 4)

Line VRAM is set by executing command 4 after setting the line control data by command 3, and it displays it on the screen.

Command 3(Line Control Data Setting 1)

Address: 106H

Format

[Function]

This command sets the line control data. Line VRAM is set by executing the line control datasetting 2 (command 4), and it displays it in the screen.

[Supplement]

• Character vertical size A/B selected by character vertical size kind control (LHS bit) content isset by the character vertical size control (command 6-0).

• The framing form is set by the framing form control (FM1 and FM0 bit) of screen output control2 (command 5-1).

0 0 0 LHS 0 LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LHS:

LW2 - LW0:

LF3 - LF0:

Character vertical size type control(0: Character vertical size A)(1: Character vertical size B)

Line spacing control(0 to 14 dots, 2-dot unit)

Framing color(16 colors)

LFD, LFC:

LFB, LFA:

Framing output control(0, 0: All OFF)(0, 1: Only the character of the character background none is framed ON.)(1, 0: Framing output ON)(1, 1: Framing output ON)

Framing control(0, 0: Framing OFF)(0, 1: Right framing)(1, 0: Left framing)(1, 1: Right and left framing)

614

CHAPTER 18 OSDC

Command 4(Line Control Data Setting 2)

Address: 108H

Format

[Function]

This command writes this data setting in line VRAM of line address specified by the VRAM writingaddress setting (command 0) with the line control data that sets the line control data setting 1(command 3).

After this command is executed, the VRAM writing address is automatically incremented.

Notes:

• When the power supply is turned on, the content of VRAM becomes undefine. Please set allVRAM data before it begins to display it.

• An automatic increment in the VRAM writing address by this command issue is not done. TheVRAM writing address should be set (command 0) in each line that sets the line control data.

0 0 0 LDS LGY1 LGY0 LGX1 LGX0 0 LE 0 LM0 L3 L2 L1 L0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LDS:

LGY1, LGY0:

LGX1, LGX0:

Line character output control(0: OFF, 1: ON)

Line hight expansion control(0, 0: Normal)(0, 1: Twice in height)(1, 0: Setting prohibited)(1, 1: Four times in height)

Line width expansion control(0, 0: Normal)(0, 1: Twice in width)(1, 0: Setting prohibited)(1, 1: Four times in width)

LE:

LM1, LM0:

L3 - L0:

Character background enhancing control(0: Normal, 1: Extension)

Line background control( 0: OFF, 1: Solid-display)

Line background color(16 colors)

615

CHAPTER 18 OSDC

18.5.5 Display Output Control (Command 5-00, Command 5-1)

Command 5-00 and command 5-1 are the commands that control the screen display output.

Command 5-00 (Display Output Control 1)

Address: 10AH

Format

[Function]

This command controls the screen display output.

0 0 0 0 0 0 0 0 0 0 0 DSP 0 0 0 MCC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DSP:

MCC:

Sprite character output control(0: OFF, 1: ON)

MAIN,CC Screen priority control(0: MAIN screen priority control, 1: CC screen priority control)

616

CHAPTER 18 OSDC

Command 5-1 (Display Output Control 2)

Address: 10CH

Format

[Function]

This command controls the screen display output.

[Supplement]

The control at the blink cycle and the blink duty control control the character that is character dataset and specifies blink control by two (command 2)(MBL=1 setting) and the sprite character forwhich sprite character blink control is specified by sprite character control 2 (command 8-2)(SBL=1 setting).

0 0 0 0 0 0 FM1 FM0 BT1 BT0 BD1 BD0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BT1, BT0:

BD1, BD0:

Control at blink cycle(0, 0 : 16V)(0, 1 : 32V)(1, 0 : 48V)(1, 1 : 64V)

Blink duty control(0, 0: ON:OFF = 1:0 always display)(0, 1: ON:OFF = 1:1)(1, 0: ON:OFF = 1:3)(1, 1: ON:OFF = 3:1)

FM1, FM0: Framing form control(0, 0: 1 horizontal framing dot)(0, 1: 2 horizontal framing dots)(1, 0: Pattern background 1)(1, 1: Pattern background 2)

617

CHAPTER 18 OSDC

18.5.6 Display Position Control (Command 5-2, Command 5-3)

Command 5-2 is a command that controls the position of a vertical screen. Command 5-3 is a command that controls the position where the horizontal screen is displayed.

Command 5-2 (Vertical Display Position Control)

Address: 10EH

Format

[Function]

This command controls the position where the main screen vertical is displayed.

Command 5-3 (Horizontal Display Position Control)

Address: 110H

Format

[Function]

This command controls the position where the main screen the horizontal is displayed.

The horizontal display position and setting values= (X8, X7, X6, X5, X4, X3, X2) × 12 + (X0, X1) × 4 [dot]

Note: However, (X1, X0)=(1, 1) is setting prohibited.

0 0 0 0 0 0 Y8Y9 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Y9 - Y0: Vertical display position control(0-2046, 2-dot unit)

0 0 0 0 0 0 0 X8 X7 X6 X5 X4 X3 X2 X1 X0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X8 to X0: Horizontal display position control(0-1532 in 4-dot units)

618

CHAPTER 18 OSDC


Command 6-0 is a command that controls displaying vertical size A and B of the character.

Command 6-0 (Character Vertical Size Control)

Address: 112H

Format

[Function]

This command controls displaying vertical size A of the character and B.

[Supplement]

The main screen can be displayed by selecting character vertical size A/B of each line. Charactervertical size kind A/B is selected by character vertical size kind line data setting control of one(command 3)(LHS bit). Each A/B number of character representation vertical dots is set by thiscommand.

0 0 0 0 0 0 0 0 0 HB2 HB1 HB0 0 HA2 HA1 HA0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HB2 - HB0:

HA2 - HA0:

Character vertical size control B control(18 - 32 dots, 2-dot unit)

Character vertical size control A control(18 - 32 dots, 2-dot unit)

619

CHAPTER 18 OSDC

18.5.8 Transparent Color Control (Command 6-2)

Command 6-2 is a command that controls the transparent color.

Command 6-2 (Transparent Color Control)

Address: 116H

Format

[Function]

This command controls a transparent color and a translucent color.

[Supplement]

• An arbitrary color display part can be assumed to be non-display by setting the arbitrary colorcode to transparent color code (TC3-TC0) and doing transparent color control ON(TCC=1)setting. The arbitrary color part outputs the display of the subordinate position layer.

• An arbitrary color display part is made non-display by setting the arbitrary color code totranslucent color code (HC3-HC0) and doing translucent color control ON(HCC=1) setting.Moreover, non-display period can be output from the terminal VOB2 at the same time. Thearbitrary color part outputs the display of the subordinate position layer.

Note:

The signal of a translucent period from the terminal VOB2 is for the areas other than the character,the framing, and graphic of the main screen.

0 0 0 0 0 0 TCC HCC TC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TCC:

HCC:

Transparent color control(0: OFF, 1: ON)

Translucent color control(0: OFF, 1: ON)

TC3 - TC0:

HC3 - HC0:

Transparent color code(16 colors)

Translucent color code(16 colors)

620

CHAPTER 18 OSDC

18.5.9 Display Period Control (Command 14-0, 14-1, 14-2, 14-3)

Command 14-0, command 14-1, command 14-2, and command 14-3 are the commands that control the display period.


Address: 132H

Format

[Function]

This command controls the display beginning timing in the vertical direction.

Command14-1 (Display Period Control 2)

Address: 134H

Format

[Function]

This command controls the display end timing in the vertical direction.


Address: 136H

0 0 0 0 0 DYS10 DYS9 DYS8 DYS7 DYS6 DYS5 DYS4 DYS3 DYS2 DYS1 DYS0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DYS10 - DYS0: Vertical direction display beginning control(0 to 2047, 1-dot unit)

0 0 0 0 0 DYE10 DYE9 DYE8 DYE7 DYE6 DYE5 DYE4 DYE3 DYE2 DYE1 DYE0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DYE10 - DYE0: Vertical direction display end control(0 to 2047, 1-dot unit)

621

CHAPTER 18 OSDC

Format

[Function]

This command controls horizontal display beginning timing.


Address: 138H

Format

[Function]

This command controls horizontal display end timing.

0 0 0 0 0 DXS10 DXS9 DXS8 DXS7 DXS6 DXS5 DXS4 DXS3 DXS2 DXS1 DXS0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DXS10 - DXS0: Horizontal direction display beginning control(0 to 2047, 1-dot unit)

0 0 0 0 0 DXE10 DXE9 DXE8 DXE7 DXE6 DXE5 DXE4 DXE3 DXE2 DXE1 DXE0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DXE10 - DXE0: Horizontal direction display end control(0 to 2047, 1-dot unit)

622

CHAPTER 18 OSDC


Command 15-0 is a command that controls the interruption.

Command 15-0 (Interruption Control)

Address: 13AH

Format

[Function]

This command controls the interruption.

Please write "0" to clear the flag set once in FIF, LIF, and VIF.

0 0 0 0 0 FIF LIF VIF 0 0 0 0 0 FIE LIE VIE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIF:

LIF:

VIF:

FIE:

LIE:

VIE:

VRAM filter end flag(0: No VRAM filter end, 1: VRAM filter end)

Line display end flag(0: No line display end, 1: Line display end)

VSYNC detection flag(0: No VSYNC detection, 1: VSYNC detection)

VRAM filter end interruption control(0: The interruption is prohibited. 1: The interruption is enabled.)

Line display end interruption control(0: The interruption is prohibited. 1: The interruption is enabled.)

VSYNC detection interruption control(0: The interruption is prohibited. 1: The interruption is enabled.)

623

CHAPTER 18 OSDC

18.5.11 Palette Control (Command 16-0 to Command 16-15)

Command 16-0 to command 16-15 are command that controls the palette value.

Command 16-0 to Command 16-15 (Palette Control)

Address: See below table.

Format

PLR2-0: Red signal palette value

PLG2-0: Green signal palette value

PLB2-0: Blue signal palette value

[Format]

This command controls the palette value.

[Supplement]

• On OSDC 4-bit color code "0" to "F", the color of RGB is set to "command 16-0" to "command16-15" by setting the palette value.

• There is the following kinds of color codes;Character (MC3-MC0)Character background color (MB3-MB0)Framing color (LF3-LF0)Line background color (L3-L0)

Address(lower 9bit)

Command No.

Data

15-11 10 9 8 7 6 5 4 3 2 1 0

















624

CHAPTER 18 OSDC

18.6 FONT RAM Interface

This chapter explains the FONT RAM interface.

Overview

This macro is FONT selector for the MB91319 series.

A part of access for the FONT from the OSDC is outputted from the RAM.

When writing to the font RAM, disable the OSDC to prevent the conflict of access.

Note:

Be sure to write every 32-bit in the order of the address in 64-bit unit writing to the RAM.

Connection Diagram

Figure 18.6-1 Connection Diagram

CPU OSDC

RAM Selector

FL ASH

(ROM)

RAM

625

CHAPTER 18 OSDC

FONT RAM Memory Map

The FONT area has up to 4096 characters, and that of 16 characters between 4080th and 4096thbecomes the RAM area. The address area of 0x0002F800 through 0x0002FFFF is the RAMarea.

The area is connected in 32-bit unit from the CPU and accesses in the 64-bit unit.

Figure 18.6-2 FONT RAM Memory Map

[bit48 to bit63]

These bits do not use from the OSDC. When accessing from the CPU, the bits can use as thenormal RAM bit . The initial value is indeterminate.

Note :

These bits contain in the MB91FV319 only. The bits do not exist in the MB91F318.

[bit0 to bit47]

These bits assign the FONT RAM memory. The initial value is indeterminate.

63 00002_F800h

32 line

X16 Char

X

256WORD

1 WORD

:::

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX




0002_FFFFh

626

CHAPTER 18 OSDC

Example of font map

Figure 18.6-3 Example of Font Map

* The size of each font consists of 24-bit width × 32-bit height.

BBBB AAAA

D C

: :

: :

P O

0002_F8000002_F8000002_F8000002_F800 0002_F8080002_F8080002_F8080002_F808 0002_F8100002_F8100002_F8100002_F810 : : : : : : : : 0002_F80002_F80002_F80002_F8FFFF0000 0002_F80002_F80002_F80002_F8FFFF8888

0002_F0002_F0002_F0002_F909090900000 0002_F0002_F0002_F0002_F909090908888 0002_F0002_F0002_F0002_F919191910000 : : : : : : : : 0002_F0002_F0002_F0002_F9999F0F0F0F0 0002_F0002_F0002_F0002_F9999FFFF8888

0002_F0002_F0002_F0002_FAAAA00000000 0002_F0002_F0002_F0002_FAAAA08080808 0002_F0002_F0002_F0002_FAAAA10101010 : : : : 0002_F0002_F0002_F0002_FEEEEFFFF0000 0002_F0002_F0002_F0002_FEFEFEFEF8888

0002_F0002_F0002_F0002_FFFFF00000000 0002_F0002_F0002_F0002_FFFFF00008888 0002_F0002_F0002_F0002_FFFFF11110000 : : : : : : : : 0002_F0002_F0002_F0002_FFF0FF0FF0FF0 0002_F0002_F0002_F0002_FFFFFFFFF8888

63 4863 4863 4863 48 47 2447 2447 2447 24 23 023 023 023 0

2 charactersof font

* A,B ... represent the font.

Unu

sed

area

627

CHAPTER 18 OSDC

628

CHAPTER 19FLASH MEMORY

This chapter provides an outline of flash memory and explains its register configuration, register functions, and operations.

19.1 Outline of Flash Memory

19.2 Flash Memory Registers

19.3 Flash Memory Access Modes

19.4 Automatic Algorithm of Flash Memory

19.5 Execution Status of the Automatic Algorithm

19.6 Writing to and Erasing from Flash Memory

629

CHAPTER 19 FLASH MEMORY

19.1 Outline of Flash Memory

This product contains a 1M byte (8M bits) flash memory where the simultaneous erasure of all sectors, erasure in sector units, and writing in half-word (16 bits) units via the FR-CPU are possible.

Outline of Flash Memory

The flash memory employed is an internal 1M byte flash memory that operates on 3 V.

The flash memory employed here is the same as the Fujitsu 8M bit flash memory MB29LV800(except for part of the sector configuration) and supports writing using a device-external ROMwriter.

When this memory is used as FR-CPU internal ROM, it becomes possible to read instructionsand data in word units (32 bits), in addition to features equivalent to the features of theMB29LV800. This enables high-speed device operation.

Along with this manual, refer to the MB29LV800 Data Sheet.

This product supports the following features by combining flash memory macros and FR-CPUinterface circuits:

• Features for use as CPU memory, for storing programs and data

Accessibility through 32-bit bus when used as ROM

Allowing read, write, and erase (automatic program algorithm*) by the CPU

• Features of a single flash memory product equivalent to MB29LV800

Allowing read or write (automatic program algorithm*) by a ROM writer

*: Automatic program algorithm: embedded algorithmTM

Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc.

This section explains use of the flash memory accessed from the FR-CPU.

For information on using the flash memory accessed from a ROM writer, see the instructionmanual provided with the ROM writer.

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Block Diagram

Figure 19.1-1 shows a block diagram of flash memory.

Figure 19.1-1 Block Diagram of Flash Memory

Detection of rising edge

Bus

con

trol

sig

nal

FR-F bus (instruction/data)

Address buffer Data buffer

Flash memory

Generation of control signal

RDY WE

FD31-0FA18-0

RESETX

RDY/BUSYX

BYTEXOEX

WEX

FA18-0 DI15-0 DO31-0

8M bits

CEX

631


Memory Map

Flash memory employs different address mapping depending on whether accessed in flashmemory mode or CPU mode.

Figure 19.1-2 shows the mapping for access in flash memory mode and CPU mode.

Figure 19.1-2 Memory Mapping for Access in Flash Memory Mode/CPU Mode

Note that 64-bit access is used for 64-bit flash memory in CPU mode;16-bit width is used in flashmemory mode.

FLASH/Mask-ROM

I/O, etc

0000_0000H

FFFF_FFFFH

0017_FFFFH

0008_0000H

0010_0000H

001F_FFFFH

CPU mode

64-bit

1M ByteFLASH

FLASH mode(MB91FV319A, MB91F318A)

FLASH mode(MB91F318S, MB91FV319R)

16-bit

1M Byte

006F_0000H

007F_FFFFH

FLASH

16-bit

1M Byte

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Sector Address Table

Figure 19.1-3 shows the sector configuration in CPU mode.

Figure 19.1-3 Sector Configuration in CPU Mode (MB91FV319A, MB91F318A)

63 56,55 48 47 40,39 32 31 24,23 16 15 8,7 0

15 8,7 0

+1/+0

+0/+1

15 8,7 0

+1/+0

+2/+3

15 8,7 0

+1/+0

+4/+5

15 8,7 0

+1/+0

+6/+7

000C_0000H

000D_FFFFH

000E_0000H

000E_7FFFH

000E_FFFFH

000F_0000H

000E_8000H

000F_FFFFH

CPUBit OrderFlashBit Order

FLASH(little endian)

CPU(big endian)

EFFFFH AFFFFH 6FFFFH 2FFFFH

E0000H A0000H 60000H 20000H

000B_FFFFH

0008_0000H

SA23(64K)

SA16(64K)

SA9(64K)

SA2(64K)

F7FFFH B7FFFH 77FFFH 37FFFH

F0000H B0000H 70000H 30000H

SA24(32K)

SA17(32K)

SA10(32K)

SA3(32K)

F9FFFH B9FFFH 79FFFH 39FFFH

FBFFFH BBFFFH 7BFFFH 3BFFFH

FFFFFH BFFFFH 7FFFFH 3FFFFH

F8000H B8000H 78000H 38000H

FA000H BA000H 7A000H 3A000H

FC000H BC000H 7C000H 3C000H

SA25(8K)

SA18(8K)

SA11(8K)

SA4(8K)

SA26(8K)

SA19(8K)

SA12(8K)

SA5(8K)

SA27(16K)

SA20(16K)

SA13(16K)

SA6(16K)

CFFFFH 8FFFFH 4FFFFH 0FFFFH

C0000H 80000H 40000H 00000H

0013_FFFFH

0010_0000H

SA21(64K)

SA14(64K)

SA7(64K)

SA0(64K)

DFFFFH 9FFFFH 5FFFFH 1FFFFH

D0000H 90000H 50000H 10000H

0017_FFFFH

0014_0000H

SA22(64K)

SA15(64K)

SA8(64K)

SA1(64K)

Note: Addresses in each sector indicate start address (lower right) and end address (upper left) in FLASH mode. The next page shows the address orders in FLASH mode.

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Figure 19.1-4 Sector Configuration in CPU Mode (MB91F318S, MB91FV319R)

0x0018_0000

SA23 SA22

64KB 64KB

0x0016_0000

SA21 SA20

64KB 64KB

0x0014_0000

SA19 SA18

64KB 64KB

0x0012_0000

SA17 SA16

64KB 64KB

0x0010_0000

0x000F_C000 SA7 8KB SA6 8KB

0x000F_8000 SA5 8KB SA4 8KB

0x000F_4000 SA3 8KB SA2 8KB

0x000F_0000 SA1 8KB SA0 8KB

SA15 SA14

32KB 32KB

0x000E_0000

SA13 SA12

64KB 64KB

0x000C_0000

SA11 SA10

64KB 64KB

0x000A_0000

SA9 SA8

64KB 64KB

0x0008_0000

+0 +1 +2 +3 +4 +5 +6 +7

64-bit

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Figure 19.1-5 Sector Configuration in FLASH Mode (MB91FV319A, MB91F318A)

15 8,7

+1/+0

0

8FFFFH

80000H

SA14(64K)

9FFFFH

90000H

SA15(64K)

AFFFFH

A0000H

SA16(64K)

B7FFFH

B0000H

SA17(32K)

B9FFFH

B8000H

SA18(8K)

BBFFFH

BA000H

SA19(8K)

BFFFFH

BC000H

SA20(16K)

CFFFFH

C0000H

SA21(64K)

DFFFFH

D0000H

SA22(64K)

EFFFFH

E0000H

SA23(64K)

F7FFFH

F0000H

SA24(32K)

F9FFFH

F8000H

SA25(8K)

FBFFFH

FA000H

SA26(8K)

FFFFFH

FC000H

SA27(16K)

15 8,7

+1/+0

0

0FFFFH

00000H

SA0(64K)

1FFFFH

10000H

SA1(64K)

2FFFFH

20000H

SA2(64K)

37FFFH

30000H

SA3(32K)

39FFFH

38000H

SA4(8K)

3BFFFH

3A000H

SA5(8K)

3FFFFH

3C000H

SA6(16K)

4FFFFH

40000H

SA7(64K)

5FFFFH

50000H

SA8(64K)

6FFFFH

60000H

SA9(64K)

77FFFH

70000H

SA10(32K)

79FFFH

78000H

SA11(8K)

7BFFFH

7A000H

SA12(8K)

7FFFFH

7C000H

SA13(16K):

:

:

:

:

:

:

:

:

:

:

:

:

: :

:

:

:

:

:

:

:

:

:

:

:

:

:

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Figure 19.1-6 Sector Configuration in FLASH Mode (MB91F318S, MB91FV319R)

0x0080_0000

0x007F_0000 SA23 64KB

0x007E_0000 SA22 64KB

0x007D_0000 SA21 64KB

0x007C_0000 SA20 64KB

0x007B_0000 SA19 64KB

0x007A_0000 SA18 64KB

0x0079_0000 SA17 64KB

0x0078_0000 SA16 64KB

0x0077_0000 SA15 64KB

0x0076_0000 SA14 64KB

0x0075_0000 SA13 64KB

0x0074_0000 SA12 64KB

0x0073_0000 SA11 64KB

0x0072_0000 SA10 64KB

0x0071_0000 SA9 64KB

0x0070_0000 SA8 64KB

0x006F_E000 SA7 8KB

0x006F_C000 SA6 8KB

0x006F_A000 SA5 8KB

0x006F_8000 SA4 8KB

0x006F_6000 SA3 8KB

0x006F_4000 SA2 8KB

0x006F_2000 SA1 8KB

0x006F_0000 SA0 8KB

16-bit

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19.2 Flash Memory Registers

The flash memory has types of two registers: flash control/status register (FLCR) and flash memory wait register (FLWC).

List of Flash Memory Registers

Figure 19.2-1 shows a list of flash memory registers.

Figure 19.2-1 Flash Memory Registers

7bit 0

Flash control/status register(FLCR)

Flash memory wait register(FLWC)

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19.2.1 Flash Control/Status Register (FLCR)

The flash control/status register (FLCR) indicates the operation status of flash memory.

Configuration of Flash Control/Status Register (FLCR) (CPU Mode)

This register controls writing to flash memory.

This register can only be accessed in CPU mode. Do not access this register using the ReadModify Write instruction.

Figure 19.2-2 shows the bit configuration of FLCR.

Figure 19.2-2 Bit Configuration of FLCR

[bit7] Reserved

This is a reserved bit. Always set this bit to "0."

[bit6, bit5] Reserved

These are reserved bits. Always set these bits to "1."

[bit4] Reserved

This is a reserved bit. It is initialized to "0" during a reset.

[bit3] RDY

This bit indicates the operation status of the automatic algorithm (write/erase).

When this bit is set to "0," writing or erasure is in progress with the automatic algorithm and noWrite and Erase command can be accepted. Moreover, data cannot be read from any addressin flash memory.

The read data indicates the flash memory status as listed in the table below.

• This bit is not initialized during a reset.

• Only read operation is possible, but write operation does not affect this bit.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Reserved Reserved Reserved Reserved RDY Reserved WE Reserved

R/W R/W R/W R R R/W R/W R/W

00007000H

(0) (1) (1) (0) (0) (0) (0) (0)

0Writing or erasing is in process, flash memory is not ready to accept a new Write/Erase command, and no data can be read from a flash memory address.

1Flash memory is ready to accept a new Write/Erase command and data can be read from a flash memory address.

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[bit2] Reserved


[bit1] WE (Write Enable)

This bit controls the writing of data and commands to flash memory in CPU mode.

When this bit is set to "0," writing data and commands to flash memory is disabled.

Moreover, data is read from flash memory in 32-bit access mode.

When this bit is set to "1," data and commands can be written to flash memory and theautomatic algorithm can be started. However, data is read from flash memory in 16-bit accessmode.

If this bit is overwritten, confirm that the RDY bit has stopped the automatic algorithm (write/erase). When the RDY bit is set to "0," the value of this bit cannot be changed.

Notes:

• If this is overwritten, confirm that the RDY bit has stopped the automatic algorithm. When the RDYbit is set to "0", the value of this bit cannot be charged.

• When WE=1, do not respond to the instruction access request and only respond to the dataaccess request.

Writing is enabled regardless of this bit in flash memory mode.

• This bit is initialized to "0" during reset.

• Read and write operations are enabled.

[bit0] Reserved


0Writing to flash memory is disabled and data is read from flash memory in 32-bit access mode.

1Writing to flash memory is enabled and data is read from flash memory in 16-bit access mode.

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19.2.2 Flash Memory Wait Register (FLWC)

The flash memory wait register (FLWC) controls the wait status of flash memory in CPU mode.

Configuration

Figure 19.2-3 shows the bit configuration of flash memory wait register (FLWC).

Figure 19.2-3 Bit Configuration of Flash Memory Wait Register (FLWC)

[bit7, bit6] Reserved

These are reserved bits. Always set these bits to "0."

[bit5, bit4] FAC1 and FAC0

These bits specify the H width of ATDIN and EQIN.

[bit3] Reserved


[bit2 to bit0] WTC2, WTC1, and WTC0 (wait cycle bits)

These bits control the wait status of flash memory.

bit7

FAC1 FAC0 WTC2 WTC1 WTC0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

R R/W R/W R/W R/W R/W R/W R/W

00007004H

(0) (1) (1) (1) (0) (0) (1) (0)

FAC1 FAC0 ATDIN EQIN

0 0 0.5 clock 1.0 clock



1 1 0.5 clock 1.5 clock 40 MHz (Initial value)

WTC2 WTC1 WTC0 Wait cycle

0 0 0 Setting is disabled.

0 0 1 1

0 1 0 2 40 MHz (Initial value)

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

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• Flash access timing

Access times and the number of access cycles of flash macros are combined as listed in thetable below.

Read Write

40MHz 40MHz

Time 50 ns 90 ns

cycle 3(2) 4(3)

Values enclosed in parentheses are WTC register values.

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19.3 Flash Memory Access Modes

The following two types of access mode are available for the FR-CPU:• 120M mode:

One word (32 bits) can be read but not written in a single cycle.• Programming mode:

Access to data with a length defined in words (32 bits) is prohibited but writing data with a length defined in half-words (16 bits) is enabled.

FR-CPU ROM Mode (32 Bits, Read Only)

In this mode, the flash memory serves as FR-CPU internal ROM. This mode enables to read oneword (32 bits) in one cycle but does not enable to write to flash memory or to start the automaticalgorithm.

Mode specification

When specifying this mode, set the "WE" bit of the flash memory status register to "0".

This mode is always set after a reset occurs at CPU run time.

This mode can be set only when the CPU is running.

Detailed operation

In this mode, one word (32 bits) can be read from the flash memory area in one cycle.

Restrictions

• Address assignment and endians in this mode differ from those for writing with the ROMwriter.

• In this mode, commands and data cannot be written to flash memory together.

FR-CPU Programming Mode (16 Bits, Read/Write)

This mode enables data to be written and erased. As one word (32 bits) cannot be accessed inone cycle, program execution in flash memory is disabled in this mode.

Mode specification

When specifying this mode, set the "WE" bit of the flash memory status register to "1".

When a reset occurs at CPU run time, the "WE" bit indicates "0". When setting this mode, set the"WE" bit to "1". If the "WE" bit is set again to "0" through a writing operation or because of a reset,the device enters ROM mode.

When the "RDY" bit of the flash memory status register is "0", the "WE" bit cannot be overwritten.When overwriting the "WE" bit, ensure that the "RDY" bit is set to "1".

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Detailed operation

One half-word (16 bits) can be read from the flash memory area in one cycle.

The automatic algorithm can be started by writing a command to flash memory.

When the automatic algorithm starts, data can be written to or erased from flash memory. Fordetails on the automatic algorithm, see "19.4 Automatic Algorithm of Flash Memory".

For details on the automatic algorithm, see "19.4 Automatic Algorithm of Flash Memory".

Restrictions

• Address assignment and endians in this mode differ from those for writing with the ROMwriter.

• This mode inhibits reading data in words (32 bits).

Automatic Algorithm Execution Status

When the automatic algorithm is started in CPU programming mode, the operation status of theautomatic algorithm can be checked using the internal Ready/Busy signal (RDY/BUSYX). Thelevel of this signal can be read as the RDY bit in the flash memory status register.

When the RDY bit is set to "0," data is being written or erased with the automatic algorithm, andno write or erase command can be accepted. Moreover, data cannot be read from any address inflash memory.

Data read with the RDY bit set to "0" is a hardware sequence flag to indicate flash memorystatus.

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19.4 Automatic Algorithm of Flash Memory

The flash memory automatic algorithm can be started using a Read/Reset, Write, Chip Erase, or Sector Erase command. The Sector Erase command can stop and restart the automatic algorithm.

Command Sequence

At the start of the automatic algorithm, one to six half-words (16 bits) are written. This data iscalled the command.

If the address and data to be written are invalid or are written in an incorrect sequence, the flashmemory is reset to read mode.

Table 19.4-1 lists commands that can be used to write data to or erase data from flash memory.

RA: Flash memory read address

PA: Flash memory write address

SA: Address of sector to be erased in flash memory (Specify an address in a sector.)

RD: Data read from flash memory

FMA: Address

DIN: Written data

Table 19.4-1 Command Sequence (MB91FV319A, MB91F318A)

Command sequence

Bus write cycle

First bus write cycle

Second bus write cycle

Third bus write cycle

Fourth bus write cycle

Fifth bus write cycle

Sixth bus write cycle

FMA DIN FMA DIN FMA DIN FMA DIN FMA DIN FMA DIN

Read/Reset 1 AXXXXH F0F0H --- --- ---- --- --- --- --- --- --- ---

Read/Reset 4 AAAAAH AAAAH A5555H 5555H AAAAAH F0F0H RA RD --- --- --- ---

Write 4 AAAAAH AAAAH A5555H 5555H AAAAAH A0A0H PA PD --- --- --- ---

Chip Erase 6 AAAAAH AAAAH A5555H 5555H AAAAAH 8080H AAAAAH AAAAH A5555H 5555H AAAAAH 1010H

Sector Erase 6 AAAAAH AAAAH A5555H 5555H AAAAAH 8080H AAAAAH AAAAH A5555H 5555H SA 3030H

Table 19.4-2 Command Sequence (MB91F318S, MB91FV319R)

Command sequence

Bus write cycle

First bus write cycle

Second bus write cycle

Third bus write cycle

Fourth bus write cycle

Fifth bus write cycle

Sixth bus write cycle

FMA DIN FMA DIN FMA DIN FMA DIN FMA DIN FMA DIN

Read/Reset 1 AXXXXH F0F0H --- --- ---- --- --- --- --- --- --- ---

Read/Reset 4 A5557H AAAAH AAAABH 5555H A5557H F0F0H RA RD --- --- --- ---

Write 4 A5557H AAAAH AAAABH 5555H A5557H A0A0H PA PD --- --- --- ---

Chip Erase 6 A5557H AAAAH AAAABH 5555H A5557H 8080H A5557H AAAAH AAAABH 5555H A5557H 1010H

Sector Erase 6 A5557H AAAAH AAAABH 5555H A5557H 8080H A5557H AAAAH AAAABH 5555H SA 3030H

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Read/Reset command

Set flash memory into Read/Reset mode.

The flash memory remains in reading state until another command is entered.

When the power is turned on, flash memory is automatically set to the read or reset state. In thiscase, data can be read without a command of the automatic algorithm.

Upon returning to read mode after the time limit is exceeded, note that a Read/Reset commandsequence can be issued. Data is read from flash memory in the next read cycle.

Program (Write)

In CPU programming mode, data is basically written in half-word units. The write operation isperformed in four cycles of bus operation. The command sequence has two "unlock" cycles,which are followed by a Write Setup command and a write data cycle. Writing to memory starts inthe last write cycle.

After an automatic write algorithm command sequence was executed, it becomes unnecessary tocontrol the flash memory externally. The flash memory itself internally generates write pulses tocheck the margin of the cells to which data is written. The data polling function compares bit7 ofthe original data with bit7 of the written data, and if these bits are the same, the automatic writeoperation ends (see "Hardware Sequence Flag," in "19.5 Execution Status of the AutomaticAlgorithm"). The automatic write operation then returns to the read mode and accepts no morewrite addresses. After that, the flash memory requests the next valid address. In this manner, thedata polling function indicates a write operation in memory.

During a write operation, all commands written to the flash memory are ignored. If a hardwarereset starts during write operation, the data at the address for writing may become invalid.

Writing operations can be performed in any address sequence and outside of sector boundaries.However, write operations cannot change a data item "0" to "1". If a "0" is overwritten with a "1",the data polling algorithm either determines that the elements are defective, or that "1" has beenwritten. In the latter case, however, the respective data item is read as "0" in reset or read mode.A data item "0" can be changed to "1" only after an erase operation.

Chip Erase

The Chip Erase command sequence ("erase all sectors simultaneously") is executed in sixaccess cycles. First, two "unlock" cycles are executed, then a "Setup" command is written. Aftertwo more "unlock" cycles, the Chip Erase command is entered.

During the Chip Erase command sequence, the user does not have to write to flash memorybefore the erase operation. When the automatic erase algorithm is executed, flash memorychecks cell states by writing a pattern of zeros before automatically erasing the contents of allcells (preprogram). In this operation, flash memory does not have to be controlled externally.

The automatic erase operation starts with the write operation of the command sequence andends when bit7 is set to "1", where flash memory returns to the read mode. The chip erase timecan be expressed as follows: time for sector erase × number of all sectors + time for writing to thechip (preprogram).

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Sector Erase

The Sector Erase command sequence is executed in six access cycles. First, two "unlock" cyclesare executed, then a "Setup" command is written. After two more "unlock" cycles, the SectorErase command is entered in the sixth cycle for starting the sector erase operation. The nextSector Erase command can be accepted within a time-out period of 50 µs after the last SectorErase command is written.

As already mentioned, multiple Sector Erase commands can be accepted during the six buscycles of the writing operation. During the command sequence, Sector Erase commands (30H) forsectors whose contents are to be erased simultaneously are written consecutively to theaddresses for these sectors. The sector erase operation itself starts from the end of the time-outperiod of 50 µs after the last Sector Erase command is written. When the contents of multiplesectors are erased simultaneously, the subsequent Sector Erase commands must be input withinthe 50 µs time-out period to ensure that they are accepted. For checking whether the succeedingSector Erase command is valid, read bit3 (see "Hardware Sequence Flag," in "19.5 ExecutionStatus of the Automatic Algorithm").

During the time-out period, any command other than Sector Erase and Temporarily Stop Erase isreset at read time, and the preceding command sequence is ignored. In the case of theTemporary Stop Erase command, the contends of the sector are erased again and the eraseoperation is completed.

Any combination and number (from 0 to 6) of sector addresses can be entered in the sector erasebuffers.

The user does not have to write to flash memory before the sector erase operation.

Flash memory automatically writes to all cells in a sector whose data is automatically erased(preprogram). When the contents of a sector are erased, the other cells remain intact. In theseoperations, flash memory does not have to be controlled externally.

The automatic sector erase operation starts from the end of the 50 µs time-out period after thelast Sector Erase command is written. When bit7 is set to "1", the automatic sector eraseoperation ends and flash memory returns to the read mode. At this time, other commands areignored.

The data polling function is enabled for any sector address in which data has been erased. Thetime required for erasing the data of multiple sectors can be expressed as follows: time for sectorerase + time for sector write (preprogram) × number of erased sectors.

Temporarily Stop Erase

The Temporarily Stop Erase command temporarily stops the automatic algorithm in flash memorywhen the user is erasing the data of a sector, thereby making it possible to write data to and readdata from the other sectors. This command is valid only during the sector erase operation andignored during chip erase and write operations.

The Temporarily Stop Erase command (B0H) is effective only during sector erasure operation thatincludes the sector erase time-out period after a Sector Erase command (30 H) is issued.

When this command is entered within the time-out period, waiting for time-out ends and the eraseoperation is suspended. The erase operation is restarted when a Restart Erase command waswritten. Temporarily Stop Erase and Restart Erase commands can be entered with any address.

When a Temporarily Stop Erase command is entered during sector erase operation, the flashmemory needs a maximum of 20 µs to stop the erase operation. When flash memory enterstemporary erase stop mode, a Ready or Busy signal is output, bit7 outputs "1", and bit6 stops totoggle. For checking whether the erase operation has stopped, enter the address of the sectorwhose data is being erased and read the values of bit6 and bit7. At this time, another TemporarilyStop Erase command entry is ignored.

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When the erase operation stops, flash memory enters the temporary erase stop and read mode.Data reading is enabled in this mode for sectors that are not subject to temporary erase. Otherthan that, there is no difference from the standard read operation. In this mode, bit2 toggles forconsecutive reading operations from sectors subject to temporary erase stop.

After the temporary erase stop and read mode is entered, the user can write to flash memory bywriting a Write command sequence. The write mode in this case is the temporary erase stop andwrite mode. In this mode, data write operations become valid for sectors that are not subject totemporary erase stop. Other than that, there is no difference from the standard byte writingoperation. In this mode, bit2 toggles for consecutive reading operations from sectors that aresubject to temporary erase stop. The temporary erase stop bit (bit6) can be used to detect thisoperation.

Note that bit6 can be read from any address, but bit7 must be read from write addresses.

To restart the sector erase operation, a Restart Erase command (30H) must be entered. AnotherRestart Erase command entry is ignored in this case. On the other hand, a Temporarily StopErase command can be entered after flash memory restarts the erase operation.

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19.5 Execution Status of the Automatic Algorithm

Flash memory is provided with hardware to indicate the internal operation status of flash memory and the completion of write/erase operations in the automatic algorithm. The following two hardware sequence flags for the automatic algorithm can be used to check the operation status of flash memory:• Ready/Busy signal• Hard ware sequence flag

Ready/Busy Signal (RDY/BUSYX)

The flash memory uses the Ready/Busy signal in addition to the hardware sequence flag toindicate whether the internal automatic algorithm is running. The Ready/Busy signal is transmittedto the flash memory interface circuit, where it can be read via the "RDY" bit of the flash memorystatus register. An interrupt signal can also be generated for the CPU at the rising edge of thisReady/Busy signal.

When the value of the "RDY" bit is "0", the flash memory is executing a write or erase operation,where new Write and Erase commands are not accepted.

When the value of the "RDY" bit is "1", the flash memory is in read/write or erase operation waitstate.

Hardware Sequence Flag

For obtaining the hardware sequence flag as data, read an arbitrary address (an odd address inbyte access) from flash memory when the automatic algorithm is executed. The data contains fivevalidity bits which indicate the status of the automatic algorithm.

When the automatic algorithm is executed for ROM1, specify an address in ROM1. Whenexecuted for ROM2, specify an address in ROM2.

Figure 19.5-1 shows the structure of the hardware sequence flag.

Figure 19.5-1 Structure of the Hardware Sequence Flag

The hardware sequence flag becomes invalid in FR-CPU ROM mode. Always use FR-CPUprogramming mode and write only in half-words or bytes.

02 1

0

0

7DPOLL TOGGLE TLOVER

6 5 4 3SETIMER TOGGl2(Undefined)

(Undefined)

15 7

7

bit

bit

bit

8

(In half-word and byte access)

During half-word read

During byte read (from odd address only)

Hardware sequence flag

Hardware sequence flag

(Undefined) (Undefined)

* Reading in units of words is disabled. (Only use this function in FR-CPU programming mode.)

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Table 19.5-1 lists the possible statuses of the hardware sequence flag.

The hardware sequence flags are explained below.

[bit7] DPOLL (Data polling flag)

This flag is used with the data polling function to report that the automatic algorithm is beingexecuted or terminated.

Automatic write operation status

When read access is performed while the automatic write algorithm is being executed, flashmemory outputs the inversion of bit7 of the last data written regardless of the address indicatedby the address signal. When read access is performed at the end of the automatic writealgorithm, flash memory outputs bit7 of the read data to the address indicated by the addresssignal.

Table 19.5-1 Statuses of the Hardware Sequence Flag

Status DPOLL TOGGLE TLOVER SETIMR TOGGL2

Executing

Automatic read operationReverse

dataToggle 0 0 1

Automatic erase operation 0 Toggle 0 1 Toggle

Temporary erase stop mode

Temporary erase stop and read (from sectors in temporary erase stop)

1 1 0 0 Toggle*1

Temporary erase stop and read (from sectors not in temporary erase stop)

Data Data Data Data Data

Temporary erase stop and write (to sectors not in temporary erase stop)

Reverse data

Toggle*2 0 0 1*3

Time limit exceeded

Automatic write operationReverse

dataToggle 1 0 1

Automatic erase operation 0 Toggle 1 1 *4

Write operation during temporary erase stop

0 Toggle 1 1 *4

*1: TOGGLE2 toggles continuous read operations from sectors in temporary erase stop status.*2: TOGGLE toggles continuous read operations from any address.*3: During temporary erase stop status and write operations, TOGGLE2 indicates "1" while reading the

address for write operation. However, TOGGLE2 toggles continuous read operations from sectors in temporary erase stop status.

*4: TOGGLE2 toggles continuous read operations for sectors under write/erase operation, but does not toggle read operations for other sectors while TLOVER indicates "1," meaning that the time limit is exceeded.

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Chip/sector erase operation status

When read access is performed while the chip erase/sector erase algorithm is being executed,flash memory outputs "0" from the target sector (sector erase), regardless of the addressindicated by the address signal. Similarly, flash memory outputs "1" at the end of the chip erase/sector erase algorithm.

Temporary sector erase stop status

When read access is performed during temporary sector erase stop status, flash memory outputs"1" when the address indicated by the address signal is included in the sector in erase status. Ifthe address is not included in the sector in erase status, flash memory outputs bit7 of the readvalue to the address. For checking whether a sector is in temporary sector erase stop status andwhich sector is in erase status, read this bit and the toggle bit flag.

Note:

Read access to a specified address is ignored while the automatic algorithm is active. Values can beoutput to other bits after data polling flag operation terminates in data read operation. Therefore,when data is to be read after terminating the automatic algorithm, confirm that data polling isterminated in the current read access.

[bit6] TOGGLE (Toggle bit flag)

This flag is used with the toggle bit function to mainly report that the automatic algorithm is beingexecuted or terminated.

Write or chip/sector erase operation status

When continuous read operations are performed while the automatic write algorithm or chip/sector erase algorithm is being executed, flash memory outputs "1" and "0" toggle results to bit6regardless of the address indicated by the address signal. When continuous read operations areperformed at the end of the automatic write algorithm or chip/sector erase algorithm, flashmemory stops bit6 from toggling and outputs bit6 (DATA: 6) of the data read from the addressindicated by the address signal.

If a write target sector is protected from overwriting during a write operation, the toggle bit tries totoggle for about 2 µs and stops toggling without changing data. If all selected sectors areprotected from overwriting, the toggle bit tries to toggle for about 100 µs and the system returns toread/reset status without changing data.

Temporary sector erase stop status

When a read operation is performed during a temporary sector erase stop operation, flashmemory outputs "1" if the address indicated by the address signal is included in the sector inerase state. If the address is not included in the sector in erase state, flash memory outputs thedata of bit6 of the read value at the address indicated by the address signal.

[bit5] TLOVER (Time limit over flag)

This flag is used to report that a time (number of internal pulses) specified internally with flashmemory is exceeded while the automatic algorithm is being executed.

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When read access is performed within a specified time (necessary for write or erase) afteractivating the automatic write or chip/sector erase algorithm, flash memory outputs "0." If readaccess is performed beyond the specified time, flash memory outputs "1." Because these outputoperations are not affected by whether the automatic algorithm is being executed or terminated,these operations can be used to check whether write or erase operation is successful. If flashmemory outputs "1" while the automatic algorithm is being executed with the data polling functionor toggle bit function, consider the write operation to be unsuccessful.

For example, when "1" is written to a flash memory address where "0" is written, failure occurs.Flash memory is locked and the automatic algorithm is not terminated. Thus, valid data is notoutput from the data polling flag. The toggle bit flag does not stop toggling, the time limit isexceeded, and "1" is output to the TLOVER flag. This status indicates that flash memory was notused correctly, not that it was defective. Execute a Reset command.

[bit4] SETIMR Sector erase timer flag

This flag is used to report that sector erasure is being awaited after starting a Sector Erasecommand.

Sector erase operation status

When read access is performed within a sector erase wait period after starting a Sector Erasecommand, flash memory outputs "0" regardless of the address indicated by the address signal ofthe target sector. If read access is performed beyond the wait period, flash memory outputs "1"regardless of the address.

When "1" is set in this flag while the data polling or toggle bit function indicates that the automaticalgorithm is being executed, an internally controlled erase operation has started. The writing ofsubsequent sector erase code and commands other than Erase Temporary Stop is ignored untilerase operation terminates.

When this flag is "0", flash memory accepts another sector erase code entry. In this case, it isrecommended to check the status of this flag by software before writing the succeeding sectorerase code. If this flag is "1" at the second time of status check, the additional sector erase codemay not be accepted.

Sector erase operation status

When a read operation is performed during a temporary sector erase stop operation, flashmemory outputs "1" if the address indicated by the address signal is included in the sector that issubject to the erase operation. If the address is not included in the sector that is subject to theerase operation, flash memory outputs the data of bit3 of the read value at the address indicatedby the address signal.

[bit6] TOGGL2 (Toggle bit flag 2)

Together with toggle bit6, this toggle bit is used with the toggle bit function to report whether flashmemory is under automatic erase operation or in temporary erase stop status.


This bit toggles the same way as bit2.

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Temporary sector erase stop operation status

When continuous read access is performed from a sector in temporary erase stop status whileflash memory is in temporary erase stop status and read mode, bit2 toggles. When continuousread access is performed from a sector not subject to a temporary erase stop operation whileflash memory is in temporary erase stop status and write mode, bit2 becomes "1." Unlike bit2,bit6 only toggles in normal write and erase operations, or in temporary erase stop status and writeoperation.

For example, bit2 and bit6 are used together to detect a temporary erase stop and read mode(bit2 toggles but bit6 does not). Bit2 is also used to detect sectors that are subject to eraseoperations. If data is read from a sector that is subject to an erase operation for the flash memory,bit2 toggles.

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19.6 Writing to and Erasing from Flash Memory

This section explains how to issue a command to start the automatic algorithm for a read/reset, write, chip erase, sector erase, temporary sector erase stop, or sector erase restart operation in flash memory.

Writing/Erase

The automatic algorithm can be executed for read/reset, write, chip erase, sector erase,temporary sector erase stop, or erase restart operations by executing bus write cycles for thecorresponding command sequence. The write cycles for each bus must always be executedcontinuously. Termination of the automatic algorithm can be checked with the data pollingfunction and toggle bit function. Flash memory is set again into read/reset status after theautomatic algorithm terminates normally.

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19.6.1 Read/Reset Status

This section explains how to issue Read/Reset commands to set flash memory into read/reset status.

Read/Reset Status

The read/reset operation becomes possible by continuously sending Read/Reset commands(listed in the command sequence table) to target sectors in flash memory.

A bus operation is performed one or three times with a Read/Reset command sequence. There isno essential difference between these two sequences. Read/reset status is the initial status offlash memory, and flash memory is set in this status at power-on or when a command terminatesnormally. In this status, the system waits for a command other than Read/Reset to be entered.

Data can be read using normal read access in this status. Programs can be accessed from theCPU the same way the programs in mask ROM are accessed. The Read/Reset command is notnecessary for reading data in normal read access. This command is required, however, toinitialize the automatic algorithm if a command does not terminate normally.

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19.6.2 Data Writing

This section explains how to issue a Write command to write data to flash memory.

Data Writing

The automatic data write algorithm can be started by continuously sending write commands(listed in the command sequence table) to target sectors in flash memory. The automaticalgorithm and automatic writing start when writing data to the target address terminates in thefourth cycle.

How to specify address

Only even-numbered addresses can be specified in write data cycles. If an odd-numberedaddress is specified, data cannot be written correctly. In other words, data must be written toeven-numbered addresses in units of half-words.

Data can be written by freely specifying the order of addresses where data is to be written.Moreover, data can be written beyond sector boundaries. Note that items of data can only bewritten with each write command in units of half-words.

Notes on writing data

Data "0" cannot be changed to "1" in a write operation. If data "1" is overwritten, the data pollingalgorithm or toggle operation does not terminate, and the flash memory device is considereddefective. An error is assumed with the time limit over flag if the specified write time is exceeded,or if only data "1" is apparently written, although data "0" is read in read/reset status. Data "0" canbe changed to "1" only with an erase operation. All commands are ignored during automaticwriting. If a hardware reset is activated during writing, the data being written is not guaranteed.

Write procedure

Figure 19.6-1 shows an example of the write procedure.

The status of the automatic algorithm in flash memory can be checked using the hardwaresequence flag. In the example in Figure 19.6-1, the data polling flag (DPOLL) is used to check fortermination of the write operation.

Data for the flag check is read from the address where the last data was written.

The data polling flag (DPOLL) changes together with the time limit over flag (TLOVER).Therefore, DPOLL must be rechecked even though TLOVER is set to "1."

The toggle bit flag (TOGGLE) also stops toggling simultaneously when the value of TLOVER ischanged to "1." Therefore, this flag must also be rechecked.

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Figure 19.6-1 Example of Write Procedure (Half-Word Access)

Write command sequence AAAAA AAAA A5555 5555 AAAAA A0A0 Write address write data

Enable writing to flash memory with WE (bit 5) in FLCR.

Writing start

Read internal address.

Data polling (DPOLL)

Data

Data

Data

Time limit (TLOVER)

Read internal address.

1

0

Data polling (DPOLL)

Data

Write error Last address

Next address

No

Disable writing to flash memory with WE (bit 5) in FLCR.

Writing completion

Check hardware sequence flag

Yes

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19.6.3 Data Erasure (Chip Erasure)

This section explains how to issue Chip Erase commands to erase all items of data in flash memory.

Data Erasure (Chip Erasure)

All items of data can be erased from flash memory by continuously sending Chip Erasecommands (listed in the command sequence table) to target sectors in flash memory.

Six bus operations are necessary to execute a chip erase operation. The operation starts whenthe sixth write cycle is completed. The user need not write any value to flash memory before chiperase operation. Flash memory automatically writes "0" to erase all cells.

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19.6.4 Data Erasure (Sector Erasure)

This section explains how to issue Sector Erase commands to erase specified sectors in flash memory. Erasure in sector units is possible and two or more sectors can be specified with this command.

Sector Erasure

Specified sectors can be erased from flash memory by continuously sending Sector Erasecommands (listed in the command sequence table) to the sectors.

How to specify sectors

A sector erase operation can be performed with six bus operations. A 50-µs sector erase waitperiod starts when a sector erase code (30H) is written to an even-numbered address accessiblein the target sector in the sixth cycle. To erase another sector, a sector code (30H) must bewritten in the same cycle the same way.

Note on specifying two or more sectors

A sector erase operation starts when the 50-µs sector erase wait period terminates after the finalsector erase code is written. Therefore, when two or more sectors are to be specified, theaddress and erase code of each target sector must be entered within 50-µs (in the sixth cycle ofthe command sequence) after specifying the preceding sector. Note that an address and erasecode not entered within 50-µs may not be accepted. The sector erase timer (hardware sequenceflag: SETIMR) can be used to check the validity of a written sector erase code. The address atwhich the read sector erase time is written should indicate the target sector.

Sector erase procedure

The hardware sequence flag can be used to check the status of the automatic algorithm in flashmemory.

Figure 19.6-2 shows an example of the sector erase procedure. In this example, the toggle bitflag (TOGGLE) is used to check for termination of the erase operation.

Note that data for the flag check is read from the sector to be erased.

The toggle bit flag (TOGGLE) stops toggling simultaneously when the value of the time limit overflag (TLOVER) changes to "1." Therefore, TOGGLE must be rechecked even though TLOVER isset to "1."

Because the data polling flag (DPOLL) also changes with TLOVER, it must also be rechecked.

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Figure 19.6-2 Sector Erase Procedure

Erase command sequence AAAAA A5555 AAAAA A5555 AAAAA

AAAA5555808055551010

Enable erasure in flash memory with WE (bit 5) in FLCR.

Enter code (30H) to sector to be erased.

Is there another sector to be erased?

Time limit (TLOVER)

Internal address read 2

1

0

Erasure error Is final sector erased?

Next sector

Yes

No

Disable erasure in flash memory with WE (bit 5) in FLCR.

Erase completion

Is value of sector erase timer 1 or 0?

Internal address read

1

0

Yes

No

Yes

No



Toggle bit (TOGGLE) data 1 = data 2?

Yes

No


Toggle bit (TOGGLE) data 1 = data 2?

Erase start

Check with hardware sequence flag

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19.6.5 Temporary Sector Erase Stop

This section explains how to issue Temporary Sector Erase Stop commands to temporarily stop a sector erase operation in flash memory. Data can be read from a sector not being erased by using this command.

Temporary Sector Erase Stop

A sector erase operation in flash memory can be stopped temporarily by continuously sendingTemporary Sector Erase Stop commands (listed in the command sequence table) to the targetsector in flash memory.

Data can be read from a sector being erased by using the Temporary Sector Erase Stopcommand to temporarily stop the erasure. Data can only be read from the sector; data cannot bewritten there. This command is only effective during sector erasure that includes an erase waitperiod. It is ignored during chip erase operation and write operation.

A sector erase operation is stopped temporarily by writing a temporary erase stop code (B0 H).The address where the temporary erase stop code is written should indicate an address in flashmemory. A Temporary Sector Erase Stop command issued during temporary erase stop status isignored.

If a Temporary Sector Erase Stop command is entered during a sector erase wait period, thesector erase wait is immediately canceled and erase operation in progress is stopped. If aTemporary Sector Erase Stop command is entered during a sector erase operation after thesector erase wait period elapses, sector erase operation is stopped temporarily after up to 15-µselapse.

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19.6.6 Sector Erase Restart

This section explains how to issue Sector Erase Restart commands to restart a temporarily stopped sector erase operation in flash memory.

Sector Erase Restart

A temporarily stopped sector erase operation can be restarted by sending Sector Erase Restartcommands (listed in the command sequence table) to the target sector in flash memory.

The Sector Erase Restart command can restart a sector erase operation that has temporarilybeen stopped with the Temporary Sector Erase Stop command. Restart operation starts when anerase restart code (30H) is written. The address where the erase restart code is written shouldindicate an address in flash memory.

Sector Erase Restart commands issued during a sector erase operation are ignored.

Restriction and Notes

(1) Do not execute the write access for the following area (I-bus)

0000_0300H to 0000_037FH0000_03E4H to 0000_03E7H0000_8000H to 0000_BFFFH0001_0000H to 0001_FFFFH

(2) Do not execute the write access to the FLASH memory at WE=0 of FMCS register.

(3) Do not execute the continuous write access for the FLASH memory at WE=1 of FMCS register. In this case, be sure to open more than "NOP"1 instruction.

Example: Command write to FLASH (command sequence) => FLASH readIdi #0xAAAA, r0Idi #0x5555, r1Idi #0xAAAAA, r6Idi #0xA5555, r7Idi #0xA0A0, r8Idi #PA, r2Idi #PD, r3

sth r0, @r6nop : Be sure to open more than "NOP"1 instructionsth r1, @r7nop : Be sure to open more than "NOP"1 instructionsth r8, @r6nop : Be sure to open more than "NOP"1 instructionsth r3, @r2nop : Be sure to open more than "NOP"1 instruction

(4) The write access is enabled only the halfword to FLASH memory at the CPU mode. Do notexecute the byte write access.

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(5) Do not execute the branch instruction to the FLASH memory area after rewriting the WE,FIXE, BIRE of the FMCS register. When branching to the FLASH area, obey the followingprogram example once the FMCS register value is read.

STB R1, @R2 / / WE=OFFLDUB @R2, R1 / / FMCS value dummy readBRA _flash_address / / Branch to the FLASH memory

(6) The sector protect cannot be used.

(7) Do not guarantee the read value immediately after rewriting to FLASH. Before reading isexecuted after writing, be sure to insert the dummy read.

STH r0, @r1 / / FLASH writeLDUB @r2, r4 / / Dummy readBRA @r3 r4 / / Polling data read

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CHAPTER 20SERIAL PROGRAMMING

CONNECTION

The built-in FLASH product supports the serial onboard writing (Fujitsu standard) of the flash ROM. The following explains its specification.

20.1 Serial Programming Connection

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CHAPTER 20 SERIAL PROGRAMMING CONNECTION

20.1 Serial Programming Connection

The built-in FLASH product supports the serial onboard writing (Fujitsu standard) of the flash ROM. The following explains its specification.

Basic Configuration of Serial Programming Connection

Fujitsu standard serial onboard writing uses the AF220/AF210/AF120/AF110 flash micro-controller programmer by Yokogawa Digital Computer Corporation.

The following figure shows the basic configuration of MB91FV319 serial programmingconnection.

Note:

For information on the functions of and operational procedures related to the flash micro-controllerprogrammer (AF220/AF210/AF120/AF110), the general-purpose common cable (AZ210) forconnection, and the connector, contact Yokogawa Digital Computer Corporation.

AF220/AF210/AF120/AF110Flash Micro-Controller

Programmer +

memory card

User systemRS232CCLK synchronous serial connection

Operable in stand-alone mode

Common general-purpose cable (AZ210)

Host interface cable

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Pins Used for Fujitsu Standard Serial Onboard Writing

Notes:

• To use the P24, P25, SIO, SO0, and SCK0 pins within the user system as well, the control circuitshown in the following figure is required.(Using the flash micro-controller programmer’s /TICS signal, the user circuit can be disconnectedin serial programming mode.)

• Connect with AF220/AF210/AF120/AF110 under the power-off state of the user system.

Pin Function Description

MD3, MD2, MD1, MD0

Mode pin

Set to enter the flash serial programming mode. Flash serial programming mode: MD3, MD2, MD1, MD0 = 0, 1, 0, 0Reference: Single-chip mode: MD3, MD2, MD1, MD0 = 0, 0, 0, 0

P24/A4, P25/A5

Programming program start pin

Set P24 = "L" and P25 = "H" (clock synchronous mode) at the flash serial writing.Reference:

When P24 = "L" and P25 = "L", used as asynchronous UART mode.

INITX,TRSTX Reset pin -

P84/SIO Serial data input pinUse channel 0 resource of UART as the interface for the serial onboard writing communication.

P85/SO0 Serial data output pin

P86/SCK0 Serial clock input pin

VDDE/VDDIPower voltage supply pin

The programming voltage is supplied from the user system.

VSS GND pin Must be shared with GND of the flash micro-controller programmer.

User

MB91FV319A/RMB91F318A/SWrite control pin

AF220/AF210/AF120/AF110

Write control pin

/TICS pin

AF220/AF210/AF120/AF110

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Example of Serial Programming Connection

Figure 20.1-1 shows an example of the serial programming connection.

Figure 20.1-1 Example of Serial Programming Connection

(19)

(10)

(13)

(27)

(6)

(5)

GND

TRXD

TCK

TAUX3

/TICS

/TRES

MD0 71

MD1 72

VDDE 4,56,92,124,158

SCK0 82

SO0 81

MD2 73

SI0 80

(14,15, 1,28)

MB91FV319A/R, MB91F318A/S

TVcc (2)

(18)WDT

INITX 75

TTXD

Vss 5,58,94,123,156

User system

Connector DX10-28S

- DX10-28S: write angle type

Pin assignments of connector (Hirose Electric)

Pin 28

DX10-28S

Pins 3, 4, 9, 11, 16, 17, 18, 20, 23, 24, 25, and 26 are opened.

Pin 14 Pin 1

Pin 15

MD3 74

At serial programming 1 10k

User circuit

User circuit

Power supplied from user (2.5V)

Power supplied from user (3.3V)

At serial programming 0

At serial programming 1

P24 49

P25 50

TRSTX 61

10k

10k

VDDI 33,96,154,170

AF200/AF210/AF120/AF110Flash micro-controllerprogrammer

-

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System Configuration of AF220/AF210/AF120/AF110 Flash Micro-controller Programmer (Yokogawa Digital Computer Corporation)

Oscillation Clock Frequency

For the write operations on flash memory, the oscillation clock that can be used is 10 MHz.

Other Precautionary Information

The port state for flash memory writing via a serial programmer is the same as the reset stateexcept the pin used at write operation.

Type Function

Main body

AF220/AC4P Model with built-in Ethernet interface /100 V to 220 V power adapter

AF210/AC4P Standard model /100 V to 220 V power adapter

AF120/AC4P Model with built-in single key Ethernet interface /100 V to 220 V power adapter

AF110/AC4P Single key model /100 V to 220 V power adapter

AZ221 Programmer dedicated RS232C cable for PC/AT

AZ210 Standard target probe (a) length: 1 m

FF201 Fujitsu FR flash micro-controller control module

AZ290 Remote controller

/P8 8 MB PC Card (Option) FLASH memory capacity of up to 1 MB supported

/E6 4 MB PC Card (Option) FLASH memory capacity of up to 2 MB supported

/E12 8 MB PC Card (Option) FLASH memory capacity of up to 6.75 MB supported

Inquiries: Yokogawa Digital Computer CorporationTelephone number: +81-42-333-6224

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668

APPENDIX

This appendix consists of the following parts: the I/O map, interrupt vector, dot clock generation PLL, USB clock, external bus interface setting, and instruction lists. The appendix contains detailed information that could not be included in the main text and reference material for programming.

APPENDIX A I/O Map

APPENDIX B Interrupt Vector

APPENDIX C Dot Clock Generation PLL

APPENDIX D USB Clock

APPENDIX E Macro Reset

APPENDIX F USB Low-power Consumption Mode

APPENDIX G External Bus Interface Setting

APPENDIX H Pin State List

APPENDIX I Instruction Lists

669

APPENDIX A I/O Map

APPENDIX A I/O Map

Table A-1 shows the correspondence between the memory space area and the peripheral resource registers.

I/O Map

[Reading the table]

Note:

The initial value of bits in a register are indicated as follows:

1: Initial value 1

0: Initial value 0

X: Initial value X

-: A physical register does not exist at the location.

block000000H PDR0[R/W] PDR1[R/W] PDR2[R/W] PDR3[R/W] T-unit

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Port Data Register

Read/write attribute

Initial value of register after reset

Register name (column 1 of the register is at address 4n, column 2 is at address 4n + 2...)Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.)

+2 +3+1+0register

address

670

APPENDIX A I/O Map

Table A-1 I/O Map (1 / 9)

AddressRegister

Block+0 +1 +2 +3

000000H|

00000FH

- - - - Reserved

000010HPDR0[R/W]XXXXXXXX

PDR1[R/W]XXXXXXXX

PDR2[R/W]XXXXXXXX

PDR3[R/W]XXXXXXXX

R-busPort Data Register


PDR5[R/W]XXXXXXXX

-PDR7[R/W]--XXXXXX


PDR9[R/W]XXXXXXXX

PDRA[R/W]-----XXX

PDRB[R/W]XXXXXXXX

00001CHPDRC[R/W]XXXXXXXX

- - -

000020HADCTH[R/W]

00000000ADCTL[R/W]

00000000ADCH[R/W]

00000000_00000000

10bit A/D converter

000024HADAT0[R]

XXXXXX00_00000000ADAT1[R]

XXXXXX00_00000000

000028HADAT2[R]


XXXXXX00_00000000

00002CHADAT4[R]


XXXXXX00_00000000

000030HADAT6[R]


XXXXXX00_00000000000034H - - - -

Reserved000038H - - - -00003CH - - - -

000040HEIRR [R/W]00000000

ENIR [R/W]00000000

ELVR [R/W]00000000

Ext int

000044HDICR [R/W]

-------0HRCL [R/W]

0--11111-------- DLYI/I-unit

000048HTMRLR0 [W]

XXXXXXXX XXXXXXXXTMR0 [R]

XXXXXXXX XXXXXXXXReload Timer 0

00004CH --------TMCSR0 [R/W]

----0000 00000000

000050HTMRLR1 [W]



000054H --------TMCSR1 [R/W]

----0000 00000000

000058HTMRLR2 [W]



00005CH --------TMCSR2 [R/W]

----0000 00000000

000060HSSR0 [R/W]

00001-00SIDR0[R]/SODR0[W]

XXXXXXXXSCR0 [R/W]00000100

SMR0 [R/W]00--0---

UART0

000064HUTIM0 [R] (UTIMR0 [W])

00000000 00000000DRCL0

--------*3UTIMC0 [R/W]

0--00001U-TIMER 0

000068HSSR1 [R/W]00001000

SIDR1[R]/SODR1[W]XXXXXXXX

SCR1 [R/W]00000100

SMR1 [R/W]00--0---

UART1

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APPENDIX A I/O Map

00006CHUTIM1 [R] (UTIMR1 [W])

00000000 00000000DRCL1

--------*3UTIMC1 [R/W]

0--00001U-TIMER 1

000070HSSR2 [R/W]00001000

SIDR2[R]/SODR2[W]XXXXXXXX

SCR2 [R/W]00000100

SMR2 [R/W]00--0---

UART2

000074HUTIM2 [R] (UTIMR [W])

00000000 00000000DRCL2

--------*3UTIMC2 [R/W]

0--00001U-TIMER 2

000078HSSR3 [R/W]00001000

SIDR3[R]/SODR[W]XXXXXXXX

SCR3 [R/W]00000100

SMR3 [R/W]00--0---

UART3

00007CHUTIM3 [R] (UTIMR [W])

00000000 00000000DRCL3

--------*3UTIMC3 [R/W]

0--00001U-TIMER 3

000080HSSR4 [R/W]00001000

SIDR4[R]/SODR[W]XXXXXXXX

SCR4 [R/W]00000100

SMR4 [R/W]00--0---

UART4

000084HUTIM4 [R] (UTIMR [W])

00000000 00000000DRCL4

--------*3UTIMC4 [R/W]

0--00001U-TIMER 4

000088H -------- --------Reserved

00008CH -------- --------

000090HPWCCL[R/W]

0000--00PWCCH[R/W]

00-00000--------

PWC000094H

PWCD[R]XXXXXXXX_XXXXXXXX

--------

000098HPWCC2[R/W]

000-----Reserved --------

00009CHPWCUD[R]

XXXXXXXX_XXXXXXXX--------

0000A0H -------- --------

Reserved0000A4H -------- --------0000A8H -------- --------0000ACH -------- --------

0000B0HIFN0 [R]

00000000IFRN0 [R/W]

00000000IFCR0 [R/W]

00-00000IFDR0 [R/W]XXXXXXXX

I2C interface ch00000B4H

IBCR0 [R/W]00000000

IBSR0 [R]00000000

ITBA0 [R/W]------00 00000000

0000B8HITMK0 [R/W]

00----11 11111111ISMK0 [R/W]

01111111ISBA0 [R/W]

00000000

0000BCH -IDAR0 [R/W]

00000000ICCR0 [R/W]

00011111IDBL0 [R/W]

-------0

0000C0HIFN1 [R]

00000000IFRN1 [R/W]

00000000IFCR1 [R/W]


I2C interface ch10000C4H

IBCR1 [R/W]00000000

IBSR1 [R]00000000

ITBA1 [R/W]------00 00000000

0000C8HITMK1 [R/W]

00----11 11111111ISMK1 [R/W]

01111111ISBA1 [R/W]

00000000

0000CCH -IDAR1 [R/W]

00000000ICCR1 [R/W]

00011111IDBL1 [R/W]

-------0

0000D0HIFN2 [R]

00000000IFRN2 [R/W]

00000000IFCR2 [R/W]


I2C interface ch2


AddressRegister

Block+0 +1 +2 +3

672

APPENDIX A I/O Map

0000D4HIBCR2 [R/W]

00000000IBSR2 [R]00000000

ITBA2 [R/W]------00 00000000

I2C interface ch20000D8HITMK2 [R/W]

00----11 11111111ISMK2 [R/W]

01111111ISBA2 [R/W]

00000000

0000DCH -IDAR2 [R/W]

00000000ICCR2 [R/W]

00011111IDBL2 [R/W]

-------0

0000E0HIFN3 [R]

00000000IFRN3 [R/W]

00000000IFCR3 [R/W]


I2C interface ch30000E4H

IBCR3 [R/W]00000000

IBSR3 [R]00000000

ITBA3 [R/W]------00 00000000

0000E8HITMK3 [R/W]

00----11 11111111ISMK3 [R/W]

01111111ISBA3 [R/W]

00000000

0000ECH -IDAR3 [R/W]

00000000ICCR3 [R/W]

00011111IDBL3 [R/W]

-------0

0000F0HT0LPCR [R/W]

-----000T0CCR [R/W]

0-010000T0TCR [R/W]

00000000T0R [R/W]---00000

Multifunctional timer

0000F4HT0DRR [R/W]

XXXXXXXX XXXXXXXXT0CRR [R/W]

XXXXXXXX XXXXXXXX

0000F8HT1LPCR [R/W]

-----000T1CCR [R/W]

0-000000T1TCR[R/W]

00000000T1R [R/W]---00000

0000FCHT1DRR [R/W]


XXXXXXXX XXXXXXXX

000100HT2LPCR [R/W]

-----000T2CCR [R/W]

0-000000T2TCR [R/W]

00000000T2R [R/W]---00000

000104HT2DRR [R/W]


XXXXXXXX XXXXXXXX

000108HT3LPCR [R/W]

-----000T3CCR [R/W]

0-000000T3TCR [R/W]

00000000T3R [R/W]---00000

00010CHT3DRR [R/W]


XXXXXXXX XXXXXXXX

000110HTMODE [R/W]-------- -----0--

- -

000114H|

00011FH

-------- -------- Reserved

000120HPTMR0 [R]

11111111_11111111PCSR0 [W]

XXXXXXXX_XXXXXXXXPPG0

000124HPDUT0 [W]

XXXXXXXX_XXXXXXXXPCNH0 [R/W]

00000000PCNL0 [R/W]

00000000

000128HPTMR1 [R]

11111111_11111111PCSR1 [W]


00012CHPDUT1 [W]


00000000PCNL1 [R/W]

00000000

000130HPTMR2 [R]

11111111_11111111PCSR2 [W]


00134HPDUT2 [W]


00000000PCNL2 [R/W]

00000000


AddressRegister

Block+0 +1 +2 +3

673

APPENDIX A I/O Map

000138HPTMR3 [R]

11111111_11111111PCSR3[W]


00013CHPDUT3 [W]


00000000PCNL3 [R/W]

00000000000140H

|00014CH

--------

000150H|

00015CH

--------

000160H --------

Reserved

000164H --------000168H --------00016CH --------000170H --------000174H --------000178H --------00017CH --------000180H --------

Reserved

000184H --------000188H --------00018CH --------000190H --------000194H --------000198H --------00019CH --------0001A0H

|0001FCH

-------- Reserved

000200HDMACA0 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMAC

000204HDMACB0 [R/W]

00000000 00000000 00000000 00000000

000208HDMACA1 [R/W]


00020CHDMACB1 [R/W]

00000000 00000000 00000000 00000000

000210HDMACA2 [R/W]


000214HDMACB2 [R/W]

00000000 00000000 00000000 00000000

000218HDMACA3 [R/W]


00021CHDMACB3 [R/W]

00000000 00000000 00000000 00000000


AddressRegister

Block+0 +1 +2 +3

674

APPENDIX A I/O Map

000220HDMACA4 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXXDMAC

000224HDMACB4 [R/W]

00000000 00000000 00000000 00000000000228H --------00022CH

|00023CH

-------- Reserved

000240HDMACR [R/W]

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXXDMAC

000244H|

0002FCH

--------

000300H|

0003ECH

--------

0003F0HBSD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search Module0003F4H

BSD1 [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8HBSDC [W]


0003FCHBSRR [R]


000400HDDR0 [R/W]00000000

DDR1 [R/W]00000000

DDR2 [R/W]00000000

DDR3 [R/W]00000000

R-bus Data Direction Register

000404HDDR4 [R/W]00000000

DDR5 [R/W]00000000

-DDR7 [R/W]

--000000

000408HDDR8 [R/W]00000000

DDR9 [R/W]00000000

DDRA [R/W]-----000

DDRB [R/W]00000000

00040CHDDRC [R/W]

00000000- - -

000410HPFR0 [R/W]

0--00000PFR1 [R/W]00000000

PFR2 [R/W]00000000

PFR3 [R/W]00000000

R-busPort Function Register

000414HPFR4 [R/W]

0000--00PFR5 [R/W]11111111

Reserved Reserved

000418H Reserved Reserved Reserved Reserved

00041CH ReservedPFRD [R/W]

---11111- -

000420H|

00043CH

-------- Reserved


AddressRegister

Block+0 +1 +2 +3

675

APPENDIX A I/O Map

000440HICR00 [R/W]

---11111ICR01 [R/W]

---11111ICR02[R/W]

---11111ICR03 [R/W]

---11111

Interrupt Control unit

000444HICR04 [R/W]

---11111ICR05 [R/W]

---11111ICR06 [R/W]

---11111ICR07 [R/W]

---11111

000448HICR08 [R/W]

---11111ICR09 [R/W]

---11111ICR10 [R/W]

---11111ICR11 [R/W]

---11111

00044CHICR12 [R/W]

---11111ICR13 [R/W]

---11111ICR14 [R/W]

---11111ICR15 [R/W]

---11111

000450HICR16 [R/W]

---11111ICR17 [R/W]

---11111ICR18 [R/W]

---11111ICR19 [R/W]

---11111

000454HICR20 [R/W]

---11111ICR21 [R/W]

---11111ICR22 [R/W]

---11111ICR23 [R/W]

---11111

000458HICR24 [R/W]

---11111ICR25 [R/W]

---11111ICR26 [R/W]

---11111ICR27 [R/W]

---11111

00045CHICR28 [R/W]

---11111ICR29 [R/W]

---11111ICR30 [R/W]

---11111ICR31 [R/W]

---11111

000460HICR32 [R/W]

---11111ICR33 [R/W]

---11111ICR34 [R/W]

---11111ICR35 [R/W]

---11111

000464HICR36 [R/W]

---11111ICR37 [R/W]

---11111ICR38 [R/W]

---11111ICR39 [R/W]

---11111

000468HICR40 [R/W]

---11111ICR41 [R/W]

---11111ICR42 [R/W]

---11111ICR43 [R/W]

---11111

00046CHICR44 [R/W]

---11111ICR45 [R/W]

---11111ICR46 [R/W]

---11111ICR47 [R/W]

---11111000470H

|00047CH

--------

Clock Control unit000480H

RSRR [R/W]

10000000 *2STCR [R/W]

00110011 *2TBCR [R/W]

00XXXX00 *1CTBR [W]

XXXXXXXX

000484HCLKR [R/W]

00000000 *1WPR

--------*3DIVRO [R/W]

00000011 *1DIVR1[R/W]

00000000 *1

000488H - -OSCCR [R/W]

XXXXXXX0-

00048CHWPCR [R/W] B

00---000- - - Watch timer

000490HOSCR [R/W] B

00---000- - -

Main oscillation stabilization time wait timer

000494H|

0005FCH

-------- Reserved

000600H|

00063FH

-------- Reserved


AddressRegister

Block+0 +1 +2 +3

676

APPENDIX A I/O Map

000640HASR0 [R/W]

00000000 00000000 *1ACR0 [R/W]

1111XX00 00000000 *1

T-unit

000644HASR1 [R/W]

XXXXXXXX XXXXXXXX *1ACR1 [R/W]

XXXXXXXX XXXXXXXX *1

000648HASR2 [R/W]



00064CHASR3 [R/W]



000650HASR4 [R/W]



000654HASR5 [R/W]



000658HASR6 [R/W]



00065CHASR7 [R/W]



000660HAWR0 [R/W]

011111111 11111111 *1AWR1 [R/W]


000664HAWR2 [R/W]

XXXXXXXX XXXXXXXX *1AWR3 [R/W]


000668HAWR4 [R/W]



00066CHAWR6 [R/W]



000670H --------000674H --------

000678HIOWR0 [R/W]XXXXXXXX

IOWR1 [R/W]XXXXXXXX

IOWR2 [R/W]XXXXXXXX

--------

00067CH --------

000680HCSER [R/W]000000001

CSHR [R/W]11111111

-TCR [R/W]00000000

000684H --------000684H

|0007F8H

-------- Reserved

0007FCH -MODR [W]XXXXXXXX

- -

000800H|

000AFCH

- Reserved


AddressRegister

Block+0 +1 +2 +3

677

APPENDIX A I/O Map

000B00HESTS0 [R/W]

X0000000ESTS1 [R/W]XXXXXXXX

ESTS2 [R]1XXXXXXX

-

DSU

000B04HECTL0 [R/W]

0X000000ECTL1 [R/W]

00000000ECTL2 [W]000X0000

ECTL3 [R/W]00X00X11

000B08HECNT0 [W]XXXXXXXX

ECNT1 [W]XXXXXXXX

EUSA [W]XXX00000

EDTC [W]0000XXXX

000B0CHEWP1 [R]

00000000 00000000-

000B10HEDTR0 [W]

XXXXXXXX XXXXXXXXEDTR1 [W]

XXXXXXXX XXXXXXXX000B14H

|000B1CH

--------

000B20HEIA0 [W]


000B24HEIA1 [W]


000B28HEIA2 [W]


000B2CHEIA3 [W]


000B30HEIA4 [W]


000B34HEIA5 [W]


000B38HEIA6 [W]


000B3CHEIA7 [W]


000B40HEDTA [R/W]


000B44HEDTM [R/W]


000B48HEOA0 [W]


000B4CHEOA1 [W]


000B50HEPCR [R/W]


000B54HEPSR [R/W]


000B58HEIAM0 [W]


000B5CHEIAM1 [W]


000B60HEOAM0/EODM0 [W]



AddressRegister

Block+0 +1 +2 +3

678

APPENDIX A I/O Map

000B64HEOAM1/EODM1 [W]


DSU000B68HEOD0 [W]


000B6CHEOD1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX000B70H

|000FFCH

-------- Reserved

001000HDMASA0 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMAC

001004HDMADA0 [R/W]


001008HDMASA1 [R/W]


00100CHDMADA1 [R/W]


001010HDMASA2 [R/W]


001014HDMADA2 [R/W]


001018HDMASA3 [R/W]


00101CHDMADA3 [R/W]


001020HDMASA4 [R/W]


001024HDMADA4 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX001028H

|006FFCH

- Reserved

007000HFLCR [R/W]0110_0000

-Program FLASH I/F

007004HFLWC [R/W]0001_0011

-

007008H|

0070FFH

- Reserved

*1:Register whose initial value depends on the reset level. The registers at the INIT level are indicated.*2:Register whose initial value depends on the reset level. The registers at the INIT level due to the INIT pin

are indicated.*3:Reserved register. Access is disabled.


AddressRegister

Block+0 +1 +2 +3

679

APPENDIX A I/O Map


AddressRegister

Block+0 +1 +2 +3

00050000H|

0005FFFFH

--------

RESERVEDReserved

00060000HFIF 00o [R]

XXXXXXXX_XXXXXXXXFIF 00i [W]

XXXXXXXX_XXXXXXXX

USBFunction

00060004HFIF 01 [R]

XXXXXXXX_XXXXXXXXFIF 02 [W]

XXXXXXXX_XXXXXXXX

00060008HFIF 03 [W]

XXXXXXXX_XXXXXXXX-

0006000CH|

0006001FH

--------

RESERVED

00060020H-

RESERVEDCONT1 [R/W]

000XX0XX_XXX00000

00060024HCONT2 [R/W]

XXXXXXXX_XXX00000CONT3 [R/W]

XXXXXXXX_XXX00000

00060028HCONT4 [R/W]


XXXXXXXX_XXXX00XX

0006002CHCONT6 [R/W]

XXXXXXXX_XXXX00XXCONT7 [R/W]

XXXXXXXX_XXX00000

00060030HCONT8 [R/W]


0XX0XXXX_0XXX0000

00060034HCONT10 [R/W]

00000000_X00000XXTTSIZE [R/W]

00010001_00010001

00060038HTRSIZE [R/W]

00010001_00010001-

RESERVED

0006003CH--------

RESERVED

00060040HRSIZE0 [R]

XXXXXXXX_XXXX0000-

RESERVED

00060044HRSIZE1 [R]

XXXXXXXX_X0000000-

RESERVED

00060048H|

0006005FH

--------

RESERVED

00060060H-

RESERVEDST1 [R/W]

XXXXXX00_00000000

00060064H--------

RESERVED

00060068HST2 [R]

XXXXXXXX_XXX00000ST3 [R/W]

00XXXXXX_X0000000USB

Function

680

APPENDIX A I/O Map

0006006CHST4 [R/W]

XXXXX000_00000000ST5 [R/W]

0XX00XXX_XX000000USB

Function00060070H

|0006007DH

--------

RESERVED

00060080H|

0006FFFDH

--------

RESERVEDRESERVED

0006FFFEHRESET-0--0----

RESERVED -

00078000HOSD_VADR [W]

XXXXXXXX_XXXXXXXXOSD_CD1 [W]

XXXXXXXX_XXXXXXXX

OSDC (MAIN)

00078004HOSD_CD2 [W]

XXXXXXXX_XXXXXXXXOSD_RCD1 [W]

XXXXXXXX_XXXXXXXX

00078008HOSD_RCD2 [W]

XXXXXXXX_XXXXXXXXOSD_SOC1 [W]

XXXXXXXX_0000XXXX

0007800CHOSD_SOC2 [W]

XXXXXXXX_XXXXXXXXOSD_VDPC [W]

XXXXXXXX_XXXXXXXX

00078010HOSD_HDPC [W]

XXXXXXXX_XXXXXXXXOSD_CVSC [W]

XXXXXXXX_XXXXXXXX

00078014HOSD_SBFCC [W]

XXXXXXXX_XXXXXXXXOSD_THCC [W]

XXXXXXXX_XXXXXXXX

00078018HOSD_GFCC [W]

XXXXXXXX_XXXXXXXXOSD_SBCC1 [W]

XXXXXXXX_XXXXXXXX

0007801CHOSD_SBCC2 [W]

XXXXXXXX_XXXXXXXXOSD_SPCC1 [W]

XXXXXXXX_XXXXXXXX

00078020HOSD_SPCC2 [W]

XXXXXXXX_XXXXXXXXOSD_SPCC3 [W]

XXXXXXXX_XXXXXXXX

00078024HOSD_SPCC4 [W]

XXXXXXXX_XXXXXXXXOSD_SYNCC [W]

XXXXXXXX_XXXXXXXX

00078028H ---- ----

0007802CH ----OSD_IOC1 [W]

XXXXXXXX_XXXXXX00

00078030HOSD_IOC2 [W]

XXXXXXXX_XXXXXXXXOSD_DPC1 [W]

XXXXXXXX_XXXXXXXX

00078034HOSD_DPC2 [W]

XXXXXXXX_XXXXXXXXOSD_DPC3 [W]

XXXXXXXX_XXXXXXXX

00078038HOSD_DPC4 [W]

XXXXXXXX_XXXXXXXXOSD_IRC [W]

XXXXXXXX_XXXXXXXX

0007803CHOSD_PLT0 [W]

XXXXXXXX_XXXXXXXXOSD_PLT1 [W]

XXXXXXXX_XXXXXXXX


AddressRegister

Block+0 +1 +2 +3

681

APPENDIX A I/O Map

00078040HOSD_PLT2 [W]


XXXXXXXX_XXXXXXXX

OSDC (MAIN)

00078044HOSD_PLT4 [W]


XXXXXXXX_XXXXXXXX

00078048HOSD_PLT6 [W]


XXXXXXXX_XXXXXXXX

0007804CHOSD_PLT8 [W]


XXXXXXXX_XXXXXXXX

00078050HOSD_PLT10 [W]


XXXXXXXX_XXXXXXXX

00078054HOSD_PLT12 [W]


XXXXXXXX_XXXXXXXX

00078058HOSD_PLT14 [W]


XXXXXXXX_XXXXXXXX

0007805CHOSD_ACT1 [W]

XXXXXXXX_XXXXXXXXOSD_ACT2 [W]

XXXXXXXX_XXXXXXXX

00078060HOSD_PLACC11 [W]

XXXXXXXX_XXXXXXXXOSD_PLACC12 [W]

XXXXXXXX_XXXXXXXX

00078064HOSD_PLACC2 [W]

XXXXXXXX_XXXXXXXXOSD_PLACC3 [W]

XXXXXXXX_XXXXXXXX

00078068HOSD_PLBCC11 [W]

XXXXXXXX_XXXXXXXXOSD_PLBCC12 [W]

XXXXXXXX_XXXXXXXX

0007806CHOSD_PLBCC2 [W]

XXXXXXXX_XXXXXXXXOSD_PLBCC3 [W]

XXXXXXXX_XXXXXXXX

00078070HOSD_PLCC11[W]

XXXXXXXX_XXXXXXXXOSD_PLCC12[W]

XXXXXXXX_XXXXXXXX

00078074HOSD_PLCCC2[W]

XXXXXXXX_XXXXXXXXOSD_PLCCC3[W]

XXXXXXXX_XXXXXXXX

00078078HOSD_CSC1 [W]

XXXXXXXX_XXXXXXXXOSD_CSC2 [W]

XXXXXXXX_XXXXXXXX

0007807CH|

000780FFH

---- ---- -


AddressRegister

Block+0 +1 +2 +3

682

APPENDIX A I/O Map

00078100HCCOSD_VADR [W]

XXXXXXXX_XXXXXXXXCCOSD_CD1 [W]

XXXXXXXX_XXXXXXXX

OSDC (CC)

00078104HCCOSD_CD2 [W]

XXXXXXXX_XXXXXXXXCCOSD_RCD1 [W]

XXXXXXXX_XXXXXXXX

00078108HCCOSD_RCD2 [W]

XXXXXXXX_XXXXXXXXCCOSD_SOC1 [W]

XXXXXXXX_0000XXXX

0007810CHCCOSD_SOC2 [W]

XXXXXXXX_XXXXXXXXCCOSD_VDPC [W]

XXXXXXXX_XXXXXXXX

00078110HCCOSD_HDPC [W]

XXXXXXXX_XXXXXXXXCCOSD_CVSC [W]

XXXXXXXX_XXXXXXXX

00078114H ----CCOSD_THCC [W]

XXXXXXXX_XXXXXXXX

00078118H ---- ----

0007811CH ---- ----

00078120H ---- ----

00078124H ---- ----

00078128H ---- ----

0007812CH ---- ----

00078130H ----CCOSD_DPC1 [W]

XXXXXXXX_XXXXXXXX

00078134HCCOSD_DPC2 [W]

XXXXXXXX_XXXXXXXXCCOSD_DPC3 [W]

XXXXXXXX_XXXXXXXX

00078138HCCOSD_DPC4 [W]

XXXXXXXX_XXXXXXXXCCOSD_IRC [W]

XXXXXXXX_XXXXXXXX


AddressRegister

Block+0 +1 +2 +3

683

APPENDIX A I/O Map

0007813CHCCOSD_PLT0 [W]

XXXXXXXX_XXXXXXXXCCOSD_PLT1 [W]

XXXXXXXX_XXXXXXXX

OSDC (CC)

00078140HCCOSD_PLT2 [W]


XXXXXXXX_XXXXXXXX



XXXXXXXX_XXXXXXXX



XXXXXXXX_XXXXXXXX

0007814CHCCOSD_PLT8 [W]


XXXXXXXX_XXXXXXXX



XXXXXXXX_XXXXXXXX



XXXXXXXX_XXXXXXXX



XXXXXXXX_XXXXXXXX

0007815CH ---- ----

00078160H|

0007FFFFH

--------

RESERVEDRESERVED


AddressRegister

Block+0 +1 +2 +3

684



Table B-1 shows the interrupt vector table, which gives the interrupt sources and interrupt vector/interrupt control register allocations for the MB91319.

Interrupt Vectors

Table B-1 Interrupt Vector (1 / 3)

Interrupt source

Interrupt numberInterrupt

level Offset Address of TBR default RN

Decimal Hexa-decimal

Reset 0 00 - 3FCH 000FFFFCH -

Mode vector 1 01 - 3F8H 000FFFF8H -

Reserved for system 2 02 - 3F4H 000FFFF4H -

Reserved for system 3 03 - 3F0H 000FFFF0H -

Reserved for system 4 04 - 3ECH 000FFFECH -

Reserved for system 5 05 - 3E8H 000FFFE8H -

Reserved for system 6 06 - 3E4H 000FFFE4H -

No-coprocessor trap 7 07 - 3E0H 000FFFE0H -

Coprocessor error trap 8 08 - 3DCH 000FFFDCH -

INTE instruction 9 09 - 3D8H 000FFFD8H -

Instruction break exception 10 0A - 3D4H 000FFFD4H -

Operand break trap 11 0B - 3D0H 000FFFD0H -

Step trace trap 12 0C - 3CCH 000FFFCCH -

NMI request (tool) 13 0D - 3C8H 000FFFC8H -

Undefined instruction exception 14 0E - 3C4H 000FFFC4H -

NMI request 15 0F 15 (FH) ,fixed 3C0H 000FFFC0H -

External interrupt 0 16 10 ICR00 3BCH 000FFFBCH -

External interrupt 1 17 11 ICR01 3B8H 000FFFB8H -



External interrupt 4 (USB-function) 20 14 ICR04 3ACH 000FFFACH -

External interrupt 5 (OSDC-MAIN) 21 15 ICR05 3A8H 000FFFA8H -

External interrupt 6 (OSDC-CC) 22 16 ICR06 3A4H 000FFFA4H -

685


Reserved for system 23 17 ICR07 3A0H 000FFFA0H -

Reload timer 0 24 18 ICR08 39CH 000FFF9CH 8

Reload timer 1 25 19 ICR09 398H 000FFF98H 9

Reload timer 2 26 1A ICR10 394H 000FFF94H 10

UART0 (Reception completed) 27 1B ICR11 390H 000FFF90H 0

UART1 (Reception completed) 28 1C ICR12 38CH 000FFF8CH 1

UART2 (Reception completed) 29 1D ICR13 388H 000FFF88H 2

UART0 (Transmission completed) 30 1E ICR14 384H 000FFF84H 3

UART1 (Transmission completed) 31 1F ICR15 380H 000FFF80H 4

UART2 (Transmission completed) 32 20 ICR16 37CH 000FFF7CH 5

DMAC0 (end or error) 33 21 ICR17 378H 000FFF78H -



DMAC3 (end or error) 36 24 ICR20 36CH 000FFF6CH -


A/D 38 26 ICR22 364H 000FFF64H -

PPG0 39 27 ICR23 360H 000FFF60H -

PPG1 40 28 ICR24 35CH 000FFF5CH -

PPG2 41 29 ICR25 358H 000FFF58H -

PPG3 42 2A ICR26 354H 000FFF54H -

DWC 43 2B ICR27 350H 000FFF50H -

CCD0 44 2C ICR28 34CH 000FFF4CH -

CCD1 45 2D ICR29 348H 000FFF48H -

Main oscillation wait 46 2E ICR30 344H 000FFF44H -

Timebase timer overflow 47 2F ICR31 340H 000FFF40H -

Reserved for system 48 30 ICR32 33CH 000FFF3CH -

Watch timer 49 31 ICR33 338H 000FFF38H -

I2C ch0 50 32 ICR34 334H 000FFF34H -

I2C ch1 51 33 ICR35 330H 000FFF30H -

I2C ch2 52 34 ICR36 32CH 000FFF2CH -

I2C ch3 53 35 ICR37 328H 000FFF28H -


Interrupt source




686


UART3 (Reception completed) 54 36 ICR38 324H 000FFF24H -

UART4 (Reception completed) 55 37 ICR39 320H 000FFF20H -

UART3 (Transmission completed) 56 38 ICR40 31CH 000FFF1CH -

UART4 (Transmission completed) 57 39 ICR41 318H 000FFF18H -

Multifunction timer 0 58 3A ICR42 314H 000FFF14H -

Multifunction timer 1 59 3B ICR43 310H 000FFF10H -

Multifunction timer 2 60 3C ICR44 30CH 000FFF0CH -

Multifunction timer 3 61 3D ICR45 308H 000FFF08H -

Reserved for system 62 3E ICR46 304H 000FFF04H -

Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H -

Reserved for system (used by REALOS*) 64 40 - 2FCH 000FFEFCH -

Reserved for system (used by REALOS*) 65 41 - 2F8H 000FFEF8H -

Reserved for system 66 42 - 2F4H 000FFEF4H -

Reserved for system 67 43 - 2F0H 000FFEF0H -

Reserved for system 68 44 - 2ECH 000FFEECH -

Reserved for system 69 45 - 2E8H 000FFEE8H -



Reserved for system 72 48 - 2DCH 000FFEDCH -

Reserved for system 73 49 - 2D8H 000FFED8H -

Reserved for system 74 4A - 2D4H 000FFED4H -

Reserved for system 75 4B - 2D0H 000FFED0H -

Reserved for system 76 4C - 2CCH 000FFECCH -

Reserved for system 77 4D - 2C8H 000FFEC8H -

Reserved for system 78 4E - 2C4H 000FFEC4H -

Reserved for system 79 4F - 2C0H 000FFEC0H -

Used in INT instruction

80

to

255

50

to

FF

-

2BCH

to

000H

000FFEBCH

to

000FFC00H

-


Interrupt source




687



The built-in dot clock generation PLL requires that the LPF be connected to the CP pin as shown in Figure C-1.

Dot Clock Generation PLL

Figure C-1 CP0 Pin Connection

The LPF constant depends on the oscillation frequency. Contact Fujitsu for the recommendedvalue of the LPF constant.

Table C-1 shows examples of recommended values.

Even in the built-in PLL generating slicer clock, a CPO pin needs to be connected with the LPFdescribed below.

R

C1 C2

CP0R2

C1 C2

VCI

CP0R1

0.25 µm: EVA, FLASH 0.18 µm: EVA, FLASH, MASK

Table C-1 Examples of Recommended Values of LPF Constant

HSYNC (kHz)

Division ratioPLL

(MHz)

Output clock (MHz)

VCOCHG[1:0]

External LPF

n m R (Ω) C1 (µF) C2 (pF)

15.75 1204 2 37.93 18.96 VCO1 10 915 0.22 None

31.5 1304 1 41.08 41.08 VCO2 10 915 0.22 None

33.75 1320 1 44.55 44.55 VCO2 10 915 0.22 None

45 1404 1 63.18 63.18 VCO3 10 2k 0.068 2700

48 1428 1 68.54 68.54 VCO3 10 2k 0.068 2700

688


Sample values of the LPF constants are listed below.

Dot Clock

When the OSDC macro is unused, inputs "0" level to the DCKO pin.

Table C-2 0.25 µm: EVA, FLASH

No.HSYNC(kHz)

PLL(MHz)

VCOExternal LPF

R (Ω) C1 (µF) C2 (pF)

1 15.734 32.223 VCO1 1400 0.077 7700

2 31.468 32.223 VCO1 700 0.16 16000

Table C-3 0.18 µm: EVA, FLASH, MASK

No.HSYNC(kHz)

PLL(MHz)

VCOExternal LPF

R1 (Ω) R2 (Ω) C1 (µF) C2 (pF)

1 15.734 32.223 VCO1 3.3 510 0.33 100

689



The USB clock is obtained from an external 48 MHz crystal oscillator or an external 48 MHz clock input.

USB Clock

The external crystal oscillator for the USB clock is controlled in the same way as the CPU crystaloscillator. That is, the external crystal oscillator is stopped in the following modes:

• Stop mode of main clock mode

• Sub-clock mode

Also, when the USB macro is unused, inputs "0" level to the X0B pin.

690



This section describes the macro reset register for controlling the USB function and the OSDC reset.

Figure E-1 Macro Reset Register

• USB-F-RST

Reset signal for USB function. Writing 1 to this bit resets the signal, and writing 0 clears thesignal.

• OSD-RST

Reset signal for the OSDC. Writing 1 to this bit resets the signal, and writing 0 clears thesignal.

Note:

When the OSDC is set the corresponding reset bit to 1, the register access is performed. Therefore,the CPU is stopped (the external interface is used the RDY enabled) because the response is notreturned.

Also, the CPU is stopped when the clock is not supplied to the OSDC.

Accessing to the OSDC is used as follow.

• The state which the corresponding reset bit is cleared 0.

• The state which the corresponding clock is supplied.

7 6 5 4 3 2 1 0

0x0006FFFEHUSB-F-

RSTOSD-RST

CS2X area

Initial value- - -0 --- 0

691



The USBIO of MB91319 series are integrated the low-power consumption mode for the unused USB. Low-power consumption mode is used to set the low-power consumption mode register as follow.

Low-Power Consumption Mode Setting Register

Using way: When writing the data 0x55 at 0006FFFCH, the USB IO is enabled to transit to thelow-power consumption mode. The initial value of this register is 00H when the USBoperation is required to 00H. Returning from the low-power consumption mode, besure to write 00H at 0006FFFCH before the USB operation is started.

7 0

0006FFFCH

CS2X area

Initial value 00H / Write Only

692



This section explains the register settings and recommended setting examples for accessing the macros of the items connected via the external bus interface.

External Bus Interface Setting

The MB91319 has a USB function, and OSDC connected via the external bus interface in thechip.

To access these macros, set the registers of the external bus interface as follows:

CS0 area: Default area (unused)

After reset is canceled, the entire 4 GB CS0 area is indicated. Set the CS0 area in an area thatdoes not overlap other chip select area.

An example of an area that can be set is the area after 0020_0000H.

CS1 area (reserved)

CS2 area

The USB function is connected to the CS2 area.

The USB function is a 16-bit macro that does not require a wait. DBW is set to 01 (16 bits), TYPEis set to 0000 (no external ready), and automatic wait is set to 02 (2 wait).

The address is set to the minimum area size of 64 KB starting from 0006_0000H.

CS3 area

The OSDC are connected to the CS3 area.

The memory stick interface and OSDC are 16-bit macros. The OSDC macro requires an externalready. DBW is set to 01 (16 bits), TYPE is set to 0001 (external ready), and automatic wait is setto 00 (0 wait).

The address is set to the minimum area size of 64 KB starting from 0007_0000H.

693


Recommended Setting Examples

Figure G-1 shows recommended setting examples for the registers of the external bus interface.

Figure G-1 Recommended Setting Examples for the Registers of the External Bus Interface.

// **start initial header program

//CS0X :

// CS1X : (Reserved)

// CS2X : USB-Func (16bit)

// CS3X : OSDC(16bit)

not useldi

ldisthldildi

sthldildisth

ldi

ldisthldildisthldildi

sth

ldi

ldisthldildisthldildi

sth

ldi

ldisthldildisthldilsi

sth

ldildistb

#0x5400,r3

#_ACR0,r4r3,@r4#_AWR0,r6#0x0098,r5

r5,@6#_ASR0,r7#0x0020,r5r5,@r7

#0x0820,r3

#_ACR1,r8r3,@r8#0x0005,r3#_ASR 1, r9r3,@r9#_AWR1,r4#0x2098,r5

r5,@r4

#0x0420,r3

#_ACR2,r8r3,@r8#0x0006,r3#_ASR2,r9r3,@r9#_AWR2,r4#0x2098,r5

r5,@r4

#0x0421.r3

#_ACR3,r8r3,@r8#0x0007,r3#_ASR3,r9r3,@r9#_AWR3,r4#0x0098,r5

r5,@r4

#=CSER,r0#0xOE,r1 // CS0X, CS2X, CS3X enabler1,@r0

// ASX[3:0]=0101,DBW[1:0]=01,BST[1:0]=00,// SREN=0,PFEN=0,WREN=0,LEND=0,TYPE[3:0]=0000// ACR0 for CS0X area access mode// set bus-width & area size// AWR0 for CS0X area access wait// W02 =0: CS delay = 0// W03 =1: RE delay = 1// W05,04=01: WR,WR delay = 0// W07,06=10: RD, WR delay = 2// W15-12=0000: auto wait = 0// set bus-wait// ASR0 for CS0X area base address// set CS0X 0x0020_0000 - 0x003f_ffff

// ASX[3:0]=0000,DBW[1:0]=10,BST[1:0]=00,// SREN=0,PFEN=0,WREN=1,LEND=0,TYPE[3:0]=0000

// CS1X 0x0005_0000-0x0005_ffff

// AWR1 for CS1X area access wait// W02 =0: CS delay = 0// W03 =1: RD delay = 1// W05,04=01: WR, WR delay = 0// W07,06=10: RD, WR delay = 2// W15-12=0010: auto wait = 2// set bus-wait

// ASX[3:00] = 0000,DBW[1:0]=01,BST[1:0]=00,// SREN=0,PFEN=0,WREN=1,LEND=0,TYPE[3:0]=0000

// CS2X 0x0006_0000-0x0006_ffff

// AWR2 for CX1X area access wait// W02 =0: CS delay = 0// W03 =1: RD delay = 1// W5,04=01: WR, WR delay = 0// W07,06=10: RD,WR delay = 2// W15-12=0010: auto wait = 2// set bus-wait

// ASX[3:0]=0000,DBW[1:0]=01,BST[1:0]=00,// SREN=0,PFEN=0,WREN=1,LEND=0,TYPE[3:00]=0001

// CS3X 0x0007_0000-0x0007_ffff

// AWR3 for CS3X area access wait// W02 = 0: CS delay = 0// W03 =1: RD delay = 1// W05,04=01: WR,WR delay = 0// W07,06=10: RD,WR delay = 2// W15-12=0000: auto wait = 0// set bus-wait

694



Table H-1 shows the pin state list table.

Pin State List

Table H-1 MD<3:0>=0000(internal Vector + Single Chip) (1 / 2)

Function macro No NameSpecified function

nameAt initialization (INTX=0)

At SLEEPAt STOP

Function name Initial value HIZ=0 HIZ=1

OSDC1 HSYNC1 - HSYNC1

Input state

Input enabled Input state Input state2 HSYNC2 - HSYNC23 HSYNC3 - HSYNC3

AD

37 PC0/AN0 AN0

Previous state retained


Output Hi-ZInput "0" fixed

38 PC1/AN1 AN139 PC2/AN2 AN240 PC3/AN3 AN341 PC4/AN4 AN442 PC5/AN5 AN543 PC6/AN6 AN644 PC7/AN7 AN745 P20/AN8 P20

Input stateOutput Hi-Z

46 P21/AN9 P2147 P22 P2248 P23 P2349 P24 P2450 P25 P2551 P26 P2652 P27 P2753 P30 P3054 P31 P3155 P32 P32

I2C ch076 P80/SCL0 SCL0 P8077 P81/SDA0 SDA0 P81


UART ch080 P84/SI0 SI0 P8481 P85/SO0 SO0 P8582 P86/SCK0 SCK0 P86


PWC input 86 P92/RIN RIN P92

Multifunction timer input

87 P93/TMI0 TMI0 P9388 P94/TMI1 TMI1 P9489 P95/TMI2 TMI2 P9590 P96/TMI3 TMI3 P96

External interrupt

91 P97/INT0 INT0 P97P: Previous state

retainedF: Input enabled

P: Output Hi-ZF: Input enabled

97 PA0/INT1 INT1 PA098 PA1/INT2 NT2 PA199 PA2/INT3 INT3 PA2

100 NMIX NMIX Input state Input enabled Input enabled Input enabled

695


PPG trigger

101 P33/TRG0 TRG0 P33




Output Hi-ZInput "0" fixed

102 P34/TRG1 TRG1 P34103 P35/TRG2 TRG2 P35104 P36/TRG3 TRG3 P36


I2C ch3.4

107 P41/SCL3 SCL3 P41108 P42/SCL4 SCL4 P42109 P43/SDA3 SDA3 P43110 P44/SDA4 SDA4 P44


UART ch3114 P50/SI3 SI3 P50115 P51/SO3 SO3 P51116 P52/SCK3 SCK3 P52117 P53 - P53118 P54 - P54119 P55 - P55120 P56 - P56121 P57 - P57125 P70 - P70126 P71 - P71127 P72 - P72128 P73 - P73129 P74 - P74

UART 4ch/Reload timer input

130 P00/SI4/TIN0 SI4/TIN0 P00131 P01/SO4/TIN1 SO4/TIN1 P01132 P02/SCK4/TIN2 SCK4/TIN2 P02

Reload timer output133 P03/TOUT0 TO0 P03134 P04/TOUT1 TO1 P04135 P05/TOUT2 TO2 P05

Multifunction timer output

136 P06/TMO0 TMO0 P06137 P07/TMO1 TMO1 P07138 P10/TMO2 TMO2 P10139 P11/TMO3 TMO3 P11

PPG output

140 P12/PPG0 PPG0 P12141 P13/PPG1 PPG1 P13142 P14/PPG2 PPG2 P14143 P15/PPG3 PPG3 P15

A/D trigger 144 P16/ATRG ATRG P16145 P17 - P17146 PB0 - PB0147 PB1 - PB1148 PB2 PB2149 PB3 PB3150 PB4 PB4151 PB5 PB5152 PB6 PB6153 PB7 PB7

USB159 UDM UDM160 UDP - UDP161 B0 - B0

Output "L"


162 B1 - B1

OSDC

163 B2 - B2164 G0 - G0165 G1 - G1166 G2 - G2167 R0 - R0168 R1 - R1169 R2 - R2171 VOB2 - VOB2

Output "L"172 VOB1 - VOB1173 FH - FH174 DCKO - DCKO175 DCKI - DCKI

Input state Input enabled Input state Input state176 VSYNC - VSYNC

Table H-1 MD<3:0>=0000(internal Vector + Single Chip) (2 / 2)

Function macro No NameSpecified function

nameAt initialization (INTX=0)

At SLEEPAt STOP

Function name Initial value HIZ=0 HIZ=1

696


Table H-2 MD<3:0>=0100(serial Writing Mode) (1 / 2)

Function macro No NameAt initialization (INTX=0) At STOP

Specified function name

Function name Initial value P24="H" P24="L"

OSDC 1 HSYNC1 - HSYNC1Input state Input state Input state2 HSYNC2 - HSYNC2

3 HSYNC3 - HSYNC3

AD

37 PC0/AN0 AN0

Input state Input state Input state

38 PC1/AN1 AN139 PC2/AN2 AN240 PC3/AN3 AN341 PC4/AN4 AN442 PC5/AN5 AN543 PC6/AN6 AN644 PC7/AN7 AN745 P20/AN8 AN846 P21/AN9 AN947 P22 P22




48 P23 P23

Programming program start pins

49 P24 P2450 P25 P2551 P26 P2652 P27 P2753 P30 P3054 P31 P3155 P32 P32



Serial data input pin 80 P84/SI0 SI0 P84Serial data output pin 81 P85/SO0 SO0 P85 OutputSerial clock input pin 82 P86/SCK0 SCK0 P86



PWC input 86 P92/RIN RIN P92

Multifunction timer input

87 P93/TMI0 TMI0 P9388 P94/TMI1 TMI1 P9489 P95/TMI2 TMI2 P9590 P96/TMI3 TMI3 P96

External interrupt

91 P97/INT0 INT0 P9797 PA0/INT1 INT1 PA098 PA1/INT2 NT2 PA199 PA2/INT3 INT3 PA2

100 NMIX NMIX Input state Input state Input state

PPG trigger

101 P33/TRG0 TRG0 P33




102 P34/TRG1 TRG1 P34103 P35/TRG2 TRG2 P35104 P36/TRG3 TRG3 P36


I2C ch3.4

107 P41/SCL3 SCL3 P41108 P42/SCL4 SCL4 P42109 P43/SDA3 SDA3 P43110 P44/SDA4 SDA4 P44


UART ch3114 P50/SI3 SI3 P50115 P51/SO3 SO3 P51116 P52/SCK3 SCK3 P52117 P53 - P53118 P54 - P54119 P55 - P55120 P56 - P56121 P57 - P57125 P70 - P70126 P71 - P71127 P72 - P72128 P73 - P73129 P74 - P74

UART 4ch/Reload timer input

130 P00/SI4/TIN0 SI4/TIN0 P00131 P01/SO4/TIN1 SO4/TIN1 P01

Reload timer output132 P02/SCK4/TIN2 SCK4/TIN2 P02133 P03/TOUT0 TO0 P03134 P04/TOUT1 TO1 P04

697


Multifunction timer output

135 P05/TOUT2 TO2 P05




136 P06/TMO0 TMO0 P06137 P07/TMO1 TMO1 P07138 P10/TMO2 TMO2 P10139 P11/TMO3 TMO3 P11

PPG output

140 P12/PPG0 PPG0 P12141 P13/PPG1 PPG1 P13142 P14/PPG2 PPG2 P14143 P15/PPG3 PPG3 P15

A/D trigger 144 P16/ATRG ATRG P16145 P17 - P17146 PB0 - PB0147 PB1 - PB1148 PB2 PB2149 PB3 PB3150 PB4 PB4151 PB5 PB5152 PB6 PB6153 PB7 PB7

USB159 UDM UDM160 UDP UDP

OSDC

161 B0 - B0

Output "L" Output "L" Output "L"

162 B1 - B1163 B2 - B2164 G0 - G0165 G1 - G1166 G2 - G2167 R0 - R0168 R1 - R1169 R2 - R2171 VOB2 - VOB2172 VOB1 - VOB1173 FH - FH174 DCKO - DCKO175 DCKI - DCKI

Input state Input state Input state176 VSYNC - VSYNC

Table H-2 MD<3:0>=0100(serial Writing Mode) (2 / 2)

Function macro No NameAt initialization (INTX=0) At STOP

Specified function name

Function name Initial value P24="H" P24="L"

698



This section provides lists of the FR family instructions.

I.1 How to Read the Instruction Lists

I.2 FR Family Instruction Lists

699


I.1 How to Read the Instruction Lists

Before the lists are presented, the following items are explained to make the lists easier to understand:• How to read the instruction lists• Addressing mode symbols• Instruction format

How to Read the Instruction Lists

1. Instruction name.

• An asterisk (*) indicates an extended instruction that is not contained in the CPUspecifications and is obtained by extension of or addition to the assembler.

2. Symbols indicating addressing modes that can be specified for the operand.

• For the meaning of symbols, see "Addressing Mode Symbols".

3. Instruction format.

4. Instruction code in hexadecimal notation.

5. Number of machine cycles.

• a: Memory access cycle that may be extended by the Ready function.

• b: Memory access cycle that may be extended by the Ready function. However, the cycleis interlocked if a direct instruction references a register intended for an LD operation,increasing the number of execution cycles by 1.

• c: Interlocked if the direct instruction is an instruction that reads or writes to R15, SSP, orUSP, or an instruction in instruction format A. The number of execution cycles increasesby 1 or 2.

• d: Interlocked if the direct instruction references MDH/MDL. The number of executioncycles increases to 2.

• The minimum for a, b, c, and d is 1 cycle.

6. Indicates a flag change.

• Flag change C: Change -: No change 0: Clear 1: Set

• Flag meaning N: Negative flag Z: Zero flag V: Overflow flag C: Carry flag

7. Instruction operation.

Mnemonic Type OP CYCLE NZVC Operation Remarks

ADD*ADD

Rj, Rj#s5, Rj

,,

AC,,

AGA4,,

11,,

CCCCCCCC

,,

Ri + Rj → RjRi + s5 → Ri

,,

-

1. 2. 3. 4. 5. 6. 7.

700


Addressing Mode Symbols

Table I.1-1 Explanation of Addressing Mode Symbols (1 / 2)

Symbol Meaning

Ri Register direct (R0 to R15, AC, FP, SP)

Rj Register direct (R0 to R15, AC, FP, SP)

R13 Register direct (R13, AC)

Ps Register direct (program status register)

Rs Register direct (TBR, RP, SSP, USP, MDH, MDL)

CRi Register direct (CR0 to CR15)

CRj Register direct (CR0 to CR15)

#i8Unsigned 8-bit immediate (-128 to 255)Note: -128 to -1 is handled as 128 to 255.

#i20Unsigned 20-bit immediate (-0X80000b to 0XFFFFF)Note: -0X7FFFF to -1 is handled as 0X7FFFF to 0XFFFFF.

#i32Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF)Note: -0X80000000 to -1 is handled as 0X80000000 to 0XFFFFFFFF.

#s5 Signed 5-bit immediate (-16 to 15)

#s10 Signed 10-bit immediate (-512 to 508, multiples of 4 only)

#u4 Unsigned 4-bit immediate (0 to 15)



#u10 Unsigned 10-bit immediate (0 to 1020, multiples of 4 only)

@dir8 Unsigned 8-bit direct address (0 to 0XFF)

@dir9 Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)

@dir10 Unsigned 10-bit direct address (0 to 0X3FC, multiples of 4 only)

label9 Signed 9-bit branch address (-0X100 to 0XFC, multiples of 2 only)

label12 Signed 12-bit branch address (-0X800 to 0X7FC, multiples of 2 only)

label20 Signed 20-bit branch address (-0X80000 to 0X7FFFF)

label32 Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF)

@Ri Register indirect (R0 to R15, AC, FP, SP)

@Rj Register indirect (R0 to R15, AC, FP, SP)

@(R13,Rj) Register relative indirect (Rj: R0 to R15, AC, FP, SP)

@(R14,disp10) Register relative indirect (disp10: -0X200 to 0X1FC, multiples of 4 only)

701


@(R14,disp9) Register relative indirect (disp9: -0X100 to 0XFE multiples of 2 only)

@(R14,disp8) Register relative indirect (disp8: -0X80 to 0X7F)

@(R15,udisp6) Register relative indirect (udisp6: 0 to 60, multiples of 4 only)

@Ri+ Register indirect with post-increment (R0 to R15, AC, FP, SP)

@R13+ Register indirect with post-increment (R13, AC)

@SP+ Stack pop

@-SP Stack push

(reglist) Register list

Table I.1-1 Explanation of Addressing Mode Symbols (2 / 2)

Symbol Meaning

702


Instruction Format

Table I.1-2 shows the instruction format.

Table I.1-2 Instruction Format

Type Instruction format

A

B

C

C’

D

E

F

16 bitMSB LSB

8 4 4

OP Rj Ri

4 8 4

OP i8/o8 Ri

8 4 4

OP Riu4/m4

7 5 4

s5/u5 Ri

ADD, ADDN, CMP, LSL, LSR, ASR

OP

8 8

OPu8/rel8/dir/reglist

8 4 4

OP SUB-OP Ri

OP rel11

5 11

703


I.2 FR Family Instruction Lists

The FR family instruction lists are presented in the order listed below.

FR Family Instruction Lists

Table I.2-1 Add-Subtract Instructions

Table I.2-2 Compare Instructions

Table I.2-3 Logic Instructions

Table I.2-4 Bit Manipulation Instructions

Table I.2-5 Multiply Instructions

Table I.2-6 Shift Instructions

Table I.2-7 Immediate Set/16-bit/32-bit Immediate Transfer Instructions

Table I.2-8 Memory Load Instructions

Table I.2-9 Memory Store Instructions

Table I.2-10 Register-to-Register Transfer Instructions

Table I.2-11 Normal Branch (No Delay) Instructions

Table I.2-12 Delayed Branch Instructions

Table I.2-13 Other Instructions

Table I.2-14 20-Bit Normal Branch Macro Instructions

Table I.2-15 20-Bit Delayed Branch Macro Instructions



Table I.2-18 Direct Addressing Instructions

Table I.2-19 Resource Instructions

Table I.2-20 Coprocessor Control Instructions

704


Add-Subtract Instructions

Compare Instructions

Table I.2-1 Add-Subtract Instructions


ADD Rj, Ri A A6 1 CCCC Ri + Rj → Ri

*ADD #s5, Ri C’ A4 1 CCCC Ri + s5 → Ri The assembler treats the highest-order bit as the sign.

ADD #u4, Ri C A4 1 CCCC Ri + extu(i4) → Ri Zero extension

ADD2 #u4, Ris C A5 1 CCCC Ri + extu(i4) → Ri Minus extension

ADDC Rj, Ri A A7 1 CCCC Ri + Rj + c → Ri Addition with carry

ADDN Rj, Ri A A2 1 ---- Ri + Rj → Ri

*ADDN #s5, Ri C’ A0 1 ---- Ri + s5 → Ri The assembler treats the highest-order bit as the sign.

ADDN #u4, Ri C A0 1 ---- Ri + extu(i4) → Ri Zero extension

ADDN2 #u4, Ri C A1 1 ---- Ri + extu(i4) → Ri Minus extension

SUB Rj, Ri A AC 1 CCCC Ri - Rj → Ri

SUBC Rj, Ri A AD 1 CCCC Ri - Rj - c → Ri Addition with carry

SUBN Rj, Ri A AE 1 ---- Ri - Rj → Ri

Table I.2-2 Compare Instructions


CMP Rj, Ri A AA 1 CCCC Ri + Rj

*CMP #s5, Ri C’ A8 1 CCCC Ri + s5 The assembler treats the highest-order bit as the sign.

CMP #u4, Ri C A8 1 CCCC Ri + extu(i4) Zero extension

CMP2 #u4, Ri C A9 1 CCCC Ri + extu(i4) Minus extension

705


Logic Instructions

Table I.2-3 Logic Instructions


AND Rj, Ri A 82 1 CC-- Ri &= Rj Word

AND Rj, @Ri A 84 1+2a CC-- (Ri) &= Rj Word

ANDH Rj, @Ri A 85 1+2a CC-- (Ri) &= Rj Halfword

ANDB Rj, @Ri A 86 1+2a CC-- (Ri) &= Rj Byte

OR Rj, Ri A 92 1 CC-- Ri | = Rj Word

OR Rj, @Ri A 94 1+2a CC-- (Ri) | = Rj Word

ORH Rj, @Ri A 95 1+2a CC-- (Ri) | = Rj Halfword

ORB Rj, @Ri A 96 1+2a CC-- (Ri) | = Rj Byte

EOR Rj, Ri A 9A 1 CC-- Ri ^ = Rj Word

EOR Rj, @Ri A 9C 1+2a CC-- (Ri) ^ = Rj Word

EORH Rj, @Ri A 9D 1+2a CC-- (Ri) ^ = Rj Halfword

EORB Rj, @Ri A 9E 1+2a CC-- (Ri) ^ = Rj Byte

706


Bit Manipulation Instructions

Table I.2-4 Bit Manipulation Instructions


BANDL #u4, @Ri C 80 1+2a ---- (Ri)&=(0xF0+u4) Low-order 4 bits are manipulated.

BANDH #u4, @Ri C 81 1+2a ---- (Ri)&=((u4<<4)+0x0F) High-order 4 bits are manipulated.

*BAND #u8, @Ri*1 ---- (Ri)&=u8

BORL #u4, @Ri C 90 1+2a ---- (Ri) | = u4 Low-order 4 bits are manipulated.

BORH #u4, @Ri C 91 1+2a ---- (Ri) | = (u4<<4) High-order 4 bits are manipulated.

*BOR #u8, @Ri*2 ---- (Ri) | = u8

BEORL #u4, @Ri C 98 1+2a ---- (Ri) ^ = u4 Low-order 4 bits are manipulated.

BEORH #u4, @Ri C 99 1+2a ---- (Ri) ^ = (u4<<4) High-order 4 bits are manipulated.

*BEOR #u8, @Ri*3 ---- (Ri) ^ = u8

BTSTL #u4, @Ri C 88 2+a 0C-- (Ri) & u4 Low-order 4 bits are manipulated.

BTSTH #u4, @Ri C 89 2+a CC-- (Ri) & (u4<<4) High-order 4 bits are manipulated.

*1: The assembler generates BANDL if the bit is set at u8&0x0F, and BANDH if the bit is set at u8&0xF0. In some cases, both BANDL and BANDH may be generated.

*2: The assembler generates BORL if the bit is set at u8&0x0F, and BORH if the bit is set at u8&0xF0. In some cases, both BORL and BORH are generated.

*3: The assembler generates BEORL if the bit is set at u8&0x0F, and BEORH if the bit is set at u8&0xF0. In some cases, both BEORL and BEORH are generated.

707


Multiply Instructions

Table I.2-5 Multiply Instructions


MUL Rj,Ri A AF 5 CCC- Ri * Rj → MDH,MDL 32bit*32bit=64bit

MULU Rj,Ri A AB 5 CCC- Ri * Rj → MDH,MDL No sign

MULH Rj,Ri A BF 3 CC-- Ri * Rj → MDL 16bit*16bit=32bit

MULUH Rj,Ri A BB 3 CC-- Ri * Rj → MDL No sign

DIV0S Ri E 97-4 1 ---- Step operation

DIV0U Ri E 97-5 1 ---- 32bit/32bit=32bit

DIV1 Ri E 97-6 d -C-C

DIV2 Ri E 97-7 1 -C-C

DIV3 E 9F-6 1 ----

DIV4S E 9F-7 1 ----

*DIV Ri*1 36 -C-C MDL / Ri → MDL, MDL % Ri → MDH

*DIVU Ri*2 -C-C MDL / Ri → MDL, MDL % Ri → MDH

*1: DIV0S, DIV1 x 32, DIV2, DIV3, or DIV4S is generated. The instruction code length becomes 72 bytes.*2: DIV0U or DIV1 x 32 is generated. The instruction code length becomes 66 bytes.

708


Shift Instructions

Immediate Set/16-bit/32-bit Immediate Transfer Instructions

Table I.2-6 Shift Instructions


LSL Rj, Ri A B6 1 CC-C Ri << Rj → Ri Logical shift

*LSL #u5, Ri (u5:0-31) C’ B4 1 CC-C Ri << u5 → Ri

LSL #u4, Ri C B4 1 CC-C Ri << u4 → Ri

LSL2 #u4, Ri C B5 1 CC-C Ri <<(u4+16) → Ri

LSR Rj, Ri A B2 1 CC-C Ri >> Rj → Ri Logical shift

*LSR #u5, Ri (u5:0-31) C’ B0 1 CC-C Ri >> u5 → Ri

LSR #u4, Ri C B0 1 CC-C Ri >> u4 → Ri

LSR2 #u4, Ri C B1 1 CC-C Ri >>(u4+16) → Ri

ASR Rj, Ri A BA 1 CC-C Ri >> Rj → Ri Arithmetic shift

*ASR #u5, Ri (u5:0-31) C’ B8 1 CC-C Ri >> u5 → Ri

ASR #u4, Ri C B8 1 CC-C Ri >> u4 → Ri

ASR2 #u4, Ri C B9 1 CC-C Ri >>(u4+16) → Ri

Table I.2-7 Immediate Set/16-bit/32-bit Immediate Transfer Instructions


LDI:32 #i32, Ri E 9F-8 3 ---- i32 → Ri

LDI:20 #i20, Ri C 9B 2 ---- i20 → Ri High-order 12 bits are zero-extended.

LDI:8 #i8, Ri B C0 1 ---- i8 → Ri High-order 24 bits are zero-extended.

*LDI # i8 | i20 | i32 ,Ri* i8 | i20 | i32 → Ri

*: If the immediate data is represented as absolute values, the assembler selects automatically from i8, i20, and i32.If immediate data contains a relative value or external reference symbol, i32 is selected.

709


Memory Load Instructions

Table I.2-8 Memory Load Instructions


LD @Rj, Ri A 04 b ---- (Rj) → Ri

LD @(R13,Rj), Ri A 00 b ---- (R13+Rj) → Ri

LD @(R14,disp10), Ri B 20 b ---- (R14+disp10) → Ri

LD @(R15,udisp6), Ri C 03 b ---- (R15+udisp6) → Ri

LD @R15+, Ri E 07-0 b ---- (R15) → Ri,R15+=4

LD @R15+, Rs E 07-8 b ---- (R15) → Rs, R15+=4 Rs: Special register *

LD @R15+, PS E 07-9 1+a+b CCCC (R15) → PS, R15+=4

LDUH @Rj, Ri A 05 b ---- (Rj) →Ri Zero extension

LDUH @(R13,Rj), Ri A 01 b ---- (R13+Rj) →Ri Zero extension

LDUH @(R14,disp9), Ri B 40 b ---- (R14+disp9) →Ri Zero extension

LDUB @Rj, Ri A 06 b ---- (Rj) →Ri Zero extension

LDUB @(R13,Rj), Ri A 02 b ---- (R13+Rj) →Ri Zero extension

LDUB @(R14,disp8), Ri B 6 b ---- (R14+disp8) →Ri Zero extension

*: Special register Rs: TBR, RP, USP, SSP, MDH, and MDLNote:In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:disp10/4 → o8, disp9/2 → o8, disp8 → o8; disp10, disp9, and disp8 have a sign.udisp6/4 → o4; udisp6 has no sign.

710


Memory Store Instructions

Register-to-Register Transfer Instructions

Table I.2-9 Memory Store Instructions


ST Ri, @Rj A 14 a ---- Ri → (Rj) Word

ST Ri, @(R13,Rj) A 10 a ---- Ri → (R13+Rj) Word

ST Ri, @(R14,disp10) B 30 a ---- Ri → (R14+disp10) Word

ST Ri, @(R15,udisp6) C 13 a ---- Ri → (R15+udisp6)

ST Ri, @-R15 E 17-0 a ---- R15-=4,Ri → (R15)

ST Rs, @-R15 E 17-8 a ---- R15-=4, Rs → (R15) Rs: Special register *

ST PS, @-R15 E 17-9 a ---- R15-=4, PS → (R15)

STH Ri, @Rj A 15 a ---- Ri → (Rj) Halfword

STH Ri, @(R13,Rj) A 11 a ---- Ri → (R13+Rj) Halfword

STH Ri, @(R14,disp9) B 50 a ---- Ri → (R14+disp9) Halfword

STB Ri, @Rj A 16 a ---- Ri → (Rj) Byte

STB Ri, @(R13,Rj) A 12 a ---- Ri → (R13+Rj) Byte

STB Ri, @(R14,disp8) B 7 a ---- Ri → (R14+disp8) Byte

*: Special register Rs: TBR, RP, USP, SSP, MDH, and MDLNote:In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:disp10/4 → o8, disp9/2 → o8, disp8 → o8; disp10, disp9, and disp8 have a sign.udisp6/4 → o4; udisp6 has no sign.

Table I.2-10 Register-to-Register Transfer Instructions


MOV Rj, Ri A 8B 1 ---- Rj → Ri Transfer between general-purpose registers

MOV Rs, Ri A B7 1 ---- Rs → Ri Rs: Special register *

MOV Ri, Rs A B3 1 ---- Ri → Rs Rs: Special register *

MOV PS, Ri E 17-1 1 ---- PS → Ri

MOV Ri, PS E 07-1 c CCCC Ri → PS

*: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL

711


Normal Branch (No Delay) Instructions

Table I.2-11 Normal Branch (No Delay) Instructions


JMP @Ri E 97-0 2 ---- Ri → PC

CALL label12 F D0 2 ---- PC+2→RP ,PC+2+(label12-PC-2)→PC

CALL @Ri E 97-1 2 ---- PC+2→RP ,Ri→PC

RET E 97-2 2 ---- RP → PC Return

INT #u8 D AC 3+3a CCCC SSP-=4,PS → (SSP),SSP-=4,PC+2 → (SSP),0→ I flag,0 → S flag,(TBR+0x3FC-u8x4) → PC

INTE E 9F-3 3+3a SSP-=4,PS → (SSP),SSP-=4,PC+2 → (SSP),0 → S flag,(TBR+0x3D8) →PC

For emulator

RETI E 97-3 2+2a CCCC (R15) → PC,R15-=4,(R15) → PS,R15-=4

BRA label9 D E0 2 ---- PC+2+(label9-PC-2) →PC

BNO label9 D E1 1 ---- No branch

BEQ label9 D E2 2/1 ---- if(Z==1) thenPC+2+(label9-PC-2) →PC

BNE label9 D E3 2/1 ---- s/Z==0

BC label9 D E4 2/1 ---- s/C==1

BNC label9 D E5 2/1 ---- s/C==0

BN label9 D E6 2/1 ---- s/N==1

BP label9 D E7 2/1 ---- s/N==0

BV label9 D E8 2/1 ---- s/V==1

BNV label9 D E9 2/1 ---- s/V==0

BLT label9 D EA 2/1 ---- s/V xor N==1

BGE label9 D EB 2/1 ---- s/V xor N==0

BLE label9 D EC 2/1 ---- s/(V xor N) or Z==1

BGT label9 D ED 2/1 ---- s/(V xor N) or Z==0

BLS label9 D EE 2/1 ---- s/C or Z==1

BHI label9 D EF 2/1 ---- s/C or Z==0

Note:• "2/1" under CYCLE indicates 2 when branching occurs and 1 when branching does not occur.• In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below:

(label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8; label12 and label9 have a sign.• To execute the RETI instruction, the S flag must be 0.

712


Delayed Branch Instructions

Table I.2-12 Delayed Branch Instructions


JMP:D @Ri E 9F-0 1 ---- Ri → PC

CALL:D label12 F D8 1 ---- PC+4 → RP ,PC+2+(label12-PC-2) → PC

CALL:D @Ri E 9F-1 1 ---- PC+4 → RP ,Ri → PC

RET:D E 9F-2 1 ---- RP → PC Return

BRA:D label9 D F0 1 ---- PC+2+(label9-PC-2) →PC

BNO:D label9 D F1 1 ---- No branch

BEQ:D label9 D F2 1 ---- if(Z==1) thenPC+2+(label9-PC-2) →PC

BNE:D label9 D F3 1 ---- s/Z==0

BC:D label9 D F4 1 ---- s/C==1

BNC:D label9 D F5 1 ---- s/C==0

BN:D label9 D F6 1 ---- s/N==1

BP:D label9 D F7 1 ---- s/N==0

BV:D label9 D F8 1 ---- s/V==1

BNV:D label9 D F9 1 ---- s/V==0

BLT:D label9 D FA 1 ---- s/V xor N==1

BGE:D label9 D FB 1 ---- s/V xor N==0

BLE:D label9 D FC 1 ---- s/(V xor N) or Z==1

BGT:D label9 D FD 1 ---- s/(V xor N) or Z==0

BLS:D label9 D FE 1 ---- s/C or Z==1

BHI:D label9 D FF 1 ---- s/C or Z==0

Notes:• In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them

as shown below:(label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8; label12 and label9 have a sign.

• A delayed branch always occurs after the next instruction (delay slot) is executed.• Instructions that can be placed in the delay slot are all 1-cycle, a-, b-, c-, and d-cycle instructions.

Multi-cycle instructions cannot be placed in the delay slot.

713


Other Instructions

Table I.2-13 Other Instructions


NOP E 9F-A 1 ---- No change

ANDCCR #u8 D 83 c CCCC CCR and u8 → CCR

ORCCR #u8 D 93 c CCCC CCR or u8 → CCR

STILM #u8 D 87 1 ---- i8 → ILM ILM immediate set

ADDSP #s10*1 D A3 1 ---- R15 += s10 ADD SP instruction

EXTSB Ri E 97-8 1 ---- Sign extension 8 → 32bit

EXTUB Ri E 97-9 1 ---- Zero extension 8 → 32bit

EXTSH Ri E 97-A 1 ---- Sign extension 16 → 32bit

EXTUH Ri E 97-B 1 ---- Zero extension 16 → 32bit

LDM0 (reglist) D 8C ---- (R15) → reglist,R15 increment

Load multi R0-R7

LDM1 (reglist) D 8D ---- (R15) → reglist,R15 increment

Load multi R8-R15

*LDM (reglist)*2 ---- (R15) → reglist,R15 increment

Load multi R0-R15

STM0 (reglist) D 8E ---- R15 decrement,reglist → (R15)

Store multi R0-R7

STM1 (reglist) D 8F ---- R15 decrement,reglist → (R15)

Store multi R8-R15

*STM (reglist)*3 ---- R15 decrement,reglist → (R15)

Store multi R0-R15

ENTER #u10*4 D 0F 1+a ---- R14 → (R15 - 4),R15 - 4 → R14,R15 - u10 → R15

Entry processing of a function

LEAVE E 9F-9 b ---- R14 + 4 → R15,(R15 - 4) → R14

Exit processing of a function

XCHB @Rj, Ri A 8A 2a ---- Ri → TEMP(Rj) → RiTEMP → (Rj)

For semaphore managementByte data

*1: For s10, the assembler calculates s10/4 and then changes to s8 to set a value. s10 has a sign.*2: If any of R0 to R7 is specified in reglist, LDM0 is generated. If any of R8 to R15 is generated, LDM1 is generated. In some cases,

both LDM0 and LDM1 are generated.*3: If any of R0 to R7 is specified in reglist, STM0 is generated. If any of R8 to R15 is generated, STM1 is generated. In some cases,

both STM0 and STM1 are generated.*4: For u10, the assembler calculates u10/4 and then changes to u8 to set a value. u10 has a sign.Note:• The number of execution cycles of LDM0(reglist) and LDM1(reglist) can be calculated as a*(n-1)+b+1 cycles if the number of

specified registers is n.• The number of execution cycles of STM0(reglist) and STM1(reglist) can be calculated as a*n+1 cycles if the number of specified

registers is n.

714


20-Bit Normal Branch Macro Instructions


Mnemonic Operation Remarks

*CALL20 label20,Ri Address of the next instruction → RP,label20 → PC

Ri: Temporary register (See Reference 1)

*BRA20 label20,Ri label20 → PC Ri: Temporary register (See Reference 2)

*BEQ20 label20,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3)

*BNE20 label20,Ri s/Z==0

*BC20 label20,Ri s/C==1

*BNC20 label20,Ri s/C==0

*BN20 label20,Ri s/N==1

*BP20 label20,Ri s/N==0

*BV20 label20,Ri s/V==1

*BNV20 label20,Ri s/V==0

*BLT20 label20,Ri s/V xor N==1

*BGE20 label20,Ri s/V xor N==0

*BLE20 label20,Ri s/(V xor N) or Z==1

*BGT20 label20,Ri s/(V xor N) or Z==0

*BLS20 label20,Ri s/C or Z==1

*BHI20 label20,Ri s/C or Z==0

[Reference 1] CALL201) If label20-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below:

CALL label122) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below:

LDI:20 #label20,RiCALL @Ri

[Reference 2] BRA201) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

BRA label92) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below:

LDI:20 #label20,RiJMP @Ri

[Reference 3] Bcc201) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

Bcc label92) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below:

Bxcc false xcc is the opposite condition of cc.LDI:20 #label20,RiJMP @Rifalse:

715


20-Bit Delayed Branch Macro Instructions



*CALL20:D label20,Ri Address of the next instruction → RP,label20 → PC


*BRA20:D label20,Ri label20 → PC Ri: Temporary register (See Reference 2)

*BEQ20:D label20,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3)

*BNE20:D label20,Ri s/Z==0

*BC20:D label20,Ri s/C==1

*BNC20:D label20,Ri s/C==0

*BN20:D label20,Ri s/N==1

*BP20:D label20,Ri s/N==0

*BV20:D label20,Ri s/V==1

*BNV20:D label20,Ri s/V==0

*BLT20:D label20,Ri s/V xor N==1

*BGE20:D label20,Ri s/V xor N==0

*BLE20:D label20,Ri s/(V xor N) or Z==1

*BGT20:D label20,Ri s/(V xor N) or Z==0

*BLS20:D label20,Ri s/C or Z==1

*BHI20:D label20,Ri s/C or Z==0

[Reference 1] CALL20:D1) If label20-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below:

CALL:D label122) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as

shown below:LDI:20 #label20,RiCALL:D @Ri


BRA :D label92) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as

shown below:LDI:20 #label20,RiJMP:D @Ri

[Reference 3] Bcc20:D1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

Bcc:D label92) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as

shown below:Bxcc false xcc is the opposite condition of cc.LDI:20 #label20,RiJMP:D @Rifalse:

716


32-Bit Normal Branch Macro Instructions



*CALL32 label32,Ri Address of the next instruction → RP,label20 → PC


*BRA32 label32,Ri label32 → PC Ri: Temporary register (See Reference 2)

*BEQ32 label32,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3)

*BNE32 label32,Ri s/Z==0

*BC32 label32,Ri s/C==1

*BNC32 label32,Ri s/C==0

*BN32 label32,Ri s/N==1

*BP32 label32,Ri s/N==0

*BV32 label32,Ri s/V==1

*BNV32 label32,Ri s/V==0

*BLT32 label32,Ri s/V xor N==1

*BGE32 label32,Ri s/V xor N==0

*BLE32 label32,Ri s/(V xor N) or Z==1

*BGT32 label32,Ri s/(V xor N) or Z==0

*BLS32 label32,Ri s/C or Z==1

*BHI32 label32,Ri s/C or Z==0

[Reference 1] CALL321) If label32-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below:

CALL label122) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction

as shown below:LDI:32 #label32,RiCALL @Ri


BRA label92) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction

as shown below:LDI:32 #label32,RiJMP @Ri

[Reference 3] Bcc321) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

Bcc label92) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction

as shown below:Bxcc false xcc is the opposite condition of cc.LDI:32 #label32,RiJMP @Ri32false:

717


32-Bit Delayed Branch Macro Instructions



*CALL32:D label32,Ri Address of the next instruction → RP,label20 → PC


*BRA32:D label32,Ri label32 → PC Ri: Temporary register (See Reference 2)

*BEQ32:D label32,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3)

*BNE32:D label32,Ri s/Z==0

*BC32:D label32,Ri s/C==1

*BNC32:D label32,Ri s/C==0

*BN32:D label32,Ri s/N==1

*BP32:D label32,Ri s/N==0

*BV32:D label32,Ri s/V==1

*BNV32:D label32,Ri s/V==0

*BLT32:D label32,Ri s/V xor N==1

*BGE32:D label32,Ri s/V xor N==0

*BLE32:D label32,Ri s/(V xor N) or Z==1

*BGT32:D label32,Ri s/(V xor N) or Z==0

*BLS32:D label32,Ri s/C or Z==1

*BHI32:D label32,Ri s/C or Z==0

[Reference 1] CALL32:D1) If label32-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below:

CALL:D label122) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as

shown below:LDI:32 #label32,RiCALL:D @Ri

[Reference 2] BRA32:D1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

BRA:D label92) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as

shown below:LDI:32 #label32,RiJMP:D @Ri

[Reference 3] Bcc32:D1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

Bcc:D label92) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as

shown below:Bxcc false xcc is the opposite condition of cc.LDI:32 #label32,RiJMP:D @Ri32false:

718


Direct Addressing Instructions

Resource Instructions

Table I.2-18 Direct Addressing Instructions


DMOV @dir10, R13 D 08 b ---- (dir10) → R13 Word

DMOV R13, @dir10 D 18 a ---- R13 → (dir10) Word

DMOV @dir10, @R13+ D 0C 2a ---- (dir10) → (R13),R13+=4 Word

DMOV @R13+, @dir10* D 1C 2a ---- (R13) → (dir10),R13+=4 Word

DMOV @dir10, @-R15 D 0B 2a ---- R15-=4,(R15) → (dir10) Word

DMOV @R15+, @dir10 D 1B 2a ---- (R15) → (dir10),R15+=4 Word

DMOVH @dir9, R13 D 09 b ---- (dir9) → R13 Halfword

DMOVH R13, @dir9 D 19 a ---- R13 → (dir9) Halfword

DMOVH @dir9, @R13+ D 0D 2a ---- (dir9) → (R13),R13+=2 Halfword

DMOVH @R13+, @dir9* D 1D 2a ---- (R13) → (dir9),R13+=2 Halfword

DMOVB @dir8, R13 D 0A b ---- (dir8) → R13 Byte

DMOVB R13, @dir8 D 1A a ---- R13 → (dir8) Byte

DMOVB @dir8, @R13+ D 0E 2a ---- (dir8) → (R13),R13++ Byte

DMOVB @R13+, @dir8* D 1E 2a ---- (R13) → (dir8),R13++ Byte

Note:In the dir8, dir9, and dir10 fields, the assembler calculates values and sets them as shown below:

dir8 → dir, dir9/2 → dir, dir10/4 → dir; dir8, dir9, and dir10 have no sign.

Table I.2-19 Resource Instructions


LDRES @Ri+, #u4 C BC a ---- (Ri) → u4 resourceRi+=4

u4: Channel number

STRES #u4, @Ri+ C BD a ---- u4 resource → (Ri)Ri+=4

u4: Channel number

Note:This instruction cannot be used for the MB91319 because it has no resource with a channel number.

719


Coprocessor Control Instructions

Table I.2-20 Coprocessor Control Instructions


COPOP #u4, #u8, CRj, CRi E 9F-C 2+a ---- Operation instruction

COPLD #u4, #u8, Rj, CRi E 9F-D 1+2a ---- Rj → CRi

COPST #u4, #u8, CRj, Ri E 9F-E 1+2a ---- CRj → Ri

COPSV #u4, #u8, CRj, Ri E 9F-F 1+2a ---- CRj → Ri No error trap

Notes:• CRi | CRj:= CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 |

CR13 |CR14 | CR15u4:= Channel specifiedu8:= Channel specified

• The instructions can not be used on MB91319 series, because MB91319 series have no coprocessor.

720

INDEX

The index follows on the next page.This is listed in alphabetic order.

721

Index

Numerics

0 Detection0 Detection........................................................235

0 Detection Data Register0 Detection Data Register (BSD0) ..........................232

1 Detection1 Detection........................................................235

1 Detection Data Register1 Detection Data Register (BSD1) ..........................233

10-Bit A/D ConverterFeatures of the 10-Bit A/D Converter ......................240Registers of the 10-Bit A/D Converter .....................241

10-bit Slave Address Mask Register10-bit Slave Address Mask Register (ITMK) .............301

10-bit Slave Address Register10-bit Slave Address Register (ITBA)......................300

16-bit/32-bit Immediate Transfer InstructionsImmediate Set/16-bit/32-bit Immediate Transfer

Instructions...........................................70916-Bit Pulse Width Counter

16-Bit Pulse Width Counter...................................190Registers of the 16-Bit Pulse Width Counter .............191

16-bit Reload RegisterBit Configuration of the 16-bit Reload Register (TMRLR)

..........................................................14416-bit Reload Timer

16-bit Reload Timer Registers................................139Overview of the 16-bit Reload Timer.......................138Precautions on Using the 16-bit Reload Timer ...........150

16-bit Timer RegisterBit Configuration of the 16-bit Timer Register (TMR)

..........................................................14316-Bit Width Pulse Counter

Basic Operation of the 16-Bit Width Pulse Counter.....19920-Bit Delayed Branch Macro Instructions

20-Bit Delayed Branch Macro Instructions ...............71620-Bit Normal Branch Macro Instructions

20-Bit Normal Branch Macro Instructions ................7152-Cycle Transfer

Burst 2-Cycle Transfer .........................................346Demand Transfer 2-Cycle Transfer .........................347Flow of Data During 2-Cycle Transfer .....................373Step/Block Transfer 2-Cycle Transfer ......................349Step/Block Transfer 2-Cycle Transfer Fly-by Transfer

..........................................................35032-Bit Delayed Branch Macro Instructions

32-Bit Delayed Branch Macro Instructions ...............71832-bit Immediate Transfer Instructions

Immediate Set/16-bit/32-bit Immediate Transfer Instructions...........................................709

32-Bit Normal Branch Macro Instructions32-Bit Normal Branch Macro Instructions ................ 717

7-bit Slave Address Mask Register7-bit Slave Address Mask Register (ISMK) .............. 304

7-bit Slave Address Register7-bit Slave Address Register (ISBA) ....................... 303

722

A

A/D ConversionA/D Conversion Started by External Trigger ............. 247A/D Conversion Started by Software....................... 247

A/D Conversion Result RegisterA/D Conversion Result Register (Channels 0 to 9) ..... 245

A/D ConverterA/D Converter ....................................................... 4Features of the 10-Bit A/D Converter ...................... 240Registers of the 10-Bit A/D Converter ..................... 241

A/D Converter Test RegisterA/D Converter Test Register ................................. 246

A/DC Control RegisterA/DC Control Register (ADCTH, ADCTL) .............. 242

AC CharacteristicsAC Characteristics of DMAC ................................ 369

AccessData Access ........................................................ 44Program Access ................................................... 44

AcknowledgeAcknowledge..................................................... 312

ADCTHA/DC Control Register (ADCTH, ADCTL) .............. 242

ADCTLA/DC Control Register (ADCTH, ADCTL) .............. 242

Add-Subtract InstructionsAdd-Subtract Instructions ..................................... 705

Address RegisterAddress Register Specifications ............................. 353Features of the Address Register ............................ 353Function of the Address Register............................ 353

Address Setting RegistersTransfer Source/Transfer Destination Address Setting

Registers (DMASA0 to 4/DMADA0 to 4).......................................................... 336

Addressing ModeAddressing Mode Symbols ................................... 701

AF110System Configuration of AF220/AF210/AF120/AF110

Flash Micro-controller Programmer ........... 667AF120

System Configuration of AF220/AF210/AF120/AF110 Flash Micro-controller Programmer ........... 667

AF210System Configuration of AF220/AF210/AF120/AF110

Flash Micro-controller Programmer ........... 667AF220

System Configuration of AF220/AF210/AF120/AF110 Flash Micro-controller Programmer ........... 667

All-Channel Control RegisterAll-Channel Control Register (DMACR) ................. 338

ArbitrationArbitration ........................................................ 312

ArchitectureInternal Architecture ............................................. 32

Automatic AlgorithmAutomatic Algorithm Execution Status.....................643

Automatic ResponseAutomatic Response of Macro Program to USB Standard

Request Commands ................................442

B

BackgroundCharacter Background Color

(Setting for Each Screen, Selected from Among 16 Colors) ................................................515

Character Background Control (Setting for Each Character)..........................................................515

Character Background Extended Display (Setting for Each Line) ............................521

Command 6-1 (Shaded Background Frame Color Control)..........................................................581

Command 7-1 (Screen Background Character Control 1)..........................................................585

Command 7-3 (Screen Background Character Control 2)..........................................................586

Configuration of Screen Background Character Display..........................................................534

Display Position Control of Screen Background Characters..........................................................469

Display Position Control of Screen Background Color..........................................................470

Line Background Color (Setting for Each Line, Selected From Among 16 Colors) ................................................524

Line Background Control (Setting for Each Line) .......524Screen Background Character Display Control...........535Screen Background Color Control ...........................537Screen Background Display ...................................533Screen Background Output Control .........................537Shaded Background Highlight Color

(Setting for Each Screen, Selected from Among 16 Colors) ........................................515, 524

Shaded Background Shadow Color (Setting for Each Screen, Selected from Among 16 Colors) ........................................515, 524

Shaded Background Succeeding Character Merge Control (Setting for Each Character)......................517

Shaded Background Succeeding Line Merge Control (Setting for Each Line) ....................519, 526

Base Clock Division Setting RegisterBase Clock Division Setting Register 0 (DIVR0) ..........95Base Clock Division Setting Register 1 (DIVR1) ..........96

Basic Block DiagramBasic Block Diagram of the I/O Port........................128

Basic ConfigurationBasic Configuration of FR MB91FV319A Serial

Programming Connection.........................664Basic Programming Model

Basic Programming Model ......................................36Baud Rate

Calculation of Baud Rate ......................................254Example of Setting U-TIMER Baud Rates and Reload

Values .................................................279

723

BFOKSetting of Transfer Enable (BFOK) Bits during Control

Transfer ...............................................448Bit Configuration

Bit Configuration of the 16-bit Reload Register (TMRLR)..........................................................144

Bit Configuration of the 16-bit Timer Register (TMR)..........................................................143

Bit Configuration of the Control Status Register (TMCSR)..........................................................140

Bit FunctionsBit Functions of the Control Status Register (TMCSR)

..........................................................140Bit Manipulation Instructions

Bit Manipulation Instructions.................................707Bit Ordering

Bit Ordering ........................................................43Bit Search Module

Bit Search Module (Used by REALOS) .......................3Bit Search Module Registers..................................232Block Diagram of the Bit Search Module .................231

BlinkBlink Control (Setting for Each Character)................507Blink Cycle .......................................................510Blink Duty Ratio.................................................510

Block DiagramBasic Block Diagram of the I/O Port .......................128Block Diagram

.......7, 83, 115, 121, 138, 170, 190, 205, 240, 250, 257, 286, 321, 380, 457, 631

Block Diagram for One Channel of PPG Timer..........154Block Diagram of the Bit Search Module .................231Block Diagram of the Delayed Interrupt Module ........228Block Diagram of the External Interrupt and NMI Controller

..........................................................218Overall Block Diagram of PPG Timer .....................153

Block SizeBlock Size.........................................................351

Block TransferBlock Transfer ...................................................370If Another Transfer Request Occurs During Block Transfer

..........................................................369Block/Step Transfer

Read and Write Timing Diagrams for DMA Block/Step Transfer ........................................421

Branch InstructionBranch Instruction with Delay Slot............................46Branch Instruction without Delay Slot .......................48

Branch Macro Instructions20-Bit Delayed Branch Macro Instructions ...............71632-Bit Delayed Branch Macro Instructions ...............71832-Bit Normal Branch Macro Instructions ................717

BSD0 Detection Data Register (BSD0) ..........................2321 Detection Data Register (BSD1) ..........................233

BSDCChange Point Detection Data Register (BSDC) ..........233

BSRRDetection Result Register (BSRR) .......................... 234

Built-in Peripheral RequestBuilt-in Peripheral Request ................................... 344

Built-in RAMBuilt-in RAM ........................................................ 3

BULK IN TransferTiming Diagram for BULK IN Transfer

(Writing by CPU and Reading by USB) ...... 436BULK OUT Transfer

Control Transfer (Data Stage) and BULK OUT Transfer......................................................... 413

Timing Diagram for BULK OUT Transfer (Reading by CPU and Writing by USB) ...... 438

Bulk TransferControl Transfer (Data Stage), Bulk Transfer, or

INTERRUPT IN Transfer........................ 414Burst 2-Cycle Transfer

Burst 2-Cycle Transfer......................................... 346Burst Fly-by Transfer

Burst Fly-by Transfer .......................................... 347Burst Transfer

Burst Transfer.................................................... 371Bus Control Register

Bus Control Register (IBCR)................................. 292Bus Error

Bus Error.......................................................... 313Bus Interface

Bus Interface ......................................................... 2Bus Modes

Bus Modes.......................................................... 64Bus Reset

Macro Program Status after USB Bus Reset.............. 451Bus Status Register

Bus Status Register (IBSR) ................................... 289BUSYX

Ready/Busy Signal (RDY/BUSYX) ........................ 648Byte Ordering

Byte Ordering ...................................................... 43

C

Capture Control RegisterCapture Control Register (TxCCR) ......................... 174

Capture Data RegisterCapture Data Register (TxCRR)............................. 180

Capture ModeCapture Mode ............................................ 183, 186

CC ScreenDisplay Position Control on the Main/CC Screen ....... 465

Change Point DetectionChange Point Detection........................................ 236

Change Point Detection Data RegisterChange Point Detection Data Register (BSDC).......... 233

Channel GroupChannel Group................................................... 364

724

CharacterBlink Control (Setting for Each Character) ............... 507Character Background Control (Setting for Each Character)

.......................................................... 515Character Horizontal Size Control

(Setting for Each Character) ..................... 481Character Vertical Size A/B .................................. 482Character/graphic Character Control

(Setting for Each Character) ..................... 502Command 1 (Character Data Set 1)......................... 573Command 1 (Character Data Setting1)..................... 612Command 2 (Character Data Set 2)......................... 574Command 2 (Character Data Setting2)..................... 613Command 6-0 (Character Vertical Size Control) ........ 580Command 7-1 (Screen Background Character Control 1)

.......................................................... 585Command 7-3 (Screen Background Character Control 2)

.......................................................... 586Command 8-1 (Sprite Character Control 1)............... 587Command 9-0 (Sprite Character Control 3)............... 588Command 9-1 (Sprite Character Control 4)............... 589Configuration of Screen Background Character Display

.......................................................... 534Display Position Control of Screen Background Characters

.......................................................... 469Display Position Control of Sprite Characters............ 471Line Character Vertical Size Type Control

(Setting for Each Line)............................ 481Origin of Italic Character...................................... 488Screen Background Character Display Control .......... 535Shaded Background Succeeding Character Merge Control

(Setting for Each Character) ..................... 517Sprite Character Configuration .............................. 538Sprite Character Display Control ............................ 538Writing a Single Character to Character RAM ........... 477Writing Multiple Characters Collectively (VRAM Fill)

.......................................................... 478Character Background

Character Background Color (Setting for Each Screen, Selected from Among 16 Colors) ................................................ 515

Character Background Control (Setting for Each Character).......................................................... 515

Character Background Extended Display (Setting for Each Line)............................ 521

Character ColorCharacter Colors

(Setting for Each Character, Selected from among 16 Colors) ............................................ 485

Color to be Replaced by the Character Color (Setting for Each Screen)......................... 506

Graphic Color/Character Color Replace Control (Setting for Each Screen)......................... 505

Character RAMWriting a Single Character to Character RAM ........... 477

Character Vertical SizeCommand 6-0 (Character Vertical Size Control)

.................................................. 580, 619Chip Erasure

Data Erasure (Chip Erasure).................................. 657

CircuitInput-Output Circuit Types......................................17Quartz Oscillation Circuit........................................24

ClassSetup Stage of Control Transfer

(Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame]) ......................................411

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame]) ......................................412

CLKBCPU Clock (CLKB)...............................................80

CLKPPeripheral Clock (CLKP) ........................................81

CLKRClock Source Control Register (CLKR)......................92

CLKTExternal Bus Clock (CLKT) ....................................81

ClockClock Division .....................................................82Clock Generation Control........................................75Clocks ................................................................25Command 18-0 (PLLA Clock Control 1-1)................601Command 18-1 (PLLA Clock Control 1-2)................601Command 18-10 (PLLC Clock Control 2).................605Command 18-11 (PLLC Clock Control 3).................606Command 18-12 (Clock Selection Control 1).............607Command 18-2 (PLLA Clock Control 2) ..................602Command 18-3 (Clock Selection Control 2) ..............608Command 18-3 (PLLA Clock Control 3) ..................602Command 18-4 (PLLB Clock Control 1-1)................603Command 18-5 (PLLB Clock Control 1-2)................603Command 18-6 (PLLB Clock Control 2) ..................604Command 18-7 (PLLB Clock Control 3) ..................604Command 18-8 (PLLC Clock Control 1-1)................605Command 18-9 (PLLC Clock Control 1-2)................605Count Clock Selection ..........................................200CPU Clock (CLKB)...............................................80Dot Clock..........................................................689Dot Clock Generation PLL ....................................688Example of USB Clock Control in the Suspended Status

..........................................................445External Bus Clock (CLKT) ....................................81External Dot Clock Input ......................................543Input Dot Clock Selection Control...........................543Internal VCO Generation Dot Clock Input ................544Main Clock Oscillation Stabilization Wait Timer ........120Main Clock Oscillation Stabilization Wait Timer Control

Register ...............................................122Main Clock Oscillation Stabilization Wait Timer Interrupt

..........................................................123Operation of Clock Supply Function ........................118Operation of the Main Clock Oscillation Stabilization Wait

Timer ..................................................125Oscillation Clock Frequency ..................................667Output Dot Clock Control .....................................547Peripheral Clock (CLKP) ........................................81

725

Precautions on Using the Main Clock Oscillation Stabilization Wait Timer..........................125

Selecting a Clock for the UART .............................270Selection of Source Clock .......................................75USB Clock ........................................................690Video Clock PLL....................................................5

Clock Control RegisterClock Control Register (ICCR) ..............................298

Clock Disable RegisterIDBL (Clock Disable Register) ..............................306

Clock DivisionClock Division .....................................................82

Clock GenerationDot Clock Generation PLL....................................688

Clock Generation ControlClock Generation Control .......................................75

Clock Source Control RegisterClock Source Control Register (CLKR) .....................92

Clock SupplyOperation of Clock Supply Function................118, 124

Closed Caption DecoderClosed Caption Decoder Function...............................5

ColorCharacter Background Color

(Setting for Each Screen, Selected from Among 16 Colors) ................................................515

Character Colors (Setting for Each Character, Selected from among 16 Colors) ............................................485

Code of the Color to be Replaced by the Trimming Color (Setting for Each Screen) .........................504

Color to be Replaced by the Character Color (Setting for Each Screen) .........................506

Command 6-1 (Shaded Background Frame Color Control)..........................................................581

Command 6-2 (Transparent/Translucent Color Control)..........................................................582

Command 6-3 (Graphic Color Control) ....................583Graphic Color/Character Color Replace Control

(Setting for Each Screen) .........................505Graphic Color/Trimming Color Replace Control

(Setting for Each Screen) .........................504Line Background Color

(Setting for Each Line, Selected From Among 16 Colors) ................................................524

Screen Background Color Control...........................537Shaded Background Highlight Color



Translucent Color Control (Setting for Each Screen)..........................................................513

Transparent Color Control (Setting for Each Screen)..........................................................511

Trimming Colors ................................................497Command

Command 0 (VRAM Write Address Set)..................572

Command 0 (VRAM Write Address Setting) ............ 611Command 1 (Character Data Set 1)......................... 573Command 1 (Character Data Setting1) .................... 612Command 11-0 (Synchronization Control) ............... 590Command 13-0 (I/O Pin Control) ........................... 591Command 13-1 (I/O Pin Control 2)......................... 592Command 14-0 (Display Period Control 1)....... 593, 621Command 14-1 (Display Period Control 2)....... 594, 621Command 14-2 (Display Period Control 3)....... 594, 621Command 14-3 (Display Period Control 4)....... 595, 622Command 15-0 (Interrupt Control) ......................... 596Command 15-0 (Interruption Control) ..................... 623Command 16-0 to Command 16-15 (Palette Control)

......................................................... 624Command 17-0 (OSDC Operation Control 1)............ 599Command 17-1 (OSDC Operation Control 2)............ 600Command 18-0 (PLLA Clock Control 1-1)............... 601Command 18-1 (PLLA Clock Control 1-2)............... 601Command 18-10 (PLLC Clock Control 2) ................ 605Command 18-11 (PLLC Clock Control 3) ................ 606Command 18-12 (Clock Selection Control 1) ............ 607Command 18-2 (PLLA Clock Control 2).................. 602Command 18-3 (Clock Selection Control 2).............. 608Command 18-3 (PLLA Clock Control 3).................. 602Command 18-4 (PLLB Clock Control 1-1) ............... 603Command 18-5 (PLLB Clock Control 1-2) ............... 603Command 18-6 (PLLB Clock Control 2).................. 604Command 18-7 (PLLB Clock Control 3).................. 604Command 18-8 (PLLC Clock Control 1-1) ............... 605Command 18-9 (PLLC Clock Control 1-2) ............... 605Command 2 (Character Data Set 2)......................... 574Command 2 (Character Data Setting 2).................... 613Command 3 (Line Control Data Set 1)..................... 575Command 3 (Line Control Data Setting 1)................ 614Command 4 (Line Control Data Set 2)..................... 576Command 4 (Line Control Data Setting 2)................ 615Command 5-00 (Display Output Control 1) .............. 616Command 5-00 (Screen Output Control 1)................ 577Command 5-1 (Display Output Control 2) ................ 617Command 5-1 (Screen Output Control 2) ................. 578Command 5-2 (Vertical Display Position Control)

................................................. 579, 618Command 5-3 (Horizontal Display Position Control)

................................................. 579, 618Command 6-0 (Character Vertical Size Control)

................................................. 580, 619Command 6-1 (Shaded Background Frame Color Control)

......................................................... 581Command 6-2 (Transparent/Translucent Color Control)

......................................................... 582Command 6-2 (TransparentColorControl) ................ 620Command 6-3 (Graphic Color Control).................... 583Command 7-1 (Screen Background Character Control 1)

......................................................... 585Command 7-3 (Screen Background Character Control 2)

......................................................... 586Command 8-1 (Sprite Character Control 1)............... 587Command 8-2 (Sprite Character Control 2)............... 588Command 9-0 (Sprite Character Control 3)............... 588Command 9-1 (Sprite Character Control 4)............... 589Command Sequence............................................ 644Commands 16-0 to 16-15 (Palette Control) ............... 597

726

Display Control Command ................................... 609Display Control Command List.............................. 610List of Display Control Commands ......................... 570Setup Stage of Control Transfer

(Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame]) ..................................... 411

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame]) ..................................... 412

Command SequenceCommand Sequence ............................................ 644

CommunicationCommunication Error that Causes No Error .............. 313End of Communication ........................................ 273Start of Communication ....................................... 273

Compare InstructionsCompare Instructions........................................... 705

Connection DiagramConnection Diagram ........................................... 625

CONTCONT1 ............................................................ 394CONT10 .......................................................... 405CONT2 ............................................................ 396CONT3 ............................................................ 398CONT4 ............................................................ 399CONT5 ............................................................ 400CONT6 ............................................................ 401CONT7 ............................................................ 402CONT8 ............................................................ 403CONT9 ............................................................ 404

Control Status RegisterBit Configuration of the Control Status Register (TMCSR)

.......................................................... 140Bit Functions of the Control Status Register (TMCSR)

.......................................................... 140Control/Status Register B (DMACB0 to 4) ............... 329Register Configurations of Control Status Registers

(PCNH and PCNL) ................................ 156Control/Status Registers A (DMACA0 to 4) ............. 324

CoprocessorCoprocessor Error Trap.......................................... 63No-coprocessor Trap ............................................. 63

Coprocessor Control InstructionsCoprocessor Control Instructions............................ 720

CorrectionField Correction Control....................................... 555

CPUCPU Clock (CLKB) .............................................. 80Example of Controlling Reception at CPU Access...... 427Example of Controlling Transmission at CPU Access

.......................................................... 429FR CPU ............................................................... 2Timing Diagram for BULK IN Transfer

(Writing by CPU and Reading by USB) ...... 436Timing Diagram for BULK OUT Transfer

(Reading by CPU and Writing by USB) ...... 438

CPU IN TransferCPU IN Transfer .................................................416

CPU ModeConfiguration of Flash Control/Status Register (FLCR)

(CPU Mode) .........................................638CPU OUT Transfer

CPU OUT Transfer..............................................418CTBR

Time Base Counter Clear Register (CTBR) .................91

D

D+ Terminating ResisterControlling the D+ Terminating Resister on the Board

..........................................................441DACK

Pin Function of the DACK, and DEOP, and DREQ Pins..........................................................340

Timing of DACK Pin Output .................................368Data Access

Data Access .........................................................44Data Direction Registers

Configuration of the Data Direction Registers (DDR)..........................................................131

Data LengthData Length (Data Width) .....................................354

Data RegisterData Register (IDAR)...........................................305

Data StageControl Transfer (Data Stage) and BULK OUT Transfer

..........................................................413Control Transfer (Data Stage), Bulk Transfer, or

INTERRUPT IN Transfer ........................414Data Width

Data Length (Data Width) .....................................354DDR

Configuration of the Data Direction Registers (DDR)..........................................................131

Default StatusUSB Function Macro Program Operation in the Default

Status ..................................................444Delay

Normal Branch (No Delay) Instructions....................712Delay Slot

Branch Instruction with Delay Slot ............................46Branch Instruction without Delay Slot........................48Precaution on Delay Slot.........................................63

Delayed Branch InstructionsDelayed Branch Instructions ..................................713

Delayed Branch Macro Instructions20-Bit Delayed Branch Macro Instructions ................71632-Bit Delayed Branch Macro Instructions ................718

Delayed Interrupt Control RegisterDelayed Interrupt Control Register

(DICR: Delayed Interrupt Control Register)..........................................................229

727

Delayed Interrupt ModuleBlock Diagram of the Delayed Interrupt Module ........228Delayed Interrupt Module Registers ........................229

Demand TransferDemand Transfer ................................................372Demand Transfer 2-Cycle Transfer .........................347Demand Transfer Fly-by Transfer ...........................348Read and Write Timing Diagrams for DMA Demand

Transfer ...............................................422Timing to Stop a Demand Transfer Request and Timing to

Invalidate the DREQ Pin Input..................365DEOP

Pin Function of the DACK, and DEOP, and DREQ Pins..........................................................340

Timing of the DEOP Pin Output.............................368Detection

0 Detection........................................................2351 Detection........................................................235Change Point Detection ........................................236Detection of USB Connector Connection and Disconnection

..........................................................446Examples of Vertical Synchronization Detection Operation

..........................................................550Field Detection Control ........................................553Slave Address Detection .......................................311Vertical Synchronization Detection .........................549

Detection Result RegisterDetection Result Register (BSRR) ..........................234

Device InitializationReset (Device Initialization) ....................................67

Device State ControlDevice State Control............................................104

Device StatesTransition of Device States ...................................105

DICRDelayed Interrupt Control Register

(DICR: Delayed Interrupt Control Register)..........................................................229

DLYI Bit of DICR ..............................................230Dimensions

Dimensions of the MB91319 .....................................8Direct Addressing Instructions

Direct Addressing Instructions ...............................719Display Control Command

Display Control Command....................................609Display Control Command List ..............................610List of Display Control Commands .........................570

Display ExampleApplied Display Examples ....................................484Display Example ........................487, 489, 493, 561Display Examples

..........482, 516, 518, 520, 522, 525, 527Display Format

Display Format...................................................507Display Memory

Display Memory and Display Screen .......................476Writing to Display Memory...................................477

Display Output ControlCommand 5-00 (Display Output Control 1) .............. 616Command 5-1 (Display Output Control 2) ................ 617

Display PeriodCommand 14-0 (Display Period Control 1)....... 593, 621Command 14-1 (Display Period Control 2)....... 594, 621Command 14-2 (Display Period Control 3)....... 594, 621Command 14-3 (Display Period Control 4)....... 595, 622Horizontal Display Period Control.......................... 560Vertical Display Period Control ............................. 559

Display PositionCommand 5-2 (Vertical Display Position Control)

................................................. 579, 618Command 5-3 (Horizontal Display Position Control)

................................................. 579, 618Display Position Control

Display Position Control of Screen Background Characters......................................................... 469

Display Position Control of Screen Background Color......................................................... 470

Display Position Control of Sprite Characters............ 471Display Position Control on the Main/CC Screen ....... 465

Display Position OffsetScreen Display Position Offset .............................. 473

Display ScreenDisplay Memory and Display Screen ...................... 476

Display SignalDisplay Signal Output Timing ............................... 556Example of Display Signal Output (1) ..................... 556Example of Display Signal Output (2) ..................... 558

DIVRBase Clock Division Setting Register 0 (DIVR0) ......... 95Base Clock Division Setting Register 1 (DIVR1) ......... 96

DLYI BitDLYI Bit of DICR .............................................. 230

DMAClearing Peripheral Interrupts by DMA ................... 359Example of Controlling DMA Reception ................. 432Example of Controlling DMA Transmission ............. 433Read and Write Timing Diagrams for DMA Block/

Step Transfer ........................................ 421Read and Write Timing Diagrams for DMA Demand

Transfer............................................... 422Suppressing DMA .............................................. 356

DMA ControllerDMA Controller (DMAC) Registers ....................... 322DMAC (DMA Controller) ........................................ 3

DMA IN TransferDMA IN Transfer ............................................... 419

DMA OUT TransferDMA OUT Transfer............................................ 420

DMA ReceptionExample of Controlling DMA Reception ................. 432

DMA TransferDMA Transfer and Interrupts ................................ 356DMA Transfer during Sleep .................................. 362DMA Transfer Request during External Hold............ 357External Hold Request During DMA Transfer ........... 357

728

Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request ........................ 357

DMA TransmissionExample of Controlling DMA Transmission ............. 433

DMACAC Characteristics of DMAC ................................ 369DMA Controller (DMAC) Registers ....................... 322DMAC (DMA Controller) ........................................ 3DMAC Interrupt Control ...................................... 362

DMACAControl/Status Registers A (DMACA0 to 4) ............. 324

DMACBControl/Status Register B (DMACB0 to 4) ............... 329

DMACRAll-Channel Control Register (DMACR) ................. 338

DMADATransfer Source/Transfer Destination Address Setting


DMASATransfer Source/Transfer Destination Address Setting


Dot ClockDot Clock ......................................................... 689External Dot Clock Input...................................... 543Input Dot Clock Selection Control .......................... 543Internal VCO Generation Dot Clock Input ................ 544Output Dot Clock Control..................................... 547

Dot Clock GenerationDot Clock Generation PLL ................................... 688

Double BufferDouble Buffer.................................................... 436

DREQMinimum Effective Pulse Width of the DREQ Pin Input

.......................................................... 365Pin Function of the DACK, and DEOP, and DREQ Pins

.......................................................... 340Timing of the DREQ Pin Input for Continuing Transfer Over

the Same Channel .................................. 368Timing to Stop a Demand Transfer Request and Timing to

Invalidate the DREQ Pin Input ................. 365DSTP

Timing of the DSTP Pin Input ............................... 368

E

EIRRExternal Interrupt Source Register (EIRR)................ 221

EITEIT (Exception, Interrupt, and Trap) ......................... 49EIT Causes.......................................................... 49EIT Operations .................................................... 60EIT Vector Table.................................................. 54Priority of EIT Causes To Be Accepted ..................... 58Return from EIT ................................................... 49

ELVRExternal Interrupt Request Level Setting Register (ELVR)

..........................................................222End Point Buffer

Setting of End Point Buffer....................................424ENIR

Interrupt Enable Register (ENIR) ............................220Enter Timer Control Register

Enter Timer Control Register (TxR) ........................178Erase

Sector Erase Restart .............................................661Temporary Sector Erase Stop .................................660Writing/Erase .....................................................653

ErasureData Erasure (Chip Erasure) ..................................657Sector Erasure ....................................................658

ErrorBus Error ..........................................................313Communication Error that Causes No Error...............313Coprocessor Error Trap ..........................................63Stopping Due To an Error .....................................360

Event Count ModeEvent Count Mode.......................................182, 185

ExceptionEIT (Exception, Interrupt, and Trap) ..........................49

Extended DisplayCharacter Background Extended Display

(Setting for Each Line) ............................521External Bus Clock

External Bus Clock (CLKT) ....................................81External Bus Interface

External Bus Interface Setting ................................693External Dot Clock

External Dot Clock Input ......................................543External Event Count Operation

External Event Count Operation .............................148External Hold

DMA Transfer Request during External Hold ............357External Hold Request During DMA Transfer............357Simultaneous Occurrence of a DMA Transfer Request and

an External Hold Request .........................357External I/O

Transfer Between External I/O and External Memory..........................................................369

External InterruptBlock Diagram of the External Interrupt and NMI Controller

..........................................................218External Interrupt Request Level.............................224Operating Procedure for an External Interrupt ............223Operation of an External Interrupt ...........................223

External Interrupt and NMI ControllerExternal Interrupt and NMI Controller Registers.........219

External Interrupt Request Level Setting RegisterExternal Interrupt Request Level Setting Register (ELVR)

..........................................................222External Interrupt Source Register

External Interrupt Source Register (EIRR) ................221

729

External MemoryTransfer Between External I/O and External Memory

..........................................................369External Transfer Request Pin

External Transfer Request Pin................................344External Trigger

A/D Conversion Started by External Trigger .............247

F

FENWhen FIFO is not Used (FEN=0) ...........................315When FIFO is Used (FEN=0) ................................317

Field CorrectionField Correction Control .......................................555

Field DetectionField Detection Control ........................................553

FIFOFIFO Operational Overview ..................................283FIFO0i .............................................................384FIFO0o.............................................................384FIFO1 ..............................................................385FIFO2 ..............................................................385FIFO3 ..............................................................386When FIFO is not Used (FEN=0) ...........................315When FIFO is Used (FEN=0) ................................317

FIFO Control RegisterIFCR (FIFO Control Register) ...............................307

FIFO Data Count RegisterIFN (FIFO Data Count Register) ............................306

FIFO Data RegisterIFDR (FIFO Data Register) ...................................307

FIFO Reception Count RegisterIFRN (FIFO Reception Count Register) ...................309

FilterLow-Pass Filter ..................................................187

FlagHardware Sequence Flag ......................................648I Flag .................................................................50Interrupt Factor Flags...........................................564Occurrence of Interrupts and Timing for Setting Flags

..........................................................274Flash Control/Status Register

Configuration of Flash Control/Status Register (FLCR) (CPU Mode) .........................................638

Flash MemoryList of Flash Memory Registers..............................637Outline of Flash Memory ......................................630

Flash Micro-controller ProgrammerSystem Configuration of AF220/AF210/AF120/AF110

Flash Micro-controller Programmer ...........667FLCR

Configuration of Flash Control/Status Register (FLCR) (CPU Mode) .........................................638

Fly-by TransferBurst Fly-by Transfer...........................................347Demand Transfer Fly-by Transfer ...........................348

Flow of Data During Fly-By Transfer...................... 375Step/Block Transfer 2-Cycle Transfer Fly-by Transfer

......................................................... 350Font Memory

Font Memory Configuration.................................. 475FONT RAM

FONT RAM Memory Map ................................... 626FR

Basic Configuration of FR MB91FV319A Serial Programming Connection ........................ 664

FR CPUFR CPU ............................................................... 2

FR FamilyFR Family Instruction Lists................................... 704

Frame ColorCommand 6-1 (Shaded Background Frame Color Control)

......................................................... 581FR-CPU Programming Mode

FR-CPU Programming Mode (16 Bits, Read/Write)......................................................... 642

FR-CPU ROM ModeFR-CPU ROM Mode (32 Bits, Read Only)............... 642

Fujitsu Standard Serial Onboard WritingPins Used for Fujitsu Standard Serial Onboard Writing

......................................................... 665

G

GenerationDot Clock Generation PLL ................................... 688

Graphic CharacterCharacter/graphic Character Control

(Setting for Each Character) ..................... 502Graphic Color

Command 6-3 (Graphic Color Control).................... 583Graphic Color/Character Color Replace Control

(Setting for Each Screen)......................... 505Graphic Color/Trimming Color Replace Control

(Setting for Each Screen)......................... 504

H

Hardware Sequence FlagHardware Sequence Flag ...................................... 648

Highlight ColorShaded Background Highlight Color

(Setting for Each Screen, Selected from Among 16 Colors)........................................ 515, 524

Hold Request Cancellation RequestHold Request Cancellation Request

(HRLC: Hold Request Cancel Request) ...... 212Hold Request Cancellation Request Sequence ........... 215

Hold Request Cancellation Request Level Setting Register

Hold Request Cancellation Request Level Setting Register (HRCL)............................................... 210

Horizontal Display PeriodHorizontal Display Period Control.......................... 560

730

Horizontal Display PositionCommand 5-3 (Horizontal Display Position Control)

.................................................. 579, 618Horizontal Size

Character Horizontal Size Control (Setting for Each Character) ............................................ 481

Horizontal SynchronousExample of Horizontal Synchronous Operation ......... 551Horizontal Synchronous Operation ......................... 551

HRCLHold Request Cancellation Request Level Setting Register

(HRCL)............................................... 210HRLC

Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) ...... 212

I

I FlagI Flag ................................................................. 50

I/O MapI/O Map ........................................................... 670

I/O PinCommand 13-0 (I/O Pin Control) ........................... 591Command 13-1 (I/O Pin Control 2)......................... 592

I/O PortBasic Block Diagram of the I/O Port ....................... 128I/O Port Modes .................................................. 129I/O Ports............................................................... 5

I2C InterfaceI2C Interface.......................................................... 4I2C Interface Registers ......................................... 287

IBCRBus Control Register (IBCR)................................. 292

IBSRBus Status Register (IBSR) ................................... 289

ICCRClock Control Register (ICCR) .............................. 298

ICRBit Configuration of the Interrupt Control Register (ICR)

.......................................................... 208Configuration of Interrupt Control Register (ICR) ........ 52Mapping of Interrupt Control Register (ICR)............... 52

IDARData Register (IDAR) .......................................... 305

IDBLIDBL (Clock Disable Register) .............................. 306

IFCRIFCR (FIFO Control Register) ............................... 307

IFDRIFDR (FIFO Data Register)................................... 307

IFNIFN (FIFO Data Count Register) ............................ 306

IFRNIFRN (FIFO Reception Count Register) ................... 309

ILMInterrupt Level Mask (ILM) Register......................... 51

Immediate Transfer InstructionsImmediate Set/16-bit/32-bit Immediate Transfer

Instructions ...........................................709INIT

Setting Initialization Reset (INIT) Clear Sequence ........71Settings Initialization Reset (INIT) ............................68Settings Initialization Reset (INIT) State...................109

INITINIT Pin Input (Settings Initialization Reset Pin) ..........69

Initial ValuesInitial Values and Functions of the Port Function Registers

(PFRs) .................................................133Initialization

Initialization.......................................................273Operation Initialization Reset (RST) ..........................68Operation Initialization Reset (RST) Clear Sequence .....71Setting Initialization Reset (INIT) Clear Sequence ........71Settings Initialization Reset (INIT) ............................68

Input Dot Clock SelectionInput Dot Clock Selection Control...........................543

Input Pin FunctionOperation of the Input Pin Function (in Internal Clock

Mode)..................................................147Input-Output Circuit

Input-Output Circuit Types......................................17Instruction

20-Bit Delayed Branch Macro Instructions ................71632-Bit Delayed Branch Macro Instructions ................71832-Bit Normal Branch Macro Instructions.................717Add-Subtract Instructions......................................705Bit Manipulation Instructions .................................707Branch Instruction with Delay Slot ............................46Branch Instruction without Delay Slot........................48Compare Instructions ...........................................705Coprocessor Control Instructions ............................720Delayed Branch Instructions ..................................713Direct Addressing Instructions ...............................719FR Family Instruction Lists ...................................704How to Read the Instruction Lists ...........................700Immediate Set/16-bit/32-bit Immediate Transfer

Instructions ...........................................709Instruction Format ...............................................703Logic Instructions................................................706Memory Load Instructions ....................................710Memory Store Instructions ....................................711Multiply Instructions............................................708Normal Branch (No Delay) Instructions....................712Operation of INT Instruction....................................61Operation of INTE Instruction..................................61Operation of RETI Instruction ..................................63Operation of Undefined Instruction Exception .............62Other Instructions................................................714Overview of Instructions .........................................34Register-to-Register Transfer Instructions .................711Resource Instructions ...........................................719Shift Instructions.................................................709

INTOperation of INT Instruction....................................61

731

INTEOperation of INTE Instruction .................................61

Internal ArchitectureInternal Architecture..............................................32

Internal Clock ModeOperation of the Input Pin Function

(in Internal Clock Mode) .........................147Internal Clock Operation

Internal Clock Operation ......................................145Internal VCO Generation

Internal VCO Generation Dot Clock Input ................544Interrupt

Clearing Peripheral Interrupts by DMA....................359Command 15-0 (Interrupt Control)..........................596DMA Transfer and Interrupts.................................356DMAC Interrupt Control ......................................362EIT (Exception, Interrupt, and Trap)..........................49Interrupt Control.................................................564Interrupt Factor Flags...........................................564Interrupt Generation Control..................................566Interrupt Levels ....................................................50Interrupt Number ................................................230Interrupt Request Generation .................................201Interrupt Resources and Timing Chart......................166Interrupt Stack .....................................................53Level Mask for Interrupt and NMI ............................51Main Clock Oscillation Stabilization Wait Timer Interrupt

..........................................................123Occurrence of Interrupts and Timing for Setting Flags

..........................................................274Operation of User Interrupt/NMI ..............................60Watch Timer Interrupt..........................................117

Interrupt Control RegisterBit Configuration of the Interrupt Control Register (ICR)

..........................................................208Configuration of Interrupt Control Register (ICR) ........52Mapping of Interrupt Control Register (ICR) ...............52

Interrupt ControllerHardware Configuration of the Interrupt Controller.....204Interrupt Controller .................................................4Interrupt Controller Registers.................................206

Interrupt Enable RegisterInterrupt Enable Register (ENIR)............................220

INTERRUPT IN TransferControl Transfer (Data Stage), Bulk Transfer, or

INTERRUPT IN Transfer ........................414Interrupt Level Mask

Interrupt Level Mask (ILM) Register .........................51Interrupt Sources

Interrupt Sources ................................................423Interrupt Stack

Interrupt Stack .....................................................53Interrupt Vectors

Interrupt Vectors.................................................685Interruption

Command 15-0 (Interruption Control) .....................623Interval Timer

Interval Timer Mode............................................184

Operation of Interval Timer Function .............. 118, 124Other Interval Timers .............................................. 5

Interval Timer ModeInterval Timer Mode ................................... 182, 184

ISBA7-bit Slave Address Register (ISBA) ....................... 303

ISMK7-bit Slave Address Mask Register (ISMK) .............. 304

Italic CharacterOrigin of Italic Character...................................... 488

Italic DisplayItalic Display Control .......................................... 486Italic Display Rules............................................. 486

ITBA10-bit Slave Address Register (ITBA) ..................... 300

ITMK10-bit Slave Address Mask Register (ITMK) ............ 301

L

Latch UpPreventing a Latch Up ........................................... 24

Level MaskLevel Mask for Interrupt and NMI............................ 51

LimitationsLimitations.......................................................... 26

Line BackgroundLine Background Color

(Setting for Each Line, Selected From Among 16 Colors)................................................ 524

Line Background Control (Setting for Each Line) ...... 524Line Character

Line Character Vertical Size Type Control (Setting for Each Line)............................ 481

Line Control DataCommand 3 (Line Control Data Set 1)..................... 575Command 3 (Line Control Data Setting 1)................ 614Command 4 (Line Control Data Set 2)..................... 576Command 4 (Line Control Data Setting 2)................ 615

Line Enlarged DisplayLine Enlarged Display Examples............................ 499

Line EnlargementLine Enlargement Control (Setting for Each Line)...... 498

Line RAMWriting to Line RAM .......................................... 479

Logic InstructionsLogic Instructions............................................... 706

Low-Pass FilterLow-Pass Filter .................................................. 187

Low-Pass Filter Control RegisterLow-Pass Filter Control Register (TxLPCR) ............. 173

Low-power ModesLow-power Modes...................................... 110, 114

LPFLPF Sampling Intervals........................................ 200

732

M

Macro ProgramAutomatic Response of Macro Program to USB Standard

Request Commands................................ 442Macro Program Status after USB Bus Reset.............. 451USB Function Macro Program Operation in the Default

Status.................................................. 444Main

Display Position Control on the Main/CC Screen ....... 465Main Clock Oscillation Stabilization Wait Timer

Main Clock Oscillation Stabilization Wait Timer ....... 120Main Clock Oscillation Stabilization Wait Timer

(for the Subclock Select) ......................... 103Main Clock Oscillation Stabilization Wait Timer Control

Register............................................... 122Main Clock Oscillation Stabilization Wait Timer Interrupt

.......................................................... 123Operation of the Main Clock Oscillation Stabilization Wait

Timer.................................................. 125Precautions on Using the Main Clock Oscillation

Stabilization Wait Timer ......................... 125Mask

Slave Address Mask ............................................ 311Master Addressing

Master Addressing .............................................. 312MB91319

Dimensions of the MB91319 ..................................... 8Pin Layout of the MB91319 ...................................... 9

MB91FV319ABasic Configuration of FR MB91FV319A Serial

Programming Connection ........................ 664MD

Mode Pins (MD0 to MD3) ...................................... 24Memory

Display Memory and Display Screen....................... 476Font Memory Configuration.................................. 475Memory Map................................................. 30, 45Memory Space ..................................................... 30Writing to Display Memory .................................. 477

Memory Load InstructionsMemory Load Instructions .................................... 710

Memory MapFONT RAM Memory Map ................................... 626Memory Map......................................... 30, 45, 632

Memory SpaceMemory Space ..................................................... 30

Memory Store InstructionsMemory Store Instructions.................................... 711

Merge ControlShaded Background Succeeding Character Merge Control

(Setting for Each Character) ..................... 517Shaded Background Succeeding Line Merge Control

(Setting for Each Line).................... 519, 526Minimum Effective Pulse Width

Minimum Effective Pulse Width of the DREQ Pin Input.......................................................... 365

ModeAddressing Mode Symbols ....................................701Bus Modes ..........................................................64Capture Mode.....................................................186Configuration of Flash Control/Status Register (FLCR)

(CPU Mode) .........................................638Event Count Mode...............................................185FR-CPU Programming Mode (16 Bits, Read/Write)

..........................................................642FR-CPU ROM Mode (32 Bits, Read Only)................642I/O Port Modes ...................................................129Interval Timer Mode ............................................184Low-power Modes ......................................110, 114Mode Settings ......................................................65One-shot Mode ...................................................164One-shot Mode Timing Charts ...............................164Operating Modes...........................................64, 269PWM Mode .......................................................162Return from Standby Mode (Sleep/Stop) ..................213Screen Display Modes ..........................................462Transfer Mode ....................................................341Wait Time after Returning from Stop Mode.................79PWM Mode Timing Chart.....................................162

Mode PinsMode Pins (MD0 to MD3) ......................................24

Most Standard CommandsSetup Stage of Control Transfer (Most Standard Commands)

..........................................................410Status Stage of Control Transfer

(Most Standard Commands)......................412Multifunction Timer

Features of the Multifunction Timer ........................170Multifunction Timer ................................................5Registers of the Multifunction Timer .......................172

Multiple CharactersWriting Multiple Characters Collectively (VRAM Fill)

..........................................................478Multiply Instructions

Multiply Instructions............................................708Multiply-by Rate

PLL Multiply-by Rate ............................................77Wait Time after Changing the PLL Multiply-by Rate

............................................................78

N

NMILevel Mask for Interrupt and NMI.............................51NMI .........................................................211, 224Operation of User Interrupt/NMI ..............................60

Normal BranchNormal Branch (No Delay) Instructions....................712

Normal Branch Macro Instructions20-Bit Normal Branch Macro Instructions.................71532-Bit Normal Branch Macro Instructions.................717

Normal ResetNormal Reset Operation..........................................74

733

O

OffsetScreen Display Position Offset ...............................473

One-shot ModeOne-shot Mode...................................................164One-shot Mode Timing Charts ...............................164

Operating ModesOperating Modes ..........................................64, 269

OperationExternal Event Count Operation .............................148Internal Clock Operation ......................................145Operation of the Input Pin Function

(in Internal Clock Mode) .........................147Operation of the Output Pin Function ......................148Other Operation..................................................149Underflow Operation ...........................................146

Operation Initialization ResetOperation Initialization Reset (RST)..........................68Operation Initialization Reset (RST) Clear Sequence.....71Operation Initialization Reset (RST) State ................108

OrderingBit Ordering ........................................................43Byte Ordering ......................................................43

OSCCROscillation Control Register (OSCCR).......................98

Oscillation CircuitQuartz Oscillation Circuit .......................................24

Oscillation Clock FrequencyOscillation Clock Frequency..................................667

Oscillation Control RegisterOscillation Control Register (OSCCR).......................98

Oscillation Stabilization WaitSources of an Oscillation Stabilization Wait ................72

Oscillation Stabilization Wait ResetOscillation Stabilization Wait Reset (RST) Status.......108

Oscillation Stabilization Wait RUN StateOscillation Stabilization Wait RUN State .................108

Oscillation Stabilization Wait TimeSelecting an Oscillation Stabilization Wait Time ..........73

Oscillation Stabilization Wait TimerMain Clock Oscillation Stabilization Wait Timer .......120Main Clock Oscillation Stabilization Wait Timer

(for the Subclock Select)..........................103Main Clock Oscillation Stabilization Wait Timer Control

Register ...............................................122Main Clock Oscillation Stabilization Wait Timer Interrupt

..........................................................123Operation of the Main Clock Oscillation Stabilization Wait

Timer ..................................................125Precautions on Using the Main Clock Oscillation

Stabilization Wait Timer..........................125OSDC

Command 17-0 (OSDC Operation Control 1) ............599Command 17-1 (OSDC Operation Control 2) ............600Features of the OSDC ..........................................455OSDC Function ......................................................5OSDC Operation Control......................................567

Other FeaturesOther Features ....................................................... 6

Other InstructionsOther Instructions ............................................... 714

Other Interval TimersOther Interval Timers .............................................. 5

Other OperationOther Operation ................................................. 149

Output Pin FunctionOperation of the Output Pin Function ...................... 148

OverviewOverview of the 16-bit Reload Timer ...................... 138

P

PaletteCommands 16-0 to 16-15 (Palette Control) ............... 597

Palette RAMPalette RAM Configuration .................................. 480

PCNHRegister Configurations of Control Status Registers

(PCNH and PCNL) ................................ 156PCNL

Register Configurations of Control Status Registers (PCNH and PCNL) ................................ 156

PCSRBit Configuration of PPG Cycle Setting Register (PCSR)

......................................................... 159PDR

Configuration of the Port Data Registers (PDR) ......... 130PDUT

Bit Configuration of PPG Duty Setting Register (PDUT)......................................................... 160

Peripheral ClockPeripheral Clock (CLKP) ....................................... 81

Peripheral InterruptsClearing Peripheral Interrupts by DMA ................... 359

Peripheral Stop ControlPeripheral Stop Control........................................ 103

PFRConfiguration of the Port Function Registers (PFR)

......................................................... 132PFRs

Initial Values and Functions of the Port Function Registers (PFRs) ................................................ 133

Pin FunctionsList of Pin Functions ............................................. 10

Pin LayoutPin Layout of the MB91319 ...................................... 9

Pin StatePin State List ..................................................... 695

PLLDot Clock Generation PLL ................................... 688PLL Multiply-by Rate ........................................... 77PLL Operation Enable ........................................... 76Video Clock PLL ................................................... 5

734

Wait Time after Changing the PLL Multiply-by Rate .... 78Wait Time after Enabling a PLL............................... 78

PLLA ClockCommand 18-0 (PLLA Clock Control 1-1) ............... 601Command 18-1 (PLLA Clock Control 1-2) ............... 601Command 18-2 (PLLA Clock Control 2).................. 602Command 18-3 (PLLA Clock Control 3).................. 602

PLLB ClockCommand 18-4 (PLLB Clock Control 1-1) ............... 603Command 18-5 (PLLB Clock Control 1-2) ............... 603Command 18-6 (PLLB Clock Control 2).................. 604Command 18-7 (PLLB Clock Control 3).................. 604

PLLC ClockCommand 18-10 (PLLC Clock Control 2) ................ 605Command 18-11 (PLLC Clock Control 3) ................ 606Command 18-8 (PLLC Clock Control 1-1) ............... 605Command 18-9 (PLLC Clock Control 1-2) ............... 605

Port Data RegistersConfiguration of the Port Data Registers (PDR) ......... 130

Port Function RegistersConfiguration of the Port Function Registers (PFR)

.......................................................... 132Initial Values and Functions of the Port Function Registers

(PFRs) ................................................ 133Power Supply

Power Supply Pins ................................................ 24Power-Off

Precautions at Power-On/Power-Off ......................... 25Power-On

Power-on ............................................................ 25Precautions at Power-On/Power-Off ......................... 25Source Oscillation Input at Power-on ........................ 25Wait Time after Power-On...................................... 78

PPGPPG..................................................................... 4PPG Output All-L and All-H ................................. 167

PPG Cycle Setting RegisterBit Configuration of PPG Cycle Setting Register (PCSR)

.......................................................... 159PPG Duty Setting Register

Bit Configuration of PPG Duty Setting Register (PDUT).......................................................... 160

PPG TimerBlock Diagram for One Channel of PPG Timer ......... 154Characteristics of PPG Timer ................................ 152Overall Block Diagram of PPG Timer ..................... 153Precautions on Using the PPG Timer....................... 168Registers of the PPG Timer................................... 155

PPG Timer RegisterBit Configuration of PPG Timer Register (PTMR) ..... 161

PrecautionsPrecautions on Using the 16-bit Reload Timer ........... 150

PriorityPriority Among Channels ..................................... 363Priority Decision ................................................ 211Priority of EIT Causes To Be Accepted ..................... 58Priority of State Transition Requests ....................... 109

ProcessingSave/Restore Processing .......................................237

Program AccessProgram Access ....................................................44

ProgrammerSystem Configuration of AF220/AF210/AF120/AF110

Flash Micro-controller Programmer ............667Programming Mode

FR-CPU Programming Mode (16 Bits, Read/Write)..........................................................642

Programming ModelBasic Programming Model ......................................36

PTMRBit Configuration of PPG Timer Register (PTMR) ......161

Pulse WidthMinimum Effective Pulse Width of the DREQ Pin Input

..........................................................365Pulse Width Counter

16-Bit Pulse Width Counter ...................................190Registers of the 16-Bit Pulse Width Counter ..............191

PWCPWC ....................................................................4

PWC Control RegisterPWC Control Register (PWCCH) ...........................194PWC Control Register (PWCCL)............................192PWC Control Register 2 (PWCC2)..........................197

PWC Data RegisterPWC Data Register (PWCD) .................................196

PWCCPWC Control Register 2 (PWCC2)..........................197

PWCCHPWC Control Register (PWCCH) ...........................194

PWCCLPWC Control Register (PWCCL)............................192

PWCDPWC Data Register (PWCD) .................................196

PWCUDUpper Value Setting Register (PWCUD) ..................198

PWM ModePWM Mode .......................................................162PWM Mode Timing Chart.....................................162

Q

Quartz Oscillation CircuitQuartz Oscillation Circuit........................................24

R

RAMBuilt-in RAM .........................................................3FONT RAM Memory Map ....................................626Palette RAM Configuration ...................................480Writing a Single Character to Character RAM ...........477Writing to Line RAM ...........................................479

RDYReady/Busy Signal (RDY/BUSYX).........................648

735

Read/Reset StatusRead/Reset Status ...............................................654

Ready/Busy SignalReady/Busy Signal (RDY/BUSYX) ........................648

REALOSBit Search Module (Used by REALOS) .......................3Reload Timer (Including One Channel for REALOS)......3

Receive OperationReceive Operation...............................................271

ReceptionExample of Controlling DMA Reception..................432Example of Controlling Reception at CPU Access ......427

Recommended SettingRecommended Setting Examples ............................694

Register-to-Register Transfer InstructionsRegister-to-Register Transfer Instructions.................711

Reload OperationReload Operation ................................................351

Reload RegisterReload Register (UTIMR).....................................251

Reload TimerReload Timer (Including One Channel for REALOS)......3

Reload ValuesExample of Setting U-TIMER Baud Rates and Reload

Values .................................................279Request

Built-in Peripheral Request ...................................344Software Request ................................................345

ResetMacro Program Status after USB Bus Reset ..............451Normal Reset Operation .........................................74Operation Initialization Reset (RST)..........................68Operation Initialization Reset (RST) Clear Sequence.....71Operation Initialization Reset (RST) State ................108Oscillation Stabilization Wait Reset (RST) Status.......108Read/Reset Status ...............................................654RESET .............................................................408Reset (Device Initialization) ....................................67Setting Initialization Reset (INIT) Clear Sequence ........71Settings Initialization Reset (INIT)............................68Settings Initialization Reset (INIT) State ..................109Software Reset (STCR: SRST Bit Writing) .................69Synchronous Reset Operation ..................................74Watchdog Reset....................................................70

Reset Source Register/Watchdog Timer Control Register

Reset Source Register/Watchdog Timer Control Register (RSRR) .................................................84

Resource InstructionsResource Instructions...........................................719

RestartSector Erase Restart.............................................661

Restore ProcessingSave/Restore Processing .......................................237

RETIOperation of RETI Instruction..................................63

ROM ModeFR-CPU ROM Mode (32 Bits, Read Only)............... 642

RSIZERSIZE0 ............................................................ 392RSIZE1 ............................................................ 393

RSRRReset Source Register/Watchdog Timer Control Register

(RSRR) ................................................. 84RST

Operation Initialization Reset (RST) ......................... 68Operation Initialization Reset (RST) Clear Sequence .... 71Operation Initialization Reset (RST) State ................ 108Oscillation Stabilization Wait Reset (RST) Status ...... 108

RUN StateOscillation Stabilization Wait RUN State ................. 108RUN State (Normal Operation).............................. 107

S

Sampling IntervalsLPF Sampling Intervals........................................ 200

SaveSave/Restore Processing....................................... 237

SCRSerial Control Register (SCR)................................ 261

ScreenCharacter Background Color

(Setting for Each Screen, Selected from Among 16 Colors)................................................ 515

Code of the Color to be Replaced by the Trimming Color (Setting for Each Screen)......................... 504

Color to be Replaced by the Character Color (Setting for Each Screen)......................... 506

Command 5-00 (Screen Output Control 1)................ 577Command 5-1 (Screen Output Control 2) ................. 578Command 7-1 (Screen Background Character Control 1)

......................................................... 585Command 7-3 (Screen Background Character Control 2)

......................................................... 586Configuration of Screen Background Character Display

......................................................... 534Display Memory and Display Screen ...................... 476Display Position Control of Screen Background Characters

......................................................... 469Display Position Control of Screen Background Color

......................................................... 470Display Position Control on the Main/CC Screen ....... 465Graphic Color/Character Color Replace Control


(Setting for Each Screen)......................... 504Screen Background Character Display Control .......... 535Screen Background Color Control .......................... 537Screen Background Output Control......................... 537Screen Configuration........................................... 459Screen Configuration Drawing............................... 460Screen Configuration Drawing 2 ............................ 461Screen Display Modes ......................................... 462Screen Display Position Offset .............................. 473Screen Output Control ......................................... 464

736

Shaded Background Highlight Color (Setting for Each Screen, Selected from Among 16 Colors) ........................................ 515, 524

Shaded Background Shadow Color (Setting for Each Screen, Selected from Among 16 Colors) ........................................ 515, 524

Translucent Color Control (Setting for Each Screen).......................................................... 513

Transparent Color Control (Setting for Each Screen).......................................................... 511

Screen BackgroundCommand 7-1 (Screen Background Character Control 1)

.......................................................... 585Command 7-3 (Screen Background Character Control 2)

.......................................................... 586Screen Background Color Control .......................... 537Screen Background Display .................................. 533Screen Background Output Control......................... 537

Screen Background CharacterConfiguration of Screen Background Character Display

.......................................................... 534Screen Background Character Display Control .......... 535

Screen Display ModesScreen Display Modes ......................................... 462

Screen Output ControlScreen Output Control ......................................... 464

SectorSector Address Table........................................... 633Sector Erase Restart ............................................ 661Sector Erasure.................................................... 658Temporary Sector Erase Stop ................................ 660

Send OperationSend Operation .................................................. 271

Serial Control RegisterSerial Control Register (SCR)................................ 261

Serial Input Data RegisterSerial Input Data Register (SIDR)/

Serial Output Data Register (SODR) .......... 264Serial Mode Register

Serial Mode Register (SMR) ................................. 259Serial Onboard Writing

Pins Used for Fujitsu Standard Serial Onboard Writing.......................................................... 665

Serial Output Data RegisterSerial Input Data Register (SIDR)/

Serial Output Data Register (SODR) .......... 264Serial Programming Connection

Basic Configuration of FR MB91FV319A Serial Programming Connection ........................ 664

Example of Serial Programming Connection ............. 666Serial Status Register

Functions of Bits in the Serial Status Register (SSR).......................................................... 266

Serial Status Register (SSR) .................................. 265Setting Initialization

Wait Time after Setting Initialization......................... 78Setting Initialization Reset

INIT Pin Input (Settings Initialization Reset Pin) ......... 69

Setting Initialization Reset (INIT) Clear Sequence ........71Settings Initialization Reset (INIT) ............................68Settings Initialization Reset (INIT) State...................109

Setup OperationExample of Controlling the Setup Operation..............426

Setup StageSetup Stage of Control Transfer


Setup Stage of Control Transfer (Most Standard Commands)..........................................................410

Shaded BackgroundCommand 6-1 (Shaded Background Frame Color Control)

..........................................................581Shaded Background Highlight Color



Shaded Background Succeeding Character Merge Control (Setting for Each Character)......................517

Shaded Background Succeeding Line Merge Control (Setting for Each Line) ....................519, 526

Shadow ColorShaded Background Shadow Color


Shift InstructionsShift Instructions.................................................709

SIDRSerial Input Data Register (SIDR)/

Serial Output Data Register (SODR)...........264Single Character

Writing a Single Character to Character RAM ...........477Slave Address

Slave Address Detection .......................................311Slave Address Mask.............................................311

SleepDMA Transfer during Sleep...................................362Return from Standby Mode (Sleep/Stop) ..................213

Sleep StateSleep State.........................................................107

SMRSerial Mode Register (SMR) ..................................259

SODRSerial Input Data Register (SIDR)/

Serial Output Data Register (SODR)...........264Software

A/D Conversion Started by Software .......................247Software Conversion Analog Input Select Register

Software Conversion Analog Input Select Register .....244Software Request

Software Request ................................................345Software Reset

Software Reset (STCR: SRST Bit Writing) .................69

737

Source ClockSelection of Source Clock .......................................75

Source OscillationSource Oscillation Input at Power-on.........................25

SourcesInterrupt Sources ................................................423

Sprite CharacterCommand 8-1 (Sprite Character Control 1) ...............587Command 8-2 (Sprite Character Control 2) ...............588Command 9-0 (Sprite Character Control 3) ...............588Command 9-1 (Sprite Character Control 4) ...............589Display Position Control of Sprite Characters ............471Sprite Character Configuration...............................538Sprite Character Display Control ............................538

SRSTSoftware Reset (STCR: SRST Bit Writing) .................69

SSPSystem Stack Pointer (SSP).....................................53

SSRFunctions of Bits in the Serial Status Register (SSR)

..........................................................266Serial Status Register (SSR) ..................................265

STST1 .................................................................387ST2 .................................................................388ST3 .................................................................389ST4 .................................................................390ST5 .................................................................391

StackInterrupt Stack .....................................................53

StageControl Transfer (Data Stage) and BULK OUT Transfer


INTERRUPT IN Transfer ........................414Setup Stage of Control Transfer

(Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame])......................................411


Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame])......................................412

Status Stage of Control Transfer (Most Standard Commands) .....................412

Standard CommandsSetup Stage of Control Transfer

(Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame])......................................411

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame])......................................412

StandbyReturn from Standby ...........................................223

Standby Control RegisterStandby Control Register (STCR) ............................ 86

Standby ModeReturn from Standby Mode (Sleep/Stop).................. 213

START ConditionSTART Condition .............................................. 310

State TransitionPriority of State Transition Requests ....................... 109

Status StageStatus Stage of Control Transfer


Status Stage of Control Transfer (Most Standard Commands) ..................... 412

STCRSoftware Reset (STCR: SRST Bit Writing)................. 69Standby Control Register (STCR) ............................ 86

Step Trace TrapOperation of Step Trace Trap .................................. 62

Step/Block TransferStep/Block Transfer 2-Cycle Transfer ..................... 349Step/Block Transfer 2-Cycle Transfer Fly-by Transfer

......................................................... 350Stop

Return from Standby Mode (Sleep/Stop).................. 213Temporary Sector Erase Stop ................................ 660

STOP ConditionSTOP Condition................................................. 310

Stop ModeWait Time after Returning from Stop Mode ................ 79

Stop StateStop State ......................................................... 107

SubclockMain Clock Oscillation Stabilization Wait Timer

(for the Subclock Select) ......................... 103Subtract Instructions

Add-Subtract Instructions ..................................... 705Succeeding Character

Shaded Background Succeeding Character Merge Control (Setting for Each Character) ..................... 517

Succeeding LineShaded Background Succeeding Line Merge Control

(Setting for Each Line).................... 519, 526Suspended Status

Example of USB Clock Control in the Suspended Status......................................................... 445

Sync SignalSync Signal Input ............................................... 548

SynchronizationCommand 11-0 (Synchronization Control) ............... 590Examples of Vertical Synchronization Detection Operation

......................................................... 550Synchronization Control (Vertical Enlargement Control)

......................................................... 561Vertical Synchronization Detection......................... 549

738

Synchronization ControlSynchronization Control (Vertical Enlargement Control)

.......................................................... 561Synchronous

Example of Horizontal Synchronous Operation ......... 551Horizontal Synchronous Operation ......................... 551

Synchronous ResetSynchronous Reset Operation .................................. 74

System ConfigurationSystem Configuration of AF220/AF210/AF120/AF110

Flash Micro-controller Programmer ........... 667System Stack Pointer

System Stack Pointer (SSP) .................................... 53

T

Table Base RegisterTable Base Register (TBR) ..................................... 54

TBCRTime Base Counter Control Register (TBCR).............. 88

TBRTable Base Register (TBR) ..................................... 54

Temporary Sector Erase StopTemporary Sector Erase Stop ................................ 660

Temporary StoppingTemporary Stopping............................................ 359

Time Base CounterTime Base Counter ............................................. 100

Time Base Counter Clear RegisterTime Base Counter Clear Register (CTBR)................. 91

Time Base Counter Control RegisterTime Base Counter Control Register (TBCR).............. 88

Timer Compare Data RegisterTimer Compare Data Register (TxDRR) .................. 179

Timer Setting RegisterTimer Setting Register (TxTCR) ............................ 176

Timing ChartInterrupt Resources and Timing Chart ..................... 166One-shot Mode Timing Charts............................... 164PWM Mode Timing Chart .................................... 162

TMCSRBit Configuration of the Control Status Register (TMCSR)

.......................................................... 140Bit Functions of the Control Status Register (TMCSR)

.......................................................... 140TMODE

TMODE ........................................................... 181TMR

Bit Configuration of the 16-bit Timer Register (TMR).......................................................... 143

TMRLRBit Configuration of the 16-bit Reload Register (TMRLR)

.......................................................... 144Tool Reset Pins

Tool Reset Pins (TRST) ......................................... 24

Trace TrapOperation of Step Trace Trap ...................................62

TransferBlock Transfer....................................................370Burst 2-Cycle Transfer .........................................346Burst Fly-by Transfer ...........................................347Burst Transfer ....................................................371Control Transfer (Data Stage) and BULK OUT Transfer


INTERRUPT IN Transfer ........................414CPU IN Transfer .................................................416CPU OUT Transfer..............................................418Demand Transfer ................................................372Demand Transfer 2-Cycle Transfer..........................347Demand Transfer Fly-by Transfer ...........................348DMA IN Transfer................................................419DMA OUT Transfer ............................................420DMA Transfer and Interrupts .................................356DMA Transfer during Sleep...................................362DMA Transfer Request during External Hold ............357External Hold Request During DMA Transfer............357Flow of Data During 2-Cycle Transfer .....................373Flow of Data During Fly-By Transfer ......................375If an External Pin Transfer Request is Reentered During

Transfer ...............................................369If Another Transfer Request Occurs During Block Transfer

..........................................................369Precautions for Control Transfer .............................449Read and Write Timing Diagrams for DMA Block/

Step Transfer.........................................421Read and Write Timing Diagrams for DMA Demand

Transfer ...............................................422Selection of the Transfer Sequence ..........................346Setting of Transfer Enable (BFOK) Bits during Control

Transfer ...............................................448Setup Stage of Control Transfer



Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request .........................357

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame]) ......................................412

Status Stage of Control Transfer (Most Standard Commands)......................412

Step/Block Transfer 2-Cycle Transfer ......................349Step/Block Transfer 2-Cycle Transfer Fly-by Transfer

..........................................................350Timing Diagram for BULK IN Transfer

(Writing by CPU and Reading by USB).......436Timing Diagram for BULK OUT Transfer

(Reading by CPU and Writing by USB).......438Timing of the DREQ Pin Input for Continuing Transfer Over

the Same Channel...................................368Transfer Address.................................................342Transfer Between External I/O and External Memory

..........................................................369

739

Transfer Count and Transfer End ............................343Transfer Count Control ........................................355Transfer Mode ...................................................341Transfer Request Acceptance and Transfer ...............358Transfer Type ....................................................342

Transfer AddressTransfer Address ................................................342

Transfer CountTransfer Count and Transfer End ............................343

Transfer Count ControlTransfer Count Control ........................................355

Transfer DataTransfer Data Format...................................271, 272

Transfer Destination Address Setting RegistersTransfer Source/Transfer Destination Address Setting

Registers (DMASA0 to 4/DMADA0 to 4)..........................................................336

Transfer InstructionsImmediate Set/16-bit/32-bit Immediate Transfer

Instructions...........................................709Transfer Mode

Transfer Mode ...................................................341Transfer Request

If an External Pin Transfer Request is Reentered During Transfer ...............................................369

If Another Transfer Request Occurs During Block Transfer..........................................................369

Transfer SequenceSelection of the Transfer Sequence..........................346

Transfer SourceTransfer Source/Transfer Destination Address Setting

Registers (DMASA0 to 4/DMADA0 to 4)..........................................................336

Transfer TypeTransfer Type ....................................................342

TransitionPriority of State Transition Requests........................109Transition of Device States ...................................105

Translucent ColorCommand 6-2 (Transparent/Translucent Color Control)

..........................................................582Translucent Color Control (Setting for Each Screen)

..........................................................513Transmission

Example of Controlling DMA Transmission .............433Example of Controlling Transmission at CPU Access

..........................................................429Transparent

Command 6-2 (Transparent/Translucent Color Control)..........................................................582

Transparent ColorTransparent Color Control (Setting for Each Screen)

..........................................................511Trap

Coprocessor Error Trap ..........................................63EIT (Exception, Interrupt, and Trap)..........................49No-coprocessor Trap .............................................63

Operation of Step Trace Trap .................................. 62Trigger

A/D Conversion Started by External Trigger ............. 247Trimming

Code of the Color to be Replaced by the Trimming Color (Setting for Each Screen)......................... 504

Trimming Colors ................................................ 497Trimming Display Rules ...................................... 497Trimming Output Control ..................................... 490Trimming Type Control ....................................... 491

Trimming ColorCode of the Color to be Replaced by the Trimming Color


(Setting for Each Screen)......................... 504TRSIZE

TRSIZE ........................................................... 407TRST

Tool Reset Pins (TRST) ......................................... 24TTSIZE

TTSIZE............................................................ 406TxCCR

Capture Control Register (TxCCR) ......................... 174TxCRR

Capture Data Register (TxCRR)............................. 180TxDRR

Timer Compare Data Register (TxDRR) .................. 179TxLPCR

Low-Pass Filter Control Register (TxLPCR) ............. 173TxR

Enter Timer Control Register (TxR)........................ 178TxTCR

Timer Setting Register (TxTCR) ............................ 176

U

UARTExample of Using the UART................................. 277Selecting a Clock for the UART............................. 270UART.................................................................. 3

UCLK48Accuracy of UCLK48.......................................... 447

Undefined InstructionOperation of Undefined Instruction Exception............. 62

Underflow OperationUnderflow Operation........................................... 146

Underline DisplayUnderline Display Control .................................... 489Underline Display Rule........................................ 489

Unused Input PinsUnused Input Pins................................................. 24

Upper Value Setting RegisterUpper Value Setting Register (PWCUD).................. 198

USBAutomatic Response of Macro Program to USB Standard

Request Commands................................ 442

740

Detection of USB Connector Connection and Disconnection.......................................................... 446

Example of USB Clock Control in the Suspended Status.......................................................... 445

Macro Program Status after USB Bus Reset.............. 451Operation of the USB Function .............................. 409Overview of the USB Function .............................. 378Supplementary Notes on the USB Function .............. 435Timing Diagram for BULK IN Transfer

(Writing by CPU and Reading by USB) ...... 436Timing Diagram for BULK OUT Transfer

(Reading by CPU and Writing by USB) ...... 438USB Function ........................................................ 5USB Function Macro Program Operation in the Default

Status.................................................. 444USB Clock

USB Clock........................................................ 690USB Function Macro Program

USB Function Macro Program Operation in the Default Status.................................................. 444

USB InterfaceUSB Interface Registers ....................................... 381

User InterruptOperation of User Interrupt/NMI .............................. 60

UTIMU-TIMER (UTIM) .............................................. 251

UTIMCPrecautions on the U-TIMER Control Register (UTIMC)

.......................................................... 253U-TIMER Control Register (UTIMC) ..................... 252

U-TIMERExample of Setting U-TIMER Baud Rates and Reload

Values................................................. 279Overview of the U-TIMER ................................... 250U-TIMER (UTIM) .............................................. 251U-TIMER Registers ............................................ 251

U-TIMER Control RegisterPrecautions on the U-TIMER Control Register (UTIMC)

.......................................................... 253U-TIMER Control Register (UTIMC) ..................... 252

UTIMRReload Register (UTIMR) .................................... 251

V

VCOInternal VCO Generation Dot Clock Input ................ 544

Vector TableEIT Vector Table.................................................. 54

Vendor CommandsSetup Stage of Control Transfer


Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands[Get_Descriptor, Set_Descriptor, and Synch_Frame]) ..................................... 412

Vertical Display PeriodVertical Display Period Control ..............................559

Vertical Display PositionCommand 5-2 (Vertical Display Position Control)

..................................................579, 618Vertical Enlargement Control

Synchronization Control (Vertical Enlargement Control)..........................................................561

Vertical SizeCharacter Vertical Size A/B...................................482Command 6-0 (Character Vertical Size Control)

..................................................580, 619Line Character Vertical Size Type Control

(Setting for Each Line) ............................481Vertical Synchronization

Examples of Vertical Synchronization Detection Operation..........................................................550

Vertical Synchronization Detection .........................549Video Clock

Video Clock PLL ....................................................5VRAM

Command 0 (VRAM Write Address Set) ..................572Command 0 (VRAM Write Address Setting) .............611Writing Multiple Characters Collectively (VRAM Fill)

..........................................................478

W

Wait TimeWait Time after Changing the PLL Multiply-by Rate.....78Wait Time after Enabling a PLL ...............................78Wait Time after Power-On ......................................78Wait Time after Returning from Stop Mode.................79Wait Time after Setting Initialization .........................78

Watch TimerOperation of The Watch Timer ...............................119Precautions for Using the Watch Timer ....................119Watch Timer ......................................................102Watch Timer Control Register................................116Watch Timer Interrupt ..........................................117

Watchdog ResetWatchdog Reset ....................................................70

Width Pulse CounterBasic Operation of the 16-Bit Width Pulse Counter .....199

WritingData Writing ......................................................655Writing/Erase .....................................................653

741

CM71-10126-2E

FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL

FR60

32-BIT MICROCONTROLLER

MB91319 Series

HARDWARE MANUAL

February 2006 the second edition

Published FUJITSU LIMITED Electronic Devices

Edited Business Promotion Dept.

controller manual - fujitsu · this chapter describes the interrupt controller, the configuration...

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