control design of pwm converters: the user friendly...
TRANSCRIPT
1
All rights reserved. Duplication or copying is not permitted
without written permission by author
Prof. Sam Ben-Yaakov
Control Design of PWM Converters: The User Friendly Approach
Email: [email protected];
Web: http://www.ee.bgu.ac.il/~pel/
Seminar material download: PET06
Power Electronics Technologies Conference
Long Beach CA, October 2006
Prof. S. Ben-Yaakov , Control Design of PWM Converters [2]
Motivation
Most switch mode systems need to operated
in closed loop
Performance largely dependent on the Compensator
(feedback) design
Loop control design is conceived as “black magic”
OR requiring tedious analytical derivations
Digital control is becoming relevant
2
Prof. S. Ben-Yaakov , Control Design of PWM Converters [3]
Objective
To present a user friendly version of control loop design including both analog and digital control
Based on:
Intuition
Simulation
Simple calculations
Prof. S. Ben-Yaakov , Control Design of PWM Converters [4]
Outline
1. Basics of feedback theory and graphical representation
2. Relationship between LoopGain and dynamic response
3. PWM converters as feedback systems
4. Voltage Mode (VM) control
5. Current Mode (dual loop) control
6. Simulation tools
7. Average models
8. Analog compensator networks
9. Digital control
10. Q&A
3
Prof. S. Ben-Yaakov , Control Design of PWM Converters [5]
1. Basics of feedback theory and graphical representation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [6]
Block diagram of a feedback systems(one loop)
ββββ
OLAεεεεS
inS
fS
+
-
outS
OL
OL
in
oCL
Aβ1
A
S
SA
⋅⋅⋅⋅++++========
β
1
S
S
1Aβin
o
OL
=>>⋅
OL1Aβin
o AS
S
OL
====<<<<<<<<⋅⋅⋅⋅
OLALG ββββ≡≡≡≡
4
Prof. S. Ben-Yaakov , Control Design of PWM Converters [7]
Block Diagram
2H
εεεεSinS
fS
+
-
outS
K
P1H
43421
)) ))ffff (( ((LGLGLGLGPPPPKKKKHHHHHHHH1111
PPPPHHHHSSSSSSSSAAAA 1111
inininin
ooooCLCLCLCL
21+==
Prof. S. Ben-Yaakov , Control Design of PWM Converters [8]
Effect of Feedback
εεεεSinS
fS
+
-
outSP
2H K
321)f(LG
KPH1
P
S
SA
2in
oCL ++++
========KH
1A
21)f(LGCL ====>>>>>>>>
5
Prof. S. Ben-Yaakov , Control Design of PWM Converters [9]
PWM Converter
mβ eβ
Prof. S. Ben-Yaakov , Control Design of PWM Converters [10]
Block diagram concepts
εεεεSinS
fS
+
-
outS
K
P1H
2HinV
++
321)f(LG
KPH1
PH
S
SA
1
1
in
oCL ++++
========
K
1A
1)f(LGCL ====>>>>>>>>
Power
stage
Vref
+
-
MOD
R1
R2
VeD
mβ eβ
Vo v
o
d ve
Vin
Power
R3C
6
Prof. S. Ben-Yaakov , Control Design of PWM Converters [11]
Audio susceptibility
εεεεSinS
fS
+
-
outS
K
P1H
2HinV
++
fS
+
-
outS
KP 1H
inV
2H
LG1
H
V
S 2
in
o
+=
Prof. S. Ben-Yaakov , Control Design of PWM Converters [12]
εεεε′′′′SinS′′′′
fS′′′′
+
-
outSP
1H K
εεεεSinS
fS
+
-
outSP1H
K
kH
1
PH1
P
S
SA
k
1
PHk1
PH
S
SA
11in
outCL
1
1
in
outCL →→→→
++++====
′′′′====′′′′→→→→
++++======== ≠≠≠≠
But loop gains are equal: PKH)f(LG 1====
7
Prof. S. Ben-Yaakov , Control Design of PWM Converters [13]
Block diagram division
BA)f(LG ====
A – known (power stage + divider)
B – unknown (have to be designed)
εεεε′′′′SinS′′′′
fS′′′′
+
-
outS
K
P1HA
B
Prof. S. Ben-Yaakov , Control Design of PWM Converters [14]
Graphical representation of BAconventional method
Tedious – need to re-plot BA
Analysis (not design) oriented
Requires iterations
A
]dB[B
3f
B
]dB[A
2f1f
]Hz[f
]Hz[f
]dB[AB
AB
3f2f1f
]Hz[f
8
Prof. S. Ben-Yaakov , Control Design of PWM Converters [15]
]dB[A
]Hz[fo
kHz1fo ====
AdB40 dec/dB20−−−−
1>BABABABA 1BA <<<<
1BA ====BA)f(LG ====
dB20B
1
Graphical Representation of BA
kHz10
20log(BA)B
120logA20log ====−−−−
1ABB
120log20logA ====⋅⋅⋅⋅⇒⇒⇒⇒====
Prof. S. Ben-Yaakov , Control Design of PWM Converters [16]
αααα
ωωωωj
σσσσ
1...sasa
1...sbsb)s(H
1n1n
nn
1m1m
mm
++++++++++++++++++++++++
==== −−−−−−−−
−−−−−−−−
Stability of Feedback System
Pole−−−−
Zero−−−−
te)tsin( ααααωωωω RHP solutions include the term
9
Prof. S. Ben-Yaakov , Control Design of PWM Converters [17]
Stability Criterion
)f(LG1
KHA 1
CL ++++====
The system is unstable if 1+LG(f) has roots in the right half of the complex plane.
Nyquist criterion is a test for location of 1+LG(f) roots.
Nyquist criterion is normally translated into the Bode plane (frequency domain)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [18]
Nyquist
Stable
unit circle-1 0f ====
)]f(LGIm[
)]f(LGRe[
mΦΦΦΦ |LG|
10
Prof. S. Ben-Yaakov , Control Design of PWM Converters [19]
)]f(LGRe[
)]f(LGIm[
unit circle-1
mΦΦΦΦ
0f ====
Nyquist
Oscillatory
Prof. S. Ben-Yaakov , Control Design of PWM Converters [20]
Nyquist
Unstable
The culprit: Phase Lag
Phase Lead in LG can help stabilize a system
unit circle-1 0f ====
)]f(LGIm[
)]f(LGRe[
mΦΦΦΦ
mΦΦΦΦ
Phase Lead
Phase Lag
11
Prof. S. Ben-Yaakov , Control Design of PWM Converters [21]
Bode plane
oφ
BA
mϕ
1BA ====
o
1|BA|
o
1|BA|m 180)180( ++++ϕϕϕϕ====−−−−−−−−ϕϕϕϕ====ϕϕϕϕ ========
Prof. S. Ben-Yaakov , Control Design of PWM Converters [22]
Bode plane
oφ
BA
mϕ
1BA ====
o
1|BA|
o
1|BA|m 180)180( ++++ϕϕϕϕ====−−−−−−−−ϕϕϕϕ====ϕϕϕϕ ========
12
Prof. S. Ben-Yaakov , Control Design of PWM Converters [23]
Minimum Phase Systemsno Right Half Plane Zero (RHPZ)
]dB[A
]Hz[f1f 2f
]Hz[f
dec/db20−−−−
dec/db40−−−−
o45−−−−
o90−−−−
o135−−−−
o180−−−−
0
phase
Prof. S. Ben-Yaakov , Control Design of PWM Converters [24]
Rate of closure (ROC)(minimum phase systems)
++++
====⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
++++⋅⋅⋅⋅
++++⋅⋅⋅⋅
++++
⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
++++⋅⋅⋅⋅
++++⋅⋅⋅⋅
++++
====
p321
321
f
fj1
k
f
fj1
f
fj1
f
fj1
f
fj1
f
fj1
f
fj1
BA
decdb20+
decdb20−
decdb40−
decdb20−
dBBA
13
Prof. S. Ben-Yaakov , Control Design of PWM Converters [25]
Application of the 1/B curveRate of closure
Rate of closure of BA is the difference
between the A and B slopes
No need to re-plot BA
Design oriented approach
1f 2f
A
B
1
dB
]Hz[f
closureofrate
dec/dB20−−−−
dec/dB40−−−−
Prof. S. Ben-Yaakov , Control Design of PWM Converters [26]
Stability Criterion
f
decdb0
decdb20−
decdb40−
decdb60−
dbA s
s
s
s
u
u
dbB
1
decdb20+
decdb0
decdb20−
decdb40−
If rate of closure system is stabledecdb20−
14
Prof. S. Ben-Yaakov , Control Design of PWM Converters [27]
Phase Margin Examples
om 90====ϕϕϕϕ o
m 45====ϕϕϕϕ
dec/dB20
dec/dB20
dec/dB20−−−−
dec/dB0
dec/dB0
dec/dB20−−−−
om 45====ϕϕϕϕ
om 45====ϕϕϕϕ
om 90====ϕϕϕϕ
om 90====ϕϕϕϕ
f
dB
dec/dB40−−−−
dec/dB60−−−−
dec/dB20−−−−
A
B
1
Prof. S. Ben-Yaakov , Control Design of PWM Converters [28]
Phase Margin Calculation
For minimum phase systems history is not important
Of
]Hz[f
dec/dB20−−−−dec/dB40−−−−
dec/dB20−−−−
p
p
p
dec/dB40−−−−
z
pz
]dB[A
B
1
15
Prof. S. Ben-Yaakov , Control Design of PWM Converters [29]
Approximate Phase Margin Calculation
Of
]Hz[f
dec/dB20−−−−dec/dB40−−−−
dec/dB20−−−−
p
p
p
dec/dB40−−−−
z
p z
]dB[A
B
1
Get the accurate phase at intersection by simulation
Phase lead in B
Phase lag in A
Prof. S. Ben-Yaakov , Control Design of PWM Converters [30]
Design Steps
Draw A
Select cross point of BA (<< than fs/2, for PWM)
Select B shape
A
1/B
|BA|
16
Prof. S. Ben-Yaakov , Control Design of PWM Converters [31]
Stability of a Source-Load System
POL
POL
POL
Front
EndConverter
ZS
ZL
ZL →→→→ negative resistance
BUS
Prof. S. Ben-Yaakov , Control Design of PWM Converters [32]
System stability
VO Z
L
Vex +
- IOZS
1
LS
ZZ
1LoopGain =
Vex ZL
VO
IO
ZS
Convenient way to examine the LG stability is the Nyquiststability test
17
Prof. S. Ben-Yaakov , Control Design of PWM Converters [33]
2. Relationship between Loop Gain and dynamic response
Prof. S. Ben-Yaakov , Control Design of PWM Converters [34]
Response in Closed Loop
εS
inS
fS
outSA1H
K
( )K
10A
50 for
1ω
s
1
K
1A
50 for
1Qω
s
ω
s
1
K
1 A:get weWhat
K
1 A:Desired
CL
om
0
CL
om
02
0
2CL
CL
=
≥+
⋅=
≤
++
⋅=
=
ϕϕϕϕ
ϕϕϕϕ
For small ϕϕϕϕm, ACL behaves
as a second order system
18
Prof. S. Ben-Yaakov , Control Design of PWM Converters [35]
Overshoot and Q in Closed Loop in Response to step in Sin
om
m
m 50 for sin
cosQ <<<<ϕϕϕϕ
ϕϕϕϕϕϕϕϕ
≅≅≅≅
om 45 target Design ≥ϕϕϕϕ
Prof. S. Ben-Yaakov , Control Design of PWM Converters [36]
Load-Step Response
εS
inS
fS
outSA1H
K
oZI ∆
outS
A 1H K
oZI ∆
43421LG
1
o
∆
out
KHA1
Z
I
S
⋅⋅+=
Small-signal output impedance
19
Prof. S. Ben-Yaakov , Control Design of PWM Converters [37]
Load-Step Response
Affected by:
Output impedance
ESR of output capacitor
Slew rate of inductor
Zof
Prof. S. Ben-Yaakov , Control Design of PWM Converters [38]
Output Impedance(Immunity to load changes)
Frequency
1.0Hz 1.0KHz 1.0MHz
db( V(OUT_S)/ i(V5))
-200
-100
0
Frequency
1.0Hz 1.0KHz 1.0MHz
db(v(out)/V(LG_IN))
db( V(OUT)/ V(LG_OUT))
-100
-50
0 Frequency
1.0Hz 1.0KHz 1.0MHz
db( V(OUT_S)/i(V5))
-40
0
40
LG
o
o
outof
BA1
Z
i
vZ
+=
∆=
ZO
ZOf
A
1/B
Buck converter – small signal
20
Prof. S. Ben-Yaakov , Control Design of PWM Converters [39]
Audio-Susceptibility (Line Regulation)(Immunity to input voltage changes)
refV
fS-
outV
PSComp
K
+
+
2HinV
Large LG reduces susceptibility
(((( ))))fLG1
H
V
V 2
in
out
++++====
Prof. S. Ben-Yaakov , Control Design of PWM Converters [40]
Steady-state (DC) Error
εεεεSinS
fS
+
-
outSP1H
K
LG1
SS in
++++====εεεε
Sε is the offset between the
sampled output and reference
Small DC error for large LG(0)
Powerstage
Vref
+
-
MOD
R1
R2
Ve
D
mβ eβ
Vo v
o
d ve
Vin
Power
R3C
21
Prof. S. Ben-Yaakov , Control Design of PWM Converters [41]
Dynamic ResponseSummary
Systems that have a slope of –20 db/dec are easy to control Response is largely determined by LG(f)
Desired LG:
LG as large as possible at low frequencies
(small DC errors)
LG of large BW - intersection point of A and 1/B
(quick response, fast recovery, rejection of Vin changes)
Phase margin > 450
(reasonable overshoot)
The culprit: Phase delay in LG
Prof. S. Ben-Yaakov , Control Design of PWM Converters [42]
Nyquist
unit circle-1 0f ====
)]f(LGIm[
)]f(LGRe[
mΦΦΦΦ
mΦΦΦΦ
om 45 target Design ≥ϕϕϕϕ
22
Prof. S. Ben-Yaakov , Control Design of PWM Converters [43]
3. PWM converters as feedback systems
Issues:
Stability
Rejection of input voltage variations (audio susceptibility)
Immunity to load changes Quick response to reference change - good
tracking.
Prof. S. Ben-Yaakov , Control Design of PWM Converters [44]
PWM converter in closed loop
Small signal responses
Linearization around operating point
Power
stage
Vref
+
-
MOD
R1
R2
Ve
D
mβ eβ
Vo v
o
d ve
Vin
Power
R3C
23
Prof. S. Ben-Yaakov , Control Design of PWM Converters [45]
Type of BlocksSmall Signals (Perturbation) Responses
Power stage is a Switching System (may be non linear)
Feedback is an analog or digital controller
Modulator: mixed mode
Linear control theory based design → small signal response
Power
stage
Vref
+
-
MOD
R1
R2
Ve
D
mβ eβ
Vo v
o
d ve
Vin
Power
R3C
Prof. S. Ben-Yaakov , Control Design of PWM Converters [46]
Small-Signals (Perturbation) Responses
Analytical solutions
Simulation
Injection of sinusoidal perturbation
AC analysis of behavioral average model
This seminar promotes the simulation approach
24
Prof. S. Ben-Yaakov , Control Design of PWM Converters [47]
Small signal response of the modular
Relationship between ve and d (Km =d/ve)
Powerstage
Vref
+
-
MOD
R1
R2
Ve
D
mβ eβ
Vo v
o
d ve
Vin
Power
R3C
Prof. S. Ben-Yaakov , Control Design of PWM Converters [48]
t
t
Zoom
Ve
D
t
dD
d is the AC component of D
Small d
25
Prof. S. Ben-Yaakov , Control Design of PWM Converters [49]
ModulatorModulator
( )v
s
vpt V
T
tVVV +
−=
( )v
s
onvpet V
T
tVVVV +
−==
( )vp
veon
s
on
VV
VVD
T
t
−−
==
Oscillator
am
a
e
vp
e
V
1
ve
dK
V
v
VV
vd
==
=−
=
Prof. S. Ben-Yaakov , Control Design of PWM Converters [50]
THE CONTROL DESIGN PROBLEM
mβ eβ
( ) FunctionlogAnafv
v
e
o −
A →→→→ Power Stage ; B →→→→ compensator e
mv
dβ =
KNOWN CONTROL
DESIGN
26
Prof. S. Ben-Yaakov , Control Design of PWM Converters [51]
4. Voltage mode (one loop) control
Prof. S. Ben-Yaakov , Control Design of PWM Converters [52]
Block diagram
The power conversion system
refV
oo v,V
( )power
inV( )power
Controller
27
Prof. S. Ben-Yaakov , Control Design of PWM Converters [53]
Buck small-signal frequency response (CCM)
MOD
Io
RL
CD
LS Vo
ESR
vo
io
D d
VD
vex
Prof. S. Ben-Yaakov , Control Design of PWM Converters [54]
Buck frequency response (CCM)
20
0
-20
-40
vo
d, dB
f, Hz1k 10k 100k100
3
1
2
-40dB/dec
-20dB/decUnstable
Second order plus zero due to ESR of CO
28
Prof. S. Ben-Yaakov , Control Design of PWM Converters [55]
Dependence on Vin
Vin:
5V
10V
15V
Frequency
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
p(V(a))
-200d
-100d
0d
SEL>>
db(V(a))
-80
-40
0
40Vin
Phase
Magnitude
ev
d
Prof. S. Ben-Yaakov , Control Design of PWM Converters [56]
Effect of Load
Frequency
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
p(V(a))
-200d
-100d
0d
SEL>>
db(V(a))
-80
-40
0
40
RL=
10ΩΩΩΩ - CCM
50 ΩΩΩΩ - DCM
100 ΩΩΩΩ - DCM
Phase
Magnitude
ev
d
29
Prof. S. Ben-Yaakov , Control Design of PWM Converters [57]
Buck Derived Converters
Forward
Half bridge (HB)
Full Bridge (FB)
Simulation is the simplest way to obtain the transfer functions
Prof. S. Ben-Yaakov , Control Design of PWM Converters [58]
Boost Power StageSmall signal response
RHPZ – non minimum-phase system
Frequency
100Hz 10KHz 1.0MHz10Hz
p(V(OUT)/V(DON))
-400d
-200d
0d
SEL>>
DB(V(OUT)/V(DON))
-50
0
50
Magnitude
Phase
30
Prof. S. Ben-Yaakov , Control Design of PWM Converters [59]
CM Boost
Frequency
100Hz 10KHz 1.0MHz10Hz
p(V(OUT)/V(verror))
-200d
-100d
0d
DB(V(OUT)/V(verror))
-40
0
40
SEL>>
Prof. S. Ben-Yaakov , Control Design of PWM Converters [60]
Buck-Boost (Flyback) Power Stage
Frequency
100Hz 10KHz 1.0MHz10Hz
DB(V(OUT)/V(don))
-40
0
40
p(V(OUT)/V(don))-200d
-100d
0d
SEL>>
RHPZ – non minimum-phase system
31
Prof. S. Ben-Yaakov , Control Design of PWM Converters [61]
5. Current Mode (dual loop) control
Prof. S. Ben-Yaakov , Control Design of PWM Converters [62]
Current Feedback
The problem of voltage mode control:
Transfer function is second order
Solution: Add current Feedback
System order is reduced for each state variable (inner loop) feedback
32
Prof. S. Ben-Yaakov , Control Design of PWM Converters [63]
The effect of current feedback
N
1
v
i
e
o =
AMP
MOD
N
Io
RL
CD
LS
Vin
εVeV
Vo
D d
io v
o
ve
For ‘strong’ feedback
eo
ε
vN
1i
0v 1LG
=
→>>
Prof. S. Ben-Yaakov , Control Design of PWM Converters [64]
Transfer function with closed Current Loop
Co RL
N
ve
First order system !
LoRC
1
⋅π2
Le R
N
vov
AMP
MOD
N
Io
RL
CD
LS
Vin
εVeV
Vo
D d
io v
o
ve
33
Prof. S. Ben-Yaakov , Control Design of PWM Converters [65]
Current Mode
AMP
MOD
K
L
S
εV
d
io v
o
ve AMP
innerloop
outerloop
vref
Co R
L
First orderFlat
Prof. S. Ben-Yaakov , Control Design of PWM Converters [66]
The advantages of current feedback
e
o
v
v
decdb40−
decdb20−
Typical power stage VM
e
o
v
v
decdb40−
decdb20−
Same power stage (outer loop) with CM
34
Prof. S. Ben-Yaakov , Control Design of PWM Converters [67]
7. Peak Current Mode (PCM) control
Prof. S. Ben-Yaakov , Control Design of PWM Converters [68]
PCM Modulator
!sametheis)D(fV
Von
in
o =
ee v V ,
d
D
35
Prof. S. Ben-Yaakov , Control Design of PWM Converters [69]
Implementation CM Boost
Some controllers have amplifiers for sensed current
Driver
FF
Clock
L
R
compSRSCf
Rf
VrefError AMP
Prof. S. Ben-Yaakov , Control Design of PWM Converters [70]
The nature of Subharmonic Oscillations
The geometric explanationLI
LI
1I∆
2I∆
2I∆
1I∆
eV
eV
STt
t
D>0.5 ∆I2>∆I1
D<0.5 ∆I2<∆I1
For D>0.5 need slope compensation
36
Prof. S. Ben-Yaakov , Control Design of PWM Converters [71]
Extra delay in PCM (Ridley)
PCM is a current sampling process
Subject to sampling delay
Delay was derived by Ray Ridley
Important for frequencies above fs/10/10/10/10 Mostly of theoretical importance
Prof. S. Ben-Yaakov , Control Design of PWM Converters [72]
Average Current Mode (ACM)Block diagram
refV
- + -+
fvZ invZ
fiZ
Vo
PWM mod
Current sample is filtered first attenuate high frequency (fS)
37
Prof. S. Ben-Yaakov , Control Design of PWM Converters [73]
PCM and ACM
Both are current feedbacks
Both reduce the order of system
The difference is in BW of the
current feedback loop
Both increase the output impedance
Prof. S. Ben-Yaakov , Control Design of PWM Converters [74]
Advantages of peak CM (PCM)
∗∗∗∗ Cycle by cycle protection
∗∗∗∗ Better dynamics
Disadvantages
∗∗∗∗ Leading edge spike
∗∗∗∗ Subharmonic oscillations
38
Prof. S. Ben-Yaakov , Control Design of PWM Converters [75]
6. Simulation tools
General purpose simulators
Dedicated simulators
PC and web based simulators
This seminar promotes PC based general purpose simulators
Prof. S. Ben-Yaakov , Control Design of PWM Converters [76]
Why Simulation
• Most control design methods apply graphical representations of transfer functions
• One can get the plots from analytical expressions or by simulation
• Simulation is the easiest way to get “A” (the small signal response of the power stage)
39
Prof. S. Ben-Yaakov , Control Design of PWM Converters [77]
Computer Simulation of Power Conversion Systems
Prof. S. Ben-Yaakov , Control Design of PWM Converters [78]
Desired Simulator’s Featuresfor Power Electronics Systems
• Convergence
• Physical models
• Small signal analysis
• Interfaces
• Run time
• Behavioral models• Statistical and optimization analysis
• Discrete domain simulation capabilities
40
Prof. S. Ben-Yaakov , Control Design of PWM Converters [79]
Some Popular Modern Simulators
SPICE Based (Berkeley)• PSPICE – MicroSim - Orcad - Cadence• ICAP/4 – Intusoft
• MICROCAP - Spectrum
Others• PSIM - Powersim• Simplorer -Ansoft• PLECS -Plexim
Power IC Models Library
• AEi – Design Automation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [80]
PSPICE – The Physical Simulator
• Most popular
• SPICE based simulator (Berkley)• Used extensively for circuit simulation
• Extensive physical models libraries • Behavioral models (ABM)• AC analysis• Statistical analysis• Optimization tool• Some PWM models • MATLAB/Simulink interface
41
Prof. S. Ben-Yaakov , Control Design of PWM Converters [81]
Working with PSPICE
Prof. S. Ben-Yaakov , Control Design of PWM Converters [82]
PSPICE Convergence Problems
• Very common in switched circuits simulation
42
Prof. S. Ben-Yaakov , Control Design of PWM Converters [83]
AEi Power IC Library
• PWM controllers are not included in PSPICE libraries• AEi’s library supports Power Electronics
150 SPICE Models for Popular Power ICs
Regulators, Controllers, Switchers
FET Drivers
Support for Capture and Schematics
Symbols
Example Applications schematics/simulations
Documentation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [84]
PSIM -The Switching Circuit Simulator
• Disregards switching instances• Fast and effective time domain algorithm • Constant time step approach • Transient (time domain) based AC analysis
• User friendly intuitive interface• Generic models: passive, switchers, motors• Analog Behavior Models library• Simulink interface• Interface to magnetics program
• Prone to errors in simulation results• Simple output graphics utility
43
Prof. S. Ben-Yaakov , Control Design of PWM Converters [85]
PSIM AC Model
Excitationsource
• Multiple time-domain runs are used to obtain AC response
Prof. S. Ben-Yaakov , Control Design of PWM Converters [86]
PLECS – The MATLAB Plug-In
• Power tool-kit for SIMULINK • Allows the simulation of power stage as integrated
part of MATLAB (SIMULINK) simulation without introducing extra delays
• Ideal for investigating digital control loops in power systems
• Only generic models• Simulink interface for both schematic and
graphics
44
Prof. S. Ben-Yaakov , Control Design of PWM Converters [87]
V_dc
V: 300
I IIMutual
Ind. 2
V Vm2
D
4MOSFET1
R3
R: 10e3
C2
C: 10e-9
Ground1
GateOut1
5
Gate
1
C1
C: 22e-6
D1
R1
R: 23Vout
1VVm1
Ground
AAm2
I_L2
3Llkg
AAm1
I_L1
2
D2
PLECS Circuit
PLECS Circuit as a Simulink Block
num(s)
s+2.564e5
Transfer Fcn
Secondary
Current
m s
Sawtooth PWM
Saturation1
Saturation
Primary
Current
Output
Voltage
-K-
Gain Drain
Voltage
0.724 Constant1
5 Constant
Gate
Vout
I_L1
I_L2
D
GateOut1
PLECS
Circui t
Circui t
Prof. S. Ben-Yaakov , Control Design of PWM Converters [88]
PSPICE cycle-by-cycle model
• Uses physical level models of “real” devices
Vin
V5
5Vdc
0
C5
10n
R11
10k
R12
1.2k
0
R6
20K
gate
eaout
C4
3.9n
OUT+OUT-
IN+IN-
E1
V(%IN+, %IN-)*100k
ETABLE(0,0) (15,15)
PWMSnubber
EA
K K1
COUPLING = 1K_Linear
L1 = L1
L2 = L2
1
2
L1
0.5m
secondary
0
0
V4
300Vdc
C2
22u
IC = 48R2
23
0
1
2
L2
0.5m
OUT+OUT-
IN+IN-
E2
V(%IN+, %IN-)*100k
ETABLE
(4.36,4.36) (9.2,9.2)
out
R3
10k
R7
10m
C3
10n
M3
IRF830
Vref
D3
MBR360
R9
10k
D5
MUR160
V6
4.3105Vdc
R13
80
V7
TD = 0
TF = 0.0009u
PW = 0.1n
PER = 10u
V1 = 0
TR = 9.999u
V2 = 5
0
Vd
1
2
L3
0.002m
R14
10
45
Prof. S. Ben-Yaakov , Control Design of PWM Converters [89]
PSIM Flyback cycle-by-cycle model(Time Domain)
DemoReal time: 3 ms
Prof. S. Ben-Yaakov , Control Design of PWM Converters [90]
PSIM DCM cycle-by-cycle simulation results
Rload=220Ω
• Textbook waveforms
46
Prof. S. Ben-Yaakov , Control Design of PWM Converters [91]
PSPICE vs. PSIM Flybackcycle-by-cycle simulation results
Prof. S. Ben-Yaakov , Control Design of PWM Converters [92]
PSPICE vs. PSIM Flybackcycle-by-cycle simulation results
Time, [ms]
2.96 2.982.95 3.002.97 2.99
Secondary current
Primary current
-2.0A
0A
2.0A
4.0A
-2.0A
0A
2.0A
4.0A
47.5V
47.7V
47.8V
47.6V
Output voltage
PSPICE PSIM
47
Prof. S. Ben-Yaakov , Control Design of PWM Converters [93]
Small Signal (AC) Analysis(Needed for Control Design)
Two Alternatives:
1. Full switched circuit: Injection of a sinusoidal perturbations
PSPICE manuallyPSIM automatic
2. Average Model
PSPICE AC analysis(linearization by simulator)
PSIM automatic transient injection
Prof. S. Ben-Yaakov , Control Design of PWM Converters [94]
Small signal response by injection of sinusoidal perturbations ( time domain)
MOD
Io
RL
CD
LS Vo
ESR
vo
io
D d
VD
vex
Transient simulation – any simulator
48
Prof. S. Ben-Yaakov , Control Design of PWM Converters [95]
PSIM Realization (Buck)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [96]
-20
-10
0
10
20
30
40
50
60
100 1K 10K
Gain
, [d
B]
PSPICEPSIM
40K
-250
-200
-150
-50
0
100 1K 10K 40K
Frequency, [Hz]
-100
PSPICEPSIM
Pha
se,
[deg]
Frequency, [Hz]
dB3V
20mV
257µS*1.5kHz*3600
Power-Stage small signal transfer functionBy injection of sinusoidal perturbation - PSIM & PSPICE
Time, [ms]
4.00 5.00 6.003.61 6.75-20
0
20
45.0
47.5
50.0
[mV
][V
]
Output voltage
Vpk-pk: 3V
Sinus excitation
Vpk-pk: 20mV
257µS
PSPICE
Boost
49
Prof. S. Ben-Yaakov , Control Design of PWM Converters [97]
The Behavioral ApproachAverage Model of Flyback - PSPICE
300.0V
outR3
0.001
47.99V
Duty cycle generator
0V
G1
I(L1)*V(doff)/n
GVALUE
OUT+OUT-
IN+IN-
d
47.99V
0V
C1
22u
in
E2
min(1-V(d),(2*Lmain*fs*I(L1)/(V(in)*V(d))-V(d)))
ETABLE
OUT+OUT-
IN+IN-
V5
0.01Vac
R4
10m
862.1mVdoff
0
PARAMETERS:
n = 1Vin = 300Vfs = 100kHzLmain = 0.5m
E1
Vin*V(d)-V(out)*V(doff)/n
EVALUE
OUT+OUT-
IN+IN-
47.99VL1
Lmain
1
2
0
V2
0.1379
0
137.9mV
V4
Vin
R2
23
• Average models can be applied to obtain frequency response – AC analysis (to be discussed later)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [98]
Signal injection versus Average model
Signal injection
Applies the switching schematics as is
Takes a long time to run
Noisy at high frequency
Average model
Runs very fast
Need to built a behavioral equivalent
Some topologies/controllers are not easy to convert to average circuits
50
Prof. S. Ben-Yaakov , Control Design of PWM Converters [99]
PSIM vs. PSPICE AC Comparison
100 1k 10kG
ain
, [d
B]
100k
100 1k 10k 100k
Frequency, [Hz]
Phase,
[de
g]
Frequency, [Hz]
-30-20
-10
0
10
20
30
40
50
0
-50
-100
-150
-200
-250
PSIMPSPICE
PSIMPSPICE
doutv
Prof. S. Ben-Yaakov , Control Design of PWM Converters [100]
Applications:• DC transfer functions • Transient (large signal, time domain) phenomena • Small signal (AC, time domain) transfer functions
Not applicable to:• Switching details, rise and fall times, spikes• Device characteristics and losses • Subharmonic oscillations
• Conduction losses can be accounted for• HF ripple can be estimated
Behavioral average modeling of switch mode systems
51
Prof. S. Ben-Yaakov , Control Design of PWM Converters [101]
Identify the switched assembly Replace the switching part by a continuous
behavioral (analog) equivalent circuit Leave the analog part as-is Run the combined circuit on a general purpose
simulator
The modeling methodology presented in this seminar is highly ‘portable’, independent of simulator
Demonstration by PSPICE Ver. 10.5 (Demo Edition)
7. Average ModelsThe Switched Inductor Model (SIM) Strategy
Prof. S. Ben-Yaakov , Control Design of PWM Converters [102]
Modulator ControlEVD
inV
AssemblySwitched
oV
++++−−−−
• The problematic part : Switched Assembly• Rest of the circuit continuous - SPICE compatible• The objective : translate the Switched Assembly into an equivalent circuit which is SPICE compatible
The switched inductor model
52
Prof. S. Ben-Yaakov , Control Design of PWM Converters [103]
Average Simulation of PWM Converters
++++−−−−
++++−−−−
++++−−−−
ontb d c
a
fC LoadR
outV
inVLI
bI CI
outV outV
LoadR LoadRfCfC
L
a d c
b
CILIbI
inVinV
b ont L
bI LI
CI
d
c
L
Buck Boost
BoostBuck −−−−
Prof. S. Ben-Yaakov , Control Design of PWM Converters [104]
TON - switch conduction time TOFF - diode conduction timeTDCM - no current time (in DCM)
L ab
c
b ONT
DCMTOFFT
L
c
a
Possible switch modes
53
Prof. S. Ben-Yaakov , Control Design of PWM Converters [105]
The Switched Inductor Model (SIM) (CCM)
The concept of average signals
t
t
t
aI
bI
cI
bI
aI
cI
b bI
cIcaI a L ONT
OFFT
Prof. S. Ben-Yaakov , Control Design of PWM Converters [106]
b bI
cIcaI a L ONT
OFFT
b
caI a
bI
cI?
⇓⇓⇓⇓
Objective : To replace the switched part by a continuous network
54
Prof. S. Ben-Yaakov , Control Design of PWM Converters [107]
b
c
a L ONTaI
bI
cILI
Average current
IbI
LI
bI
ONT
ST
onLS
ONLb DI
T
TII ========
S
ONon
T
TD =
offLS
OFFLc DI
T
TII ========
La II ====
Similarly :
Prof. S. Ben-Yaakov , Control Design of PWM Converters [108]
b
c
bI
cI
a aG
bG
cG
aI
Toward a continuous model
b
caLa II ====
onLb DII ⋅⋅⋅⋅====
offLc DII ⋅⋅⋅⋅====
⇓⇓⇓⇓Ga, Gb,Cc - currentdependent sources
offLc
onLb
La
DIG
DIG
IG
⋅⋅⋅⋅≡≡≡≡
⋅⋅⋅⋅≡≡≡≡
≡≡≡≡
55
Prof. S. Ben-Yaakov , Control Design of PWM Converters [109]
LV
LIV
t
LV
LV
LI
LI
valueAverageXX
L
V
dt
Id
L
V
dt
dI LL
========
====⇒⇒⇒⇒====
IL derivation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [110]
LV (((( ))))b,aV
(((( ))))c,aV
onT offT
sT
offon
S
offonL
D)c,a(VD)b,a(V
T
T)c,a(VT)b,a(VV
⋅⋅⋅⋅++++⋅⋅⋅⋅====
====⋅⋅⋅⋅++++⋅⋅⋅⋅
====
b
c
a L
)b,a(V
)c,a(V
Average inductor voltage
56
Prof. S. Ben-Yaakov , Control Design of PWM Converters [111]
The Generalized Switched Inductor Model (GSIM) Model
b
c
aaG
bG
cG
offonL
offLc
onLb
La
D)c,a(VD)b,a(VV
DIG
DIG
IG
⋅⋅⋅⋅++++⋅⋅⋅⋅====
⋅⋅⋅⋅====
⋅⋅⋅⋅====
====
b
ca
LL
Lr
LI
LE
Topology independent !
Prof. S. Ben-Yaakov , Control Design of PWM Converters [112]
Example: Implementation in Buck Topology
1. The formal approach
off0onin0L
offconba
D]0V[D]VV[E
D)L(IGD)L(IG)L(IG
⋅⋅⋅⋅−−−−++++⋅⋅⋅⋅−−−−====
⋅⋅⋅⋅====⋅⋅⋅⋅========
b
c
a
aGbG
cG
oRoC
inV
oV
LELI
L
)b,a(V
)c,a(VLr
S L
oC oRinV
ab
c
57
Prof. S. Ben-Yaakov , Control Design of PWM Converters [113]
Implementation in Buck Topology
2. The intuitive approach - by inspection
L
oCoRinV
oV
LI
inE
bG
S L
oC oRinV D
oV
Loin
onLb
oninin
VVE
DIG
DVE
→→→→++++
⋅⋅⋅⋅====
⋅⋅⋅⋅====
Polarity: (voltage and current sources) selected by inspection
Prof. S. Ben-Yaakov , Control Design of PWM Converters [114]
Boost
S
L
oC oRinV
DoV
L
oCoRinV
oV
ooff VD ⋅⋅⋅⋅
offL DI ⋅⋅⋅⋅
• Emulate average voltage on inductor• Create IL dependent current sources
58
Prof. S. Ben-Yaakov , Control Design of PWM Converters [115]
Making the model SPICE compatible
lL
IL and DON are time dependent Variables IL(t), DON (t)
DON is not an electrical variable
onDLIbG
Prof. S. Ben-Yaakov , Control Design of PWM Converters [116]
⇓⇓⇓⇓In SPICE environment
Don is coded into voltage
++++−−−−
Source
onD"D":nodeofName on
)L(I)D(V lon ∗∗∗∗ lL
Gvalue
59
Prof. S. Ben-Yaakov , Control Design of PWM Converters [117]
DC (steady state points) - as is
TRAN (time domain) - as is
AC ( small signal) - as is
• Linearization is carried out by simulator !
Running SPICE simulation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [118]
Discontinuous Model (DCM)
b
cLIa L ONT
OFFT
onT offT
offT
sT
t
pkILI
ons
Nsoff
onsoff
D1T
TT'D
TT'T
−−−−====−−−−
====
−−−−====
Doff ≠≠≠≠ 1 - Don
60
Prof. S. Ben-Yaakov , Control Design of PWM Converters [119]
The combined DCM / CCM model
b
ca
L
b
c
aaG
bG
cG
L
Lr
LI
−−=
+=
+≡
+≡
≡
onon
sLonoff
offonL
offon
offLc
offon
onLb
La
DD)b,a(V
LfI2),D1(minD
D)c,a(VD)b,a(VV
DD
DIG
DD
DIG
IG
Prof. S. Ben-Yaakov , Control Design of PWM Converters [120]
Synchronous Power Stages(diode replaced by switch)
Only two stated for switched inductor:
open and closed
No third state as in DCM
Use CCM model
61
Prof. S. Ben-Yaakov , Control Design of PWM Converters [121]
LResrR
outC
oVoutL
1D
MODPWM
onDV
exV
D
inV
pulsinV
Buck ConverterExample:
Prof. S. Ben-Yaakov , Control Design of PWM Converters [122]
File: Buck_cy_by_cy.OPJ
Lout
Lout
a
PARAMETERS:
VIN = 10v
out
in RLoad
RLoad
Rinductor
Rinductor
PARAMETERS:
LOUT = 75uCOUT = 220uRLOAD = 10
Vin
Vin+
-
CoutCout
PARAMETERS:FS = 100kTS = 1/fs
0
buck_cy_by_cy.sch
Dbreak
D1
Cycle by Cycle simulationof PWM Buck converter
+ -
+ -
Sbreak-XS1
VD
PW = 5u
PER = 10u
+-
Resr
Resr
PARAMETERS:RESR = 0.07RINDUCTOR = 0.1
62
Prof. S. Ben-Yaakov , Control Design of PWM Converters [123]
Time
0s 2.0ms 4.0ms 6.0ms
-I(Lout)
-10A
0A
10A
V(out)
0V
10V
Power Start-Up at Constant Don
DCM to CCM
Prof. S. Ben-Yaakov , Control Design of PWM Converters [124]
Time
1.625ms 1.750ms1.535ms 1.862ms
-I(Lout)
0A
250mA
500mA
Zooming up
63
Prof. S. Ben-Yaakov , Control Design of PWM Converters [125]
L
oCoR
inV
oVLr
cr
dsonR
b c
a
SIM
inV
dsonR b
c
aG
bG
cG
oC
oRcr
a
Lr
L
LI
LE
Average model
Prof. S. Ben-Yaakov , Control Design of PWM Converters [126]
File: Buck.OPJ
PARAMETERS:
FS = 100kTS = 1/fs
Average simulation by SIM-Model of PWM Buck converter
PARAMETERS:VIN = 10vVDON = 0.5
PARAMETERS:
RESR = 0.07RINDUCTOR = 0.1
Rinductor
Rinductor
Vin
Vin+
-
Resr
Resr
EDoff
min(2*abs(I(Lout))*Lout/(Ts*(vin-V(a))*V(Don))-V(Don),1-V(Don))
etable
OUT+
OUT-
IN+
IN-
0
Gb
V(Don)*I(Lout)/(V(Don)+V(Doff))
GVALUE
OUT+
OUT-
IN+
IN-
Vexcitation
1V
+-
buck.sch
NODESET= 5
+
VDon
VDon
+
-
Ga
I(Lout)
GVALUEOUT+
OUT-
IN+
IN-Gc
V(Doff)*I(Lout)/(V(Don)+V(Doff))
GVALUE
OUT+
OUT-
IN+
IN-
c
b
RLoad
RLoad
0
DoffDon
PARAMETERS:LOUT = 75uCOUT = 220uRLOAD = 10
EL
V(Don)*V(a,b)+V(Doff)*V(a,c)
EVALUE
OUT+
OUT-
IN+
IN-
Lout
LoutIC = 0
a
CoutCout
Dbreak
D1
b a
c
• Don coded into voltage • Doff for CCM/DCM
64
Prof. S. Ben-Yaakov , Control Design of PWM Converters [127]
Inductor
EL
V(Don)*V(a,b)+V(Doff)*V(a,c)
EVALUE
OUT+
OUT-
IN+
IN-
Lout
Lout
Rinductor
Rinductor
Prof. S. Ben-Yaakov , Control Design of PWM Converters [128]
Input side
0
b
Gb
V(Don)*I(Lout)/(V(Don)+V(Doff))
GVALUE
OUT+
OUT-
IN+
IN-
Gc
V(Doff)*I(Lout)/(V(Don)+V(Doff))
GVALUE
OUT+
OUT-
IN+
IN-Dbreak
D1
c
Vin
Vin+
-
65
Prof. S. Ben-Yaakov , Control Design of PWM Converters [129]
Output side
Resr
Resr
Ga
I(Lout)
GVALUE
OUT+
OUT-
IN+
IN-
a
RLoad
RLoad
NODESET= 5
+
CoutCout
Prof. S. Ben-Yaakov , Control Design of PWM Converters [130]
DC Sweep plus Parametric (on Rload)
66
Prof. S. Ben-Yaakov , Control Design of PWM Converters [131]
Sweeping Rload Constant Don
RLoad
1.0 10 100 1.0K
V(out)
4V
6V
8V
10V
CCM
DCM
Diode losses
Prof. S. Ben-Yaakov , Control Design of PWM Converters [132]
Transient Analysis –Power Turn-On
67
Prof. S. Ben-Yaakov , Control Design of PWM Converters [133]
Power Start-Up at Constant Don
Time
0s 2.0ms 4.0ms 6.0ms
-I(Lout)
0A
5A
10A
SEL>>
V(out)
0V
5V
10V
Prof. S. Ben-Yaakov , Control Design of PWM Converters [134]
Comparing Cycle-by-Cycle to Average Simulation
Time
1.625ms 1.750ms 1.875ms-I(Lout)
0A
400mA
-268mA
766mA
68
Prof. S. Ben-Yaakov , Control Design of PWM Converters [135]
AC AnalysisThe Real Strength of Average Simulation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [136]
• The circuit is linearized by simulator (elements, devices and expressions)
• Numerical linearization !e.g. a source f(x,y,z) is replaced by:
zZ
)Z,Y,X(f)ZZ,Y,X(f
yY
)Z,Y,X(f)Z,YY,X(f
xX
)Z,Y,X(f)Z,Y,XX(f
∆−∆+
+
∆−∆+
+
∆−∆+
• Transparent to user
Linearization
69
Prof. S. Ben-Yaakov , Control Design of PWM Converters [137]
PSpice simulations examples
Buck Average Buck Cy by Cy
Prof. S. Ben-Yaakov , Control Design of PWM Converters [138]
LResrR
outC
oVmainL
D
1D
MODPWM
onDV
exV
inV
pulsinV
Boost
a c
b
70
Prof. S. Ben-Yaakov , Control Design of PWM Converters [139]
1 Dbreak
Dmain
RswRsw
PARAMETERS:
VIN_DC = 10vVDON = 0.5
Don
Gb
V(Don)*I(Lmain)/(V(Don)+V(Doff))
GVALUEOUT+
OUT-
IN+
IN-
Lmain
Lmain
0
PARAMETERS:
FS = 100kTS = 1/fs
Vexcitation
1V
+-
a b
Resr
Resr
Rinductor
Rinductor
EDoff
min(2*I(Lmain)*Lmain/(Ts*v(a,b)*V(Don))-V(Don),1-V(Don))
etable
OUT+
OUT-
IN+
IN-
CoutCout
0
c
Gc
V(Doff)*I(Lmain)/(V(Don)+V(Doff))
GVALUE
OUT+
OUT-
IN+
IN-Vin_DC
Vin_DC
+
-
RLoad
RLoad
out
Boost.sch
PARAMETERS:
LMAIN = 75uCOUT = 220uRLOAD = 10
Ga
I(Lmain)GVALUE
OUT+
OUT-
IN+
IN-
PARAMETERS:
RESR = 0.07RINDUCTOR = 0.1RSW = 0.1
Vin_pulse
+-
Doff
EL
(V(Don)*V(a,b)+V(Doff)*V(a,c))
EVALUE
OUT+
OUT-
IN+
IN-
SIM-Model under CCM & DCM for PWM Boost converter
VDon
VDon
+
-
Boost Simulation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [140]
Frequency
1.0Hz 100Hz 10KHz 1.0MHzP(V(out))
-400d
-200d
0d
SEL>>
V(out)
1.0V
10mV
100V
ESR of Cout
100mΩ10 mΩ1mΩ
RLoad= 10Ω
71
Prof. S. Ben-Yaakov , Control Design of PWM Converters [141]
RLoad = 1000Ohm
Frequency
1.0Hz 1.0KHz 1.0MHzP(V(out))
-100d
0d
SEL>>
V(out)
1.0VDCM
DCM
Prof. S. Ben-Yaakov , Control Design of PWM Converters [142]
PSpice simulation example
Boost simulation
72
Prof. S. Ben-Yaakov , Control Design of PWM Converters [143]
POWER STAGE
Duty Cycle 'D' Generator
I L
Vref
D
Error Ampl.
V outVin
Power Input
VE
ref
ONVL
• General representation of a switch mode DC-DC converter
Modulators – The Duty Cycle Generators
Prof. S. Ben-Yaakov , Control Design of PWM Converters [144]
PWM MODULATOR - Voltage Mode
MP
MEM
e VV
VVmode)(voltageK
V
D
−−−−−−−−
========
MP
e
e VV
v
V
d
⋅⋅⋅⋅====
73
Prof. S. Ben-Yaakov , Control Design of PWM Converters [145]
Coding
ModulatorControl
D
inV
oV
++++−−−−
MK
Mp
MEM
VV
VV)emodvoltage(K
−−−−−−−−
====
D coded into voltage
1V0 D ≤≤≤≤≤≤≤≤
Prof. S. Ben-Yaakov , Control Design of PWM Converters [146]
Duty Cycle Limiter• Behavioral dependent source ETABLE
0.90.1
E1
V(%IN+, %IN-)
ETABLE
TABLE = (0.1,0.1) (0.9,0.9)
OUT+
OUT-
IN+
IN-
Out
In
0.9
0.1
74
Prof. S. Ben-Yaakov , Control Design of PWM Converters [147]
Average Current Mode
• VE is a function of Vo and IL• ‘Control’ is the original analog circuit• Same modulator as in voltage mode
ModulatorControl
EVD
inV
oV
++++−−−−
MK
Prof. S. Ben-Yaakov , Control Design of PWM Converters [148]
L=195 µ D
28v
++
+FF
+C=2000 µ
Rc=0.012 ΩRo=11.2 Ω
Rs
25mΩ
Vp=0.25v
+
+ 2.8v
Rf=72.2k ΩCf=0.23 µ
R2=2.5k Ω
R1
47.5Ω
3.25
Peak Current Mode Control
75
Prof. S. Ben-Yaakov , Control Design of PWM Converters [149]
Current Mode CCM
V(V)
KS = Current Loop Gain MC = Slope CompensationTS = Switching PeriodL = Inductance of main inductor|I(L)| = Average inductor current
++++
++++−−−−
====
L2
)b,a(VKSMCTS
)Doff(V)Don(V
)L(IKS)Ve(V
EDon
If your can write an expression, it can be modeled !
Prof. S. Ben-Yaakov , Control Design of PWM Converters [150]
File: CM-Boost.opj
Power stage
DCG - CM
Doff CCM/DCM
d_c vl
0V+
-
SIM-Model under CCM & DCM for Current-Mode PWM Boost converter
Edoff
min(abs((2*i(vl)*lin/(ts*v(don)*(v(in)-v(sw))))-v(don)),1-v(don))
etable
OUT+
OUT-
IN+
IN-
Red_c
1k
PARAMETERS:KS = 81.25mTS = 40uMC = 6250
PARAMETERS:RESR = 0.012COUT = 2mVIN_DC = 28
PARAMETERS:
RSON = 1mRSW = rson+rsenRL = 11.2
out
csw
V13
1.09
+
-Redoff
1k
Gdoff
v(doff)*i(vl)/(V(Don)+V(Doff))
gvalue
OUT+
OUT-
IN+
IN-
doff
rind
1mresr
resr
Gsw
i(vl)*v(d_c)
gvalue
OUT+
OUT-
IN+
IN-
RL
RL
PARAMETERS:LIN = 195uRSEN = 0.025FS = 1/ts
Vexatation 1
+ -
Vin_DC
Vin_DC
+
-
rsw
rsw
Gd
i(vl)*v(d_c)
gvalue
OUT+
OUT-
IN+
IN-
cout
cout
Schematic file name: CM-Boost\CM-Boost.sch
Edon
fs*(v(Verror)-ks*i(vl)*v(d_c))/(mc+ks*(v(in)-v(sw))/(2*lin))
etable
OUT+
OUT-
IN+
IN-
Dbreak
d1
a
Verror
Vin_pulse
+-ELs
v(sw)*v(don)+(v(c)+v(out))*v(doff)+v(in)*(1-v(don)-v(doff))
evalue
OUT+
OUT-
IN+
IN-
lin
lin
Redon1k
don
Ed_c
1/(v(don)+v(doff))
etable
OUT+
OUT-
IN+
IN-
in
76
Prof. S. Ben-Yaakov , Control Design of PWM Converters [151]
Inductor
lin
lin
in
ELs
v(sw)*v(don)+(v(c)+v(out))*v(doff)+v(in)*(1-v(don)-v(doff))
evalue
OUT+
OUT-
IN+
IN-
0V
Vin_pulse
+-
rind
1m
Vin_DC
Vin_DC
+
-
vl
0V+
-
a
27.99V
Prof. S. Ben-Yaakov , Control Design of PWM Converters [152]
Duty Cycle Generator
Edon
fs*(v(Verror)-ks*i(vl)*v(d_c))/(mc+ks*(v(in)-v(sw))/(2*lin))
etable
OUT+
OUT-
IN+
IN-
Redoff
1k
Redon
1k
don
0V
Edoff
min(abs((2*i(vl)*lin/(ts*v(don)*(v(in)-v(sw))))-v(don)),1-v(don))
etable
OUT+
OUT-
IN+
IN-
doff
77
Prof. S. Ben-Yaakov , Control Design of PWM Converters [153]
V(out)/V(Don) as normalV(out)/V(Verror) lower order
Frequency
100Hz 10KHz 1.0MHz10Hzp(V(OUT)) p(V(OUT)/ V(DON))
-400d
-200d
0ddb(V(OUT)) db(V(OUT)/ V(DON))
-50
0
50
SEL>>
d
vo
d
vo
e
o
v
v
e
o
v
v
Prof. S. Ben-Yaakov , Control Design of PWM Converters [154]
PSpice simulation example
CM-Boost
78
Prof. S. Ben-Yaakov , Control Design of PWM Converters [155]
Models of IC Controllers
Vendors do not supply simulation models of IC controllers
Large signal controllers’ models are supplied with some simulators (e.g. PSIM)
Average models ( applicable for small signal analysis) are available from AEi
It is easy to build your own behavioral average models (for control)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [156]
The Power Stage small-signal response
A prerequisite for control design
Can be obtained by analytical derivations/expressions
By Simulation
– On switched model (cycle by Cycle)
– Average models
79
Prof. S. Ben-Yaakov , Control Design of PWM Converters [157]
Close loopBandwith f
o
Break frequency notimportant,
as low as possible
|A|ββ/1
AOL
Make as large as possibleAβ
1. Find A(f) of Power stage
2. Decide on f03. Choose type of
compensating network
4. Calculate feedback network
Feedback Loop Design of PWM Converters
Prof. S. Ben-Yaakov , Control Design of PWM Converters [158]
The Relationship to PID
( ) =⋅++== dI
pe
compKs
s
KK
v
vsH
( ) ( )s
ωsωs
K
K
s
KsKsK z2z1
I
dIp2
d +⋅+=
+⋅+⋅=
( )d
Id
2
ppz1,2
2K
K4KKKω
−±−=
80
Prof. S. Ben-Yaakov , Control Design of PWM Converters [159]
The Relationship to PID
[ ]dB
V
V
e
comp
1f 2f
( ) ( )s
ωsωs
K
K
s
KsKsK z2z1
I
dIp2
d +⋅+=
+⋅+⋅=
Prof. S. Ben-Yaakov , Control Design of PWM Converters [160]
The Relationship to PID
[ ]dB
V
V
e
comp1f 2f
B
1
81
Prof. S. Ben-Yaakov , Control Design of PWM Converters [161]
The Relationship to PID
[[[[ ]]]]dB
d
Vo
dec
dB40-
dec
dB20-
Prof. S. Ben-Yaakov , Control Design of PWM Converters [162]
BW Limitations(of LG, crossing of A and B)
PWM is a smapled data sysyem .
Nyquist sampling theorem applies
Cross over frequency fo (A, B, LG ) < fs/2
In practice fo < 10 fs/2
82
Prof. S. Ben-Yaakov , Control Design of PWM Converters [163]
8. Analog compensator networks
Prof. S. Ben-Yaakov , Control Design of PWM Converters [164]
ffp
RC2
1f
π=
in
fo
R
RA =
Possible phase compensation schemesLag (A)
83
Prof. S. Ben-Yaakov , Control Design of PWM Converters [165]
Lag (B)
Frequency
100Hz 10KHz 1.0MHz10Hz
p(-V(out1))
-100d
-50d
0d
SEL>>
db(V(out1))
-40
0
40
E1
V(%IN+, %IN-)*1E6EVALUE
OUT+OUT-
IN+IN-
R1
1k
0V
C1
10n
R2
100k
V11Vac
0Vdc
0V
0V
out1
Prof. S. Ben-Yaakov , Control Design of PWM Converters [166]
in
f2
ffL
OLo
R
RA
RC2
1f
.)ampl(AA
=
π=
=
f
β1
f
decdb20
β
f1
f2
A0
A2
Lag – Lead (B)
84
Prof. S. Ben-Yaakov , Control Design of PWM Converters [167]
Lag-Lead (B)
Frequency
100Hz 10KHz 1.0MHz10Hz
p(-V(out2))
-100d
-50d
0d
SEL>>
db(V(out2))
0
50
100
E3
V(%IN+, %IN-)*1E6 EVALUE
OUT+OUT-
IN+IN-
C2
10n
R9
1g0V
out2
0V
R3
10k
0V
R4
1kV21Vac
0Vdc
Prof. S. Ben-Yaakov , Control Design of PWM Converters [168]
Double zero compensation scheme
21
32
RR
CC
<
>β
β
1
dec
dB20−
48476
43421
48476
43421
48476
43421
48476
43421 33111223 CR
1
CR
1
CR
1
CR
1
⋅<
⋅<
⋅<
⋅ ππππ 2222
32CRf 2
1
⋅π
OLA
2
3
R
R
32CRf 2
1
⋅π
1
3
R
R
85
Prof. S. Ben-Yaakov , Control Design of PWM Converters [169]
Double Zero (B)
Frequency
100Hz 10KHz 1.0MHz10Hz
p(-V(out3))
-100d
0d
100d
SEL>>
db(V(out3))
0
20
40
C5
10n
C3
10n
0V
0
R7
100k
V31Vac
0Vdc
0V
R81g
out3R5
1k
E2
V(%IN+, %IN-)*1E6EVALUE
OUT+OUT-
IN+IN-R6
100k
C4
100p
0V
Prof. S. Ben-Yaakov , Control Design of PWM Converters [170]
C2
1n
V2
2.5R10
1k
C3
10n
R4
22k
R9
1k
C4
100p
0
E2
V(%IN+, %IN-)*1000k
EVALUE
OUT+OUT-
IN+IN- Don
out1R8
100k
Double Zero- Alternative
86
Prof. S. Ben-Yaakov , Control Design of PWM Converters [171]
-20db/drc
-40db/dec
Rate of closure
20 db/dec
A
1/β
Phase advance by compensator
Application of Double Zero Compensator
Prof. S. Ben-Yaakov , Control Design of PWM Converters [172]
Voltage Mode Control Compensator Design Example
VM Regulator
87
Prof. S. Ben-Yaakov , Control Design of PWM Converters [173]
Obtaining the Loop Gain by Simulation
εεεεSinS
fS
+
-
outSPSH
K
εεεεS
SGL f=
Prof. S. Ben-Yaakov , Control Design of PWM Converters [174]
Loop Gain by Simulation
outSPS
K
εεεεSinS
fS
+
-
COMP+
H
+
εεεε′′′′S
fS′′′′SS
εεεεS
SGL f
′′
=
88
Prof. S. Ben-Yaakov , Control Design of PWM Converters [175]
εεεεSinS +
-
outSPSH
Kεεεε′′′′S
fS ′′′′
SS
+
+fS
εεεε′′′′′′′′
====S
SGL f
Loop Gain by Simulation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [176]
LG(f) = V1/V2
Loop-GainGetting Loop-Gain under closed loop response A(f)*B(f)
Vin=0
89
Prof. S. Ben-Yaakov , Control Design of PWM Converters [177]
The relevant analysis is .AC
• Locate the AC source at the output of a low impedance device (could be real or behavioral)
• Set the AC value to any value (1 V is fine)
• Make sure that there are no other AC sources in the system
• Check bias point (.OUT file)
• Remember that the classical stability criteria take into account the phase reversal (1800)
Rules for Getting Loop-Gain by Simulation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [178]
PSpice Simulation
VM Regulator
90
Prof. S. Ben-Yaakov , Control Design of PWM Converters [179]
PSIM Demonstration
Large signal Small signal
Schematic
Probe
Schematic
Probe
LoopGain
Probe
TF
Prof. S. Ben-Yaakov , Control Design of PWM Converters [180]
Peak and Average Current Mode
MOD
Vo
VrefV
e
D
inner loop
outer loop
I L
IL/Ve flat
Two step design: inner loop and outer loop
91
Prof. S. Ben-Yaakov , Control Design of PWM Converters [181]
The advantages of current feedback(PCM or ACM)
e
o
V
V
decdb40−
decdb20−
Typical power stage VM
e
o
V
V
decdb40−
decdb20−
Same power stage (outer loop) with CM
With closed inner-loop
Prof. S. Ben-Yaakov , Control Design of PWM Converters [182]
Vac = 1V ; Vc =Constant (operating point) ; KS= 1/20
µ Ω
Inner Loop designAverage Current Mode
92
Prof. S. Ben-Yaakov , Control Design of PWM Converters [183]
Don
0
0
0
Ve
in
Doff
E4
V(Ve)
ETABLE
OUT+OUT-
IN+IN-
V1
100Vdc
G1
V(Doff)*I(L1)/(V(Don)+V(Doff))
GVALUE
OUT+OUT-
IN+IN-
InductorSection
out
Ro
Ro
L1
Lin
0
0
Co
Co
OutputSection
E5
min(2*i(L1)*Lin/(Ts*V(Don)*V(in)+0.1m)-V(Don),1-V(Don))
ETABLE
OUT+OUT-
IN+IN-
0
R1
0.1
V31Vac
DC = 0.74Vdc
Duty Cycle Generator
0
Resr
.02
PARAMETERS:Lin = 1mCo = 450uTs = 10uRo = 610
E1
V(Doff)*V(out)+V(in)*(1-V(Don)-V(Doff))
EVALUE
OUT+OUT-
IN+IN-
Prof. S. Ben-Yaakov , Control Design of PWM Converters [184]
Frequency
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
DB(I(L1)/(V(Ve)))
-40
0
40
80
(13.154K,13.335)
1/β
F=13kHz; Gain= -13.3db=0.22
I(L1)/V(Ve)
The response for inner loop design
93
Prof. S. Ben-Yaakov , Control Design of PWM Converters [185]
V2
1Vac0Vdc
PARAMETERS:Lin = 1mCo = 450uTs = 10uRo = 610
ks
Error Amplifier
Rf
68k
Rin
15k
Ve
Cf
820p
00
0
E2
I(L1)/20EVALUE
OUT+OUT-
IN+IN-
E3
1E6*V(%IN+, %IN-)EVALUE
OUT+OUT-
IN+IN-
Vc
Cfh 62p
V30Vac
DC = 0.12Vdc
0
Ve_out
• The error amplifier (For KS =1/20)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [186]
Frequency
100Hz 10KHz 1.0MHz10Hz
DB( I(L1)/V(Ve)) -DB( V(VE_OUT)/I(L1))
-40
0
40
80
(2.9126K,10.624)
(12.761K,13.564)
1/β
I(L1)/V(Ve)
94
Prof. S. Ben-Yaakov , Control Design of PWM Converters [187]
Frequency
100Hz 10KHz 1.0MHz10Hz
DB( I(L1)/V(Vc))
-40
0
40
I(L1)/V(Vc)
Closed inner Loop
Prof. S. Ben-Yaakov , Control Design of PWM Converters [188]
Vac = 1V ; Vc =Constant (operating point) ; KS= 1/20
KM
Cfh
Cf
Rf
VE
D
CO
RO
D
Rin
Vin L
1m H
VC
470 Fµ 160Ω
VE_OUT
VO
95
Prof. S. Ben-Yaakov , Control Design of PWM Converters [189]
Frequency
100Hz 10KHz 1.0MHz10Hz
p(V(VE_OUT)/V(Ve))
0d
90d
180d
SEL>>
(12.467K,60.107)
DB(V(VE_OUT)/V(Ve))
-100
0
100
(12.467K,72.211m)
Phase margin 600
LoopGain
Prof. S. Ben-Yaakov , Control Design of PWM Converters [190]
R(-V(VE_OUT)/V(Ve))
-20K 0 20K 40K
IMG(-V(VE_OUT)/V(Ve))
-40K
-20K
0
20K
Nyquist Plot
Imaginary(LG) versus Real(LG)
96
Prof. S. Ben-Yaakov , Control Design of PWM Converters [191]
p(-V(VE_OUT)/V(Ve))
-200d -150d -100d -50d -0d
db(V(VE_OUT)/V(Ve))
-100
0
100
Phase margin
Nichols Plot
|LG| versus Phase(LG)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [192]
Frequency
100Hz 10KHz 1.0MHz10Hz
DB( I(L1)/V(Vc))
-40
0
40
I(L1)/V(Vc)
Closed Inner Loop(Tracing)
97
Prof. S. Ben-Yaakov , Control Design of PWM Converters [193]
• Toward Power factor Correction (open loop)
0InductorSection
R1
0.1
Abs(310*Sin(6.28*50*time))+0.01
in
L1
LinE1
V(Doff)*V(out)+V(in)*(1-V(Don)-V(Doff))
EVALUE
OUT+OUT-
IN+IN-
V2
1Vac
0Vdc
0
Cfh 62p
Cf
820pIC = -1v Ve_out
Rf
68k
ks
0
Ve
Rin
15k
E3
1E6*V(%IN+, %IN-)
EVALUE
OUT+OUT-
IN+IN-
ErrorAmplifier
Vc
PARAMETERS:Lin = 1mCo = 450uTs = 10uRo = 610
Abs(2.4*Sin(6.28*50*time)/20)+0.01
0
E2
I(L1)/20
EVALUE
OUT+OUT-
IN+IN-
Rect. line
Closed Inner Loop
Prof. S. Ben-Yaakov , Control Design of PWM Converters [194]
Time
10ms 20ms 30ms 40ms 50ms
V(Doff)+ V(Don)
0V
1.0V
SEL>>
V(Don)
0V
0.5V
1.0V
I(L1)
-4.0A
0A
4.0A
In CCM: Don+Doff = 1
Don +Doff
I(L1)
Don
Transient Simulation -CCM
98
Prof. S. Ben-Yaakov , Control Design of PWM Converters [195]
Time
10ms 20ms 30ms 40ms 50ms
V(Doff)+ V(Don)
0V
1.0V
SEL>>
V(Don)
0V
0.5V
1.0V
I(L1)
-4.0A
0A
4.0A
After changing Lm to 300µH
Don +Doff
I(L1)
Don
Transient Simulation - CCM/DCM
Prof. S. Ben-Yaakov , Control Design of PWM Converters [196]
Three Loops Feedback PFC System(Conventional CCM)
Lin Dout
Cout Rload
+-
RS
+-
RefM
RECTIFIER
R1
R2
R3
R4
AC PWM
99
Prof. S. Ben-Yaakov , Control Design of PWM Converters [197]
-+
Lbst
E G
POWER STAGE
Li (t)
t
AC in
+
_ cpC
Rs
RczRci
Rm
Eca-+
C. ERR. AMP
czC
Gm
Vout
R0 0C
vfC
VrefEva
Rvf
Rvi
+
_
V. ERR. AMP
-+
Rvd
Vout
Rff3
Rff2
C2ff
C1ff
Rff1
FF. LPF
AC in
PWM
-+
Eff ffR
FILTER & LOAD
SQR-DIV-MUL
f1f
rec
ret
swout
vaout
caout
van
vap
D
line
lineret
sw
cap
caipci
sw
Vline
UC3854 Based Average Model
Prof. S. Ben-Yaakov , Control Design of PWM Converters [198]
CCM - Based on UC3854
out
rec
vapEca
1E6*V(%IN+, %IN-)
EvalueOUT+
OUT-
IN+
IN-
line
Rs
Rs
R18 2*Ro
Racl
Rac
PARAMETERS:
RO = 610CO = 450uFTS = 10uF
Vrms = 230V
caout
sw
Rcz
24k
Riv
1MegVref 7.5V+
-
Rci4k
Ccz
620p
Cff10.1u
Rvd10k
Ccp
62p
E6
(V(caout)-1.1)/5.4
etable
OUT+
OUT-
IN+
IN-
Gm
I(V_Iac)*(V(vaout)-1)/(pwr(V(f),2))
Gvalue
OUT+
OUT-
IN+
IN-
Esw
V(Doff)*V(out)+V(rec)*(1-V(Don)-V(Doff))Evalue
OUT+
OUT-
IN+
IN-
out
PARAMETERS:RS = 0.25RAC = 910kLin = 1m
Rm4k
G3
I(L1)*V(Line)/abs(v(line))
gvalue
OUT+
OUT-
IN+
IN-
f1
CoCo
IC = 390
V1
+-
rec
Cvf 47n
f
Rvi511k
V4
+-
Rff3
20k
Eva
1000*V(%IN+, %IN-)
Evalue
OUT+
OUT-
IN+
IN-
Rff2
91k
RoRo*2
EDoff
min(2*I(L1)*Lin/(Ts*v(rec)*V(Don)+0.1m)-V(Don),1-V(Don))
Etable
OUT+
OUT-
IN+
IN-
Doff
Gsw
V(Doff)*I(L1)/(V(Don)+V(Doff))
Gvalue
OUT+
OUT-
IN+
IN-
V_Iin
0V
+
-
cai
cap
E1
abs(V(line))
Evalue
OUT+
OUT-
IN+
IN-
ret
van
Don
V_Iac
0V
+
-
Rff1
910k
Rvf 180k
Cff2
0.5u
L1
Lin
vaout
Av_Model_UC.opj
100
Prof. S. Ben-Yaakov , Control Design of PWM Converters [199]
0V
out
Rvd10k
Cvf Fed_Cap
Rvi511k
vap
Eva
1000*V(%IN+, %IN-)
Evalue
OUT+
OUT-
IN+
IN-
Rvf 180k
R2
1Meg
7.492V7.500V
van7.614V
ba_out
V13
1Vac
0Vdc
Vref 7.5V+
-
0V
vaout7.614V
390.0V
R3
ESR
RoRo
0V
Gsw
V(Doff)*I(L1)/(V(Don)+V(Doff))
Gvalue
OUT+
OUT-
IN+
IN-
390.0V
CoCoIC = 390
out
0V
Voltage Control Loop
Output Section
Error Amplifier andCompensation Network
Excitation
Prof. S. Ben-Yaakov , Control Design of PWM Converters [200]
Time
400ms 450ms 500ms 550ms 600ms 650ms 700ms
i(V_Iin)
-10A
0A
10A
v(line)
-400V
0V
400V
SEL>>
Input Current
Input Voltage
Input Voltage Step Response: 115Vrms to 230Vrms
Pout=250W, Slew Rate=160V/mS
101
Prof. S. Ben-Yaakov , Control Design of PWM Converters [201]
Time
400ms 450ms 500ms 550ms 600ms 650ms 700ms
v(out)
375.0V
400.0V
412.5V
425.0V
SEL>>
v(line)
-400V
0V
400V
Pout=250W, Slew Rate=160V/mS
Output Voltage
Input Voltage
Input Voltage Step Response: 115Vrms to 230Vrms
Prof. S. Ben-Yaakov , Control Design of PWM Converters [202]
Current Loop Gain at Different Input Voltages
Vin=50V, 100V, 200V, 300V
Frequency
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
p(v(ba_out)/v(Don))-180
-200d
-100d
0d
db(v(ba_out)/v(Don))
-200
0
200
SEL>>
102
Prof. S. Ben-Yaakov , Control Design of PWM Converters [203]
Loop Gain of Voltage Control Loop
Frequency
100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz
p(v(ba_out)/v(vaout))-180
-400d
-200d
0d
db(v(ba_out)/v(vaout))
-200
-100
0
SEL>>
Φm=650
Prof. S. Ben-Yaakov , Control Design of PWM Converters [204]
PSpice simulation
PFC-AC PFC-TRAN
103
Prof. S. Ben-Yaakov , Control Design of PWM Converters [205]
CCM Control Concept with no Sensing of Input Voltage
V ac
L
R o C o
V o D I in
V ref
D off
E/A
PWM
M
SW
Low PassFilter
I L (av) V e
K M
I L
V in
Prof. S. Ben-Yaakov , Control Design of PWM Converters [206]
Average Model
Out
R3
770k
L1
Lin
(14-V(%IN))*14m
don
PARAMETERS:
res = 380*380/P
Lin = 1m
Ts = 1/100k
Vrms = 220
P = 1kW
ba_in
V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff))
G1
i(L1)*v(Doff)/(v(don)+v(doff))
GVALUE
OUT+OUT-IN+IN-
0.99
0
C2
3.3u
Ipk
Vrms*1.414*abs(sin(6.28*50*time))
1-I(L1)*v(k)
14
1
in
E1
V(%IN+, %IN-)*100k
EVALUE
OUT+OUT-
IN+IN-
0
min(1-v(don),2*I(L1)/(v(Ipk)+1u)-v(Don))
doff
R6res
ba_out
v(in)*v(don)*Ts/Lin
0.99
0
eao
R4
10k
OutR1 0.1
Iin
V25
+
-
k
C1
1mF
IC = 390
V1
1Vac0Vdc
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time)))
THD meter
104
Prof. S. Ben-Yaakov , Control Design of PWM Converters [207]
Time
740ms 760ms 780ms 800ms730ms
I(L1)
10A
20A
0A
v(in)
0V
100V
200V
300V
SEL>>
Input Behavior at Different Line Voltages
Pout=1kW, Vin=80Vrms, 230Vrms, 265Vrms
Rectified Input Voltage
Inductor Current
Prof. S. Ben-Yaakov , Control Design of PWM Converters [208]
Frequency
1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz
p(v(ba_out)/v(Don))+180
0d
-100d
100d
db(v(ba_out)/v(Don))
-100
0
100
SEL>>
Loop Gain of Current Control Loop
Φm=900
105
Prof. S. Ben-Yaakov , Control Design of PWM Converters [209]
Frequency
100Hz 1.0KHz 10KHz 100KHz30Hz
db(i(l1)/v(in))
-60
-40
-30
Current Loop Transfer Function
iL/vin=const
Prof. S. Ben-Yaakov , Control Design of PWM Converters [210]
PSpice simulation
PFC_no_sens-TRANPFC_no_sens-AC
106
Prof. S. Ben-Yaakov , Control Design of PWM Converters [211]
Conventional Border Line Control Method
L D
Cout Rload
Ref
R1
R2
-
DRIVERVac
R
SQZero
Detector
Prof. S. Ben-Yaakov , Control Design of PWM Converters [212]
MC33261 Based Average Model
107
Prof. S. Ben-Yaakov , Control Design of PWM Converters [213]
MC33261 Based Average Model
2
10n
0C21.59u
1
0
V(%IN2)*0.62*(V(%IN1) -2.5)
1
3
2
R1
0.1
ea
1
0
iload
0Vdc
ref
L1
Lin
G1
i(l1)*v(Doff)/(v(don)+v(doff))
GVALUE
OUT+OUT-IN+IN-
0
Error Amplifier
0
I1
0.5m
R4
12k
inv
R510k
C5
0.68u
R3
1.6meg
in
0
in
C1
Cout
IC = 400
Out
1.414*Vrms*abs(sin(6.28*50*time))
Don
5.7
2.1
R10nom_load
PARAMETERS:
Lin = 0.87m
Vrms = 220
Nom_load = Vo*Vo/P
Cout = 180u
Vo = 400
P = 175W
Rsense = 0.1
Doff
THD
E1
V(%IN+, %IN-)*17783EVALUE
OUT+OUT-
IN+IN-
C3
10n
R21.3meg
1-v(Doff)
V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff))
Curr_tresh
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time)))
THD meter
0
Out
2*i(L1)*Rsense*V(in)/(v(Curr_tresh)*v(out))
Q2
Q2N2222
R6
1k
Q1Q2N2222
V22.5
+
-
Prof. S. Ben-Yaakov , Control Design of PWM Converters [214]
PSpice simulation
PFC_bord-TRANPFC_bord-AC
108
Prof. S. Ben-Yaakov , Control Design of PWM Converters [215]
Border Line Control Concept with no Sensing of Input Voltage
Prof. S. Ben-Yaakov , Control Design of PWM Converters [216]
onin
avpk TL
V)t(I)t(I == 2 .constTif.const
)t(I
)t(Von
av
in ==
Principle of OperationVin
Ipk(t)
Iin
Iav(t)
t
t
109
Prof. S. Ben-Yaakov , Control Design of PWM Converters [217]
MC33260 Based Average Model
offT
onT
onT
DonE
+=
offon
offDoff
TT
TE
+=
f(Vout)Io =
Prof. S. Ben-Yaakov , Control Design of PWM Converters [218]
Out
0
R51meg
Ton
i(l1)*(sin(6.28*50*time)/abs(sin(6.28*50*time)))
THD meter
1.4*Vrms*abs(sin(6.28*50*time))
C1
Cout
IC = 400
R1
0.1
THD
i(V_Io)
ABM3
L1
LinIC =
v(Vcontrol)*200u*Cch/(2*i(V_Io)*i(V_Io)+10n)
R3
1meg
Out
1
0
Toff
V(OUT)*V(doff)+V(in)*(1-V(Don)-V(Doff))
Doff
C3680n
Vreg
V_Io
2.6V +
-
in
Don
Vcontrol
G1
i(l1)*v(Doff)/(v(don)+v(doff))
GVALUE
OUT+OUT-IN+IN-
R10nom_load
0
In Out
0 1.5v
194u 1.5v
200u 0v
TABLE1
v(Toff)/(V(Ton)+V(Toff))
v(Ton)/(V(Ton)+V(Toff))
iload
0Vdc
2*i(L1)*Lin/(v(out)-v(in))
1
0
PARAMETERS:
Lin = 320u
Vrms = 220
Nom_load = Vo*Vo/P
Cout = 47u
Vo = 400
P = 80
Rsense = 1
CT = 2.7n
Cch = 15p+CT
R6
300k
MC33260 Based Average Model
110
Prof. S. Ben-Yaakov , Control Design of PWM Converters [219]
Combined Stage(Boost-Flyback)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [220]
Principle of Operation
• CB serves as output capacitor for Boost Section and as input voltage source for Flyback section.
ON:
OFF:
111
Prof. S. Ben-Yaakov , Control Design of PWM Converters [221]
Average Model
R6
1k
1
0
1
0
0
C2
100uIC = 50
Flyback Input
Voltage Section
C3
1u
V(out)*n*V(Doff2)
C1
50uIC =
min((2*I(L2)/(V(pk2)+0.1m)-V(Don)),1-V(Don))
0
L2
L2
1 2
V(in)*V(Don)*v(Ts)/L1
pk2
Boost Doff Generator
Boost Inductor Section
310*abs(sin(6.28*50*time))
Flyback Inductor Section
R1
0.1
Load Section
Don
E1
V(%IN+, %IN-)*1e5EVALUE
OUT+OUT-
IN+IN-
Flyback Doff Generator
in
V2
5
I(L1)*V(Doff1)/(V(Don)+V(Doff1))
Feedback and Don Generator
V(Vc)*V(Don)*Ts/L2
NODESET= 500+
I(L2)*V(Don)/(V(Don)+V(Doff2))
Doff1
R4
1meg
Boost Output Section
Vc
V(Vc)*V(Doff1)+V(in)*(1-V(Don)-V(Doff1))
R3
50
Doff2
L1
L1
1 2
0
out
V(Vc)*V(Don)
v(out)*5/50
0
1
0
R2
0.01
I(L2)*n*V(Doff2)/(V(Don)+V(Doff2))
min((2*I(L1)/(V(pk1)+0.1m)-V(Don)),1-V(Don))
pk1
R5
330k
0.2/5
PARAMETERS:
L1 = 50un = 7
Ts = 1/100kHz
L2 = 100u
Prof. S. Ben-Yaakov , Control Design of PWM Converters [222]
V(in)*V(Don)*v(Ts)/L1
Boost Doff Generator
1
0
pk1 Doff1
min((2*I(L1)/(V(pk1)+0.1m)-V(Don)),1-V(Don))
Flyback Doff Generator
V(Vc)*V(Don)*Ts/L2
Doff2
1
0
pk2
min((2*I(L2)/(V(pk2)+0.1m)-V(Don)),1-V(Don))
1
0
0.2/5
0
Don R6
1k
C3
1u
v(out)*5/50
R5
330k
Feedback and Don Generator
E1
V(%IN+, %IN-)*1e5EVALUE
OUT+OUT-
IN+IN-
0
V2
5
Doff Generator for Boost Section
Doff Generator for Flyback Section
Error Amplifier and Don
generatorVoltage Divider
112
Prof. S. Ben-Yaakov , Control Design of PWM Converters [223]
Time
680.0ms 690.0ms 700.0ms 710.0ms671.4ms 721.4ms
I(L1)
0A
0.5A
1.0A
SEL>>
v(out)
37.5V
50.0V
62.5V
Vin=230V, Pout=100W, 50W
Behavior at Different Power Levels
Output Voltage
Inductor Current
Prof. S. Ben-Yaakov , Control Design of PWM Converters [224]
Combined Stage(SEPIC with Transformer)
CoutR
PWM
Vac
load
n:1
LF
+-
Ref
E/A
D
CB
D in f
SW
L B
113
Prof. S. Ben-Yaakov , Control Design of PWM Converters [225]
Principle of Operation
n
Vout 2)( nIILFLB⋅+
ON:
OFF:
Prof. S. Ben-Yaakov , Control Design of PWM Converters [226]
E1
V(%IN+, %IN-)*1e5
EVALUE
OUT+OUT-
IN+IN-
out
R2
0.5
pk1
V(in)*V(Don)*Ts/L1
pk2
0
min((2*I(L2)/(V(pk2)+0.1m)-V(Don)),1-V(Don))
I(L2)*V(Don)/(v(doff2)+v(don))
0.495/5
min((2*I(L1)/(V(pk1)+0.1m)-V(Don)),1-V(Don))
Vc
0
1
0
I(L1)*V(Doff1)*n/(v(doff1)+v(don))+I(L2)*V(Doff2)*n/(v(doff2)+v(don))
Vrms*1.414*abs(sin(6.28*50*time))
V6
1Vac0Vdc
Doff1
V2
5
L1
L1
1 2
V(in)*(v(Don)+V(Doff1))-(V(out)*n+v(Vc))*V(Doff1)
R3
load
ba_in
R5
900k
0
R6
10k
V(Vc)*V(Don)*Ts/L2
L2
L2
1 2
in
V(Vc)*V(Don)-V(out)*n*max(V(Doff2),V(Doff1))
PARAMETERS:
L1 = 90un = 6
Ts = 1/90kHz
L2 = 225uVrms = 265Load = 5
0
ba_out
R4
1meg0
doff2
C4
1u
R1
0.0001
0
1
0
C1140u
IC =
C2
10mIC = 19
Don
1
0
I(L1)*V(Doff1)/(v(doff1)+v(don))
v(out)*5/19
Average Model
114
Prof. S. Ben-Yaakov , Control Design of PWM Converters [227]
Time
640.0ms 650.0ms 660.0ms 670.0ms 679.7ms
v(out)
10V
15V
20V
25V
SEL>>
I(L1)
0A
250mA
500mA
Vin=230V, Pout=70W, 50W
Behavior at Different Power Levels
Inductor Current
Output Voltage
Prof. S. Ben-Yaakov , Control Design of PWM Converters [228]
PSpice simulation
PFC_DCM - CBCPFC_DCM - avg
115
Prof. S. Ben-Yaakov , Control Design of PWM Converters [229]
Prof. S. Ben-Yaakov , Control Design of PWM Converters [230]
9. Digital Control
( ) ( ) ( )sBsPSMKtKsLG =
Analog/continuous control
116
Prof. S. Ben-Yaakov , Control Design of PWM Converters [231]
Digital/discrete control
( ) ( )zBsPSeKKKLG Ts-A/DMt
∆=
• Sampling and computation delay
• Additional gain – KA/D
z
1⇔∆Ts-e
A/D
N
V
2 A/D
PWMN2
1
Prof. S. Ben-Yaakov , Control Design of PWM Converters [232]
Time
T∆∆∆∆
Sampling IssuesZOH
117
Prof. S. Ben-Yaakov , Control Design of PWM Converters [233]
ZOH fs=10KHz
500Hz
1.5KHz
2.5KHz
Prof. S. Ben-Yaakov , Control Design of PWM Converters [234]
Time
sample (n)
computationA/D
output
PWM (n+1)
sample (n+2)(result of sample (n))
D (n) D (n+1)
S
Sf
1T ====
sample (n+1)
Sampling rate = fs
Sampling Delays
118
Prof. S. Ben-Yaakov , Control Design of PWM Converters [235]
Time
sample (n)
computationA/D
outputPWM (n+1)
sample (n+1)
(result of sample (n-1))
D (n) D (n+1)
S
Sf
1T ====
D (n)
Slow Sampling Rate
Sampling rate = 2
fs
Prof. S. Ben-Yaakov , Control Design of PWM Converters [236]
Compensation network, continuous
( ) ( ) ( )tcVdt
tcdVteKV +=− τ
( ) ( ) ( )∫∫∫ +=− dttcVtcdVdtteVK τ
( ) ( ) ( )scVs
1scVseV
s
K+=− τ
( )( ) 1s
K
sV
sV
e
c
+−=
τ
Differential equation:
Integral equation:
Laplace transform:
Transfer function:
2R1R
K =
C1R=τ
+
-Ve(t)
Vc(t)
R2
C
R1
( ) ( ) ( )1
cc
2
e
R
tV
dt
tdVC
R
tV−−=
119
Prof. S. Ben-Yaakov , Control Design of PWM Converters [237]
Discretization rules
Differential equations transforms to difference equations
Integral equations transforms to summations
( ) [ ] [ ]∆T
1nVnV
dt
tdV −−⇒
( ) [ ]∑∫∞=
⇒1-n
-k
kV∆TdttV
Z-transform is the discrete time dual of the Laplace transform
( ) ( ) ( ) [ ] kz
-k
kVzVdtste
-
tVsV −∞
∞==⇔−
∞
∞= ∑∫
Transfer functions are represented in Z
Prof. S. Ben-Yaakov , Control Design of PWM Converters [238]
ωωωωj
σσσσ
S plane]zIm[
-1 ]zRe[
Z plane
-1
1
1
stable unstable
unstable
stable
1
1
e
o
az1
z
az
1
v
v−−−−
−−−−
++++====
++++====
1
e
1
o zv)az1(v −−−−−−−− ====++++)1n()1n( eoo vavv −−−−−−−− ++++⋅⋅⋅⋅====
Unstable if a>1
120
Prof. S. Ben-Yaakov , Control Design of PWM Converters [239]
1z
z)z(
v
v2
in
o
−−−−====
2
1
in
o
z1
z)z(
v
v−−−−
−−−−
−−−−====
1in
2o zv)z1(v −−−−−−−− ====−−−−
1in
2oo zvzvv −−−−−−−− ++++====
)1n()2n( inoo vvv −−−−−−−− ++++====
The intuitive meaning of the z operators ⇒⇒⇒⇒ derivative operator; z ⇒⇒⇒⇒ Delay operator
Prof. S. Ben-Yaakov , Control Design of PWM Converters [240]
Continuous to discrete transformation
• Pole-Zero matching
• Zero Order Hold (ZOH)
• Trapezoid (bilinear) transformation
121
Prof. S. Ben-Yaakov , Control Design of PWM Converters [241]
Pole-Zero matching
• Map discrete poles/zeros by
• For complex s-domain roots
• Maintain same DC gain
T∆isi ez =
T∆ijbT∆iaiiii eezjbas =→+=
( ) ( ) 1z0s zGsG == =
( )( )
( )nz
m
ez
e1K
zV
zV
τ∆T
τ∆T
e
c
−=
−
−=
−
−
( )( )( )( )
( )( )
τ
ττ
∆T
e
c
e
c
∆Te
c
e1PzV
zV
sV
sV
ez
PK
1s
K
sV
sV
−
==
−
−=→=
−→
+=
1|0| zs
Z
== 0b;τ
1a ii
m, n - constants
Prof. S. Ben-Yaakov , Control Design of PWM Converters [242]
Zero Order Hold (ZOH)
Transfer function:
( )( ) nz
m
∆Tz∆T
∆TK
zV
zV
e
c
−=
+−+
=
τττ
1
∆T
1zs
−⇔
∆T
∆TK
+τ
∆T+ττ
Hold equivalent = sampled area
( )( ) 1s
K
sV
sV
e
c
+=
τ
( )( )
1∆T
1z
K
zV
zV
e
c
+−
=τ
122
Prof. S. Ben-Yaakov , Control Design of PWM Converters [243]
Trapezoid (bilinear) transformation
1z
1z
∆T
2s
+−
⇔
Transfer function:
( )( )
−+
+=
1z
1z
2∆T
2∆TK
zV
zV
e
c
τ
2
2
∆T
∆TK
+τ
Hold equivalent = sampled area
( )( ) 1s
K
sV
sV
e
c
+=
τ
( )( )
11z
1z
∆T
2
K
zV
zV
e
c
++−
=τ
Prof. S. Ben-Yaakov , Control Design of PWM Converters [244]
Comparison of hold types
fs=50KHz
( )( ) 1.1s
10
sV
sV
e
c
+=
0
123
Prof. S. Ben-Yaakov , Control Design of PWM Converters [245]
Effects of sampling rate
Hold Type: ZOH
Discretization: Inherent Phase-lag
Prof. S. Ben-Yaakov , Control Design of PWM Converters [246]
A/D and PWM ResolutionThe Limit Cycle Problem
Oscillatory output Stable output[mV/bit]
duty/Vc
124
Prof. S. Ben-Yaakov , Control Design of PWM Converters [247]
No Limit cycle rules
One bit of the DPWM should change Vo
by less than 1 bit of the A/D
Compensator must include integral action (included in PID)
System must satisfy Nyquist criterion
Taking into account the system gains
A/DDPWMtPS qqKK <
0A(s)B(s)10A(s)B(s)1 ≠+>+
Stability Oscillations
Prof. S. Ben-Yaakov , Control Design of PWM Converters [248]
Digital Compensator Design Methods
Frequency domain based
Pole location in z plane
Time domain design
125
Prof. S. Ben-Yaakov , Control Design of PWM Converters [249]
Frequency domain design
1. Design a frequency domain controller (Bode, Nichols, etc.)
2. Refinement: take into account the sampling and computational delays
3. Translate the analog controller into a Z equivalent
4. Simulate by numerical simulator (e. g. MATLAB)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [250]
Frequency domain design References
[1]V. Yousefzadeh, W. Narisi, Z. Popovic, and D. Maksimovic, “A digitally controlled DC/DC converter for an RF power amplifier”, IEEE Trans. on PE, Vol. 21, 1, 164-172, 2006.
[2]G. F. Franklin, J. D. Powell, M. L. Workman, Digital control of dynamic systems, 3rd edition, Prentice Hall, 1998.
[3] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller IC for DC-DC converters”, IEEE Trans. on PE, Vol. 18, 1, 2, 438-446, 2003.
126
Prof. S. Ben-Yaakov , Control Design of PWM Converters [251]
Z Plane DesignUsing the MATLAB SISO tool
1. Define the system structure
2. Define the Plant response
3. Define the compensator template
4. Select the analysis view (Root Locus, Bode, Nichols)
5. Insert design constraints (gain, BW, PM, settling time, Natural frequency, etc.)
6. You can use the GUI to change pole/zero locations (either in S or Z and observe the resulting closed loop response
• Trial and error procedure
Prof. S. Ben-Yaakov , Control Design of PWM Converters [252]
MATLAB SISO tool References
[1] O. Garcia, A. de Castro, A. Soto, J. A. Oliver, J. A. Cobos, J Cezon, “Digital control for power supply of a transmitter with variable reference”, IEEE Applied Power Electronics conference APEC-2006, 1411-1416, Dallas, 2006.
[2] The Mathworks, Matlab control toolbox user guide, available at www.mathworks.com.
127
Prof. S. Ben-Yaakov , Control Design of PWM Converters [253]
Time domain Discrete Controller Design
Digital compensator operates in the sampled-data domain
Direct controller design - does not involve errors related to approximations (s to z)
When working in the time domain, system attributes such as bandwidth and phase margin seem artificial
Relevant parameters are: rise time, overshoot etc.
Improved performance of the closed loop system compared to other discrete design approaches
Does not involve trial and error procedure
Prof. S. Ben-Yaakov , Control Design of PWM Converters [254]
Time domain Discrete Controller DesignReferences
[1] G. F. Franklin, J. D. Powell, M. L. Workman, Digital control of dynamic systems, 3rd edition, Prentice Hall, 1998.
[2] J. R. Ragazzini and G. F. Franklin, Sampled-data control systems, McGraw-Hill, 1958.
[3] J. G. Truxal, Automatic feedback control systems synthesis, McGraw-Hill, 1955.
[4] B. Miao, R. Zane, and D. Maksimovic, “Automated Digital Controller
[5] Design for Switching Converters”, IEEE Power Electronics Specialists Conference, PESC-2005, 2729-2735, Recife, 2005.
[6] M. M. Peretz and S. Ben-Yaakov, Time domain design of digital compensators for PWM DC-DC converters, IEEE Applied Power Electronics conference APEC-2007, In Press.
NEW
128
Prof. S. Ben-Yaakov , Control Design of PWM Converters [255]
Time domain Discrete Controller Design
• Plant transfer function (continuous): A(s)
• S to Z transformation: A(s) -> A(z)
• Defining the desired closed loop response: ACL(s)
• S to Z transformation: ACL(s) -> ACL(z)
• Ideal controller:
( ) ( ) ( )( ) ( )
( ) ( )( ) ( )zAzA
zAzB
zBzA1
zBzAzA
CL
CLCL
1
1 −=→
+=
Prof. S. Ben-Yaakov , Control Design of PWM Converters [256]
Closed-loop response
oo 90m45 <<ϕ
1Qω
s
ω
s
n2
n
2++
1
2nd order system Design constraint:
System will have the characteristic equation
129
Prof. S. Ben-Yaakov , Control Design of PWM Converters [257]
Describing the closed-loop response by time domain characteristics
( )( )
1Qω
s
ω
s
1
sd
sV
n2
n
2o
++
=
2nd order system
( )
( )π
Mln2
π
Mln1
QeM
t
1.8ω
ω
1.8t
p
2p
24Q
11
2Q
π
p
rn
nr
+
−=⇒=
≈⇒≈
−−
Rise time:
Overshoot
0 5 10 15 20 25 30 350
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6Step Response
Time (sec)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [258]
Describing the desired ACL in Z
212
0
212
0
n2
n
2 azaza
bzbzb
1Qω
s
ω
s ++
++→
++
Z
• Second order characteristic equation sets the ACL(z)
denominator (a0, a1, a2)
• To derive the complete ACL equation (i. e. numerator) additional constraints are to be satisfied:
• Stability at infinity (bounded system) ( ) 0zA z|CL =∞=
( ) 1zA z|CL ==1
• Response to ramp (velocity constant) ( )Vz|
CL
K
1
dz
zdA=
=1
• Steady state error to step
130
Prof. S. Ben-Yaakov , Control Design of PWM Converters [259]
Template-oriented controller
( ) ( )( ) ( )zA
1
zCLA1
zCLAidealzB
−=
•Ideal controller to satisfy the design constraints
This design method suffers from:
• controller implementation on digital platform vary by design (plant, ACL, etc.)
• High order - too many parameters – long computation time
Prof. S. Ben-Yaakov , Control Design of PWM Converters [260]
Template-based controller
In each computational event, only data points around the sampling instant are considered
The controller uses only information that is in the vicinity of the sampling instant and is blind to all other information
The implemented finite difference equation can be based on a short-term time response of the system rather than on the full response
131
Prof. S. Ben-Yaakov , Control Design of PWM Converters [261]
A look at the step response of B(z)ideal
Objective:• Find a compensator template that will match (or will be
close to) the the ideal response – at least at the first few samples
• The compensator should have fewer computation cycles
Prof. S. Ben-Yaakov , Control Design of PWM Converters [262]
The answer - PID controller
( )( ) s
1Qω
s
ω
s
sV
sV c2
c
2
e
c
++
=
PID template: continuous
( )( ) 21
21
e
c
zz
czbza
zV
zV
−−
−−
−
++=
PID template: discrete p-z matching
( )( ) 1
21
e
c
z1
czbza
zV
zV
−
−−
−
++=
Taking into account the sampling delay (A/D)
132
Prof. S. Ben-Yaakov , Control Design of PWM Converters [263]
PID controller
[ ] [ ] [ ] [ ] [ ]2-necV1-nebVneaV1-ncVncV +++=
Difference Equation (will be implemented on the digital platform)
Only 3 samples!!!Only 4 computations!!!
Prof. S. Ben-Yaakov , Control Design of PWM Converters [264]
Extracting PID coefficients (a, b, c)
Amplitude
Ideal
PID
133
Prof. S. Ben-Yaakov , Control Design of PWM Converters [265]
PID coefficients extraction procedure
[ ] [ ] [ ] [ ] [ ]
[ ] [ ] [ ] [ ] [ ][ ] [ ] [ ] [ ] [ ][ ] [ ] [ ] [ ] [ ]
+++=
+++=
+++=
+++=
0cV1bV2aV0V2V
1-cV0bV1aV0V1V
2-cV1-bV0aV1-V0V
2-ncV1-nbVnaV1-nVnV
eeecc
eeecc
eeecc
eeecc
n=0
n=1
n=2
Prof. S. Ben-Yaakov , Control Design of PWM Converters [266]
Design example
Vo = 5V
Tr=100u
Mp=10%
Switching frequency=sampling rate= 50KHz
0.49561.403z2z
0.4123z 0.5044(z)CLA
+−
+=
134
Prof. S. Ben-Yaakov , Control Design of PWM Converters [267]
Plant response
Amplitude
0.961.908z2z
0.06459z 0.06548PS(z)
++
+=
82
8
101.333 + s 2500 + s
103.333PS(s)
⋅
⋅= ZOH
Prof. S. Ben-Yaakov , Control Design of PWM Converters [268]
Ideal controller response
z 0.05945 2z 0.1249 - 3z 0.06548
0.3958 -1.271z2z 1.375 -30.5044zB(z)
+
+=
135
Prof. S. Ben-Yaakov , Control Design of PWM Converters [269]
Extracting PID coefficients (a, b, c)
( )1
21
Fz
2.93z6.15z3zB
−
−−
−
+−=
1
4.
Prof. S. Ben-Yaakov , Control Design of PWM Converters [270]
Closed loop response
0 0.5 1 1.5 2 2.5 3
x 10-3
0
0.2
0.4
0.6
0.8
1
1.2
1.4Step Response
Time (sec)
Am
plitu
de
Ideal
PID
136
Prof. S. Ben-Yaakov , Control Design of PWM Converters [271]
Closed loop step response - results
Reference is stepped from 5V to 6V
Prof. S. Ben-Yaakov , Control Design of PWM Converters [272]
A look at the frequency domain
PM=40
BW=4KHz
Magnitude (dB)
Phase (deg)
137
Prof. S. Ben-Yaakov , Control Design of PWM Converters [273]
Experimental
PM=33
BW=3.2KHz
Prof. S. Ben-Yaakov , Control Design of PWM Converters [274]
Load step
PID coefficients
a=3.4
b=-6.15
c=2.93 Vout
138
Prof. S. Ben-Yaakov , Control Design of PWM Converters [275]
Slower Response
Vo = 5V
Tr=500u
Mp=0% No over shoot
Switching frequency=sampling rate= 50KHz
Prof. S. Ben-Yaakov , Control Design of PWM Converters [276]
Controller response
( )1
21
Sz
z1z2zB
−
−−
−
+−=
1
38.81.52.1Derived PID:
139
Prof. S. Ben-Yaakov , Control Design of PWM Converters [277]
Closed loop
0 0.5 1 1.5 2 2.5 3
x 10-3
0
0.2
0.4
0.6
0.8
1
1.2
1.4Step Response
Time (sec)
Am
plitu
de
Prof. S. Ben-Yaakov , Control Design of PWM Converters [278]
Closed loop step response - results
Reference is stepped from 5V to 6V
140
Prof. S. Ben-Yaakov , Control Design of PWM Converters [279]
A look at the frequency domain
PM=80
BW=800Hz
Prof. S. Ben-Yaakov , Control Design of PWM Converters [280]
Experimental
PM=80
BW=1.5KHz
141
Prof. S. Ben-Yaakov , Control Design of PWM Converters [281]
Load step
PID coefficients
a=1.52
b=-2.81
c=1.38
Prof. S. Ben-Yaakov , Control Design of PWM Converters [282]
Comparison to analog design
The analog controller was set to have the same bandwidth as the digital design
Load step applied: 1A to 1.5A
142
Prof. S. Ben-Yaakov , Control Design of PWM Converters [283]
Load step - analog (Spice simulation)
Prof. S. Ben-Yaakov , Control Design of PWM Converters [284]
Load step - analog
143
Prof. S. Ben-Yaakov , Control Design of PWM Converters [285]
Load step digital
Prof. S. Ben-Yaakov , Control Design of PWM Converters [286]
Thank you for Your Attention
Thanks to the Israeli Science Foundation for supporting our research
144
Prof. S. Ben-Yaakov , Control Design of PWM Converters [287]
10. Q&A
Prof. S. Ben-Yaakov , Control Design of PWM Converters [288]
Sort Biography of Presenter
Prof. Shmuel (Sam) Ben-Yaakov
BSc degree in Electrical Engineering from the Technion, Haifa Israel, in 1961
MS and PhD degrees in Engineering from the UCLA, in 1967 and 1970
respectively.
Full Professor at the Department of Electrical and Computer Engineering, Ben-
Gurion University of the Negev, Beer-Sheva, Israel,
Heads the Power Electronics Group of BG University
Published over 250 scientific and technical papers in leading journals and
conferences
Holds about 20 patents (as an inventor)
Consultant to companies worldwide on design-oriented theoretical issues in
the areas of analog and power electronics as well as on product development.
Founder and CTO of Green Power Technologies Ltd. (http://www.g-p-t.com)
Present research interests include: power electronics aspects of piezoelectric
elements, analog and digital control, power factor correction, lighting
electronics, soft switching and active thermal cooling.
145
Prof. S. Ben-Yaakov , Control Design of PWM Converters [289]
Primary to secondary isolation
The problem :
FilterConverter RO V
O
D
Isolationbarrier
Prof. S. Ben-Yaakov , Control Design of PWM Converters [290]
isolation
oVPowerstage
feedback
refV
inP
-+
Alternative
Powerstage
refV
-+
D
feedback
isolation
oV
A
B
isolation
Powerstage
feedback
oV
Gain-
refV
+
isolation
Powerstage
-
refV
++Gain
feedback
D
D
oV
C
D