control code device function connector * see …...u14 syncoutb0_c_n_adrv vdd_interface_c...

1 17

<User Define><User Define><User Define>

: Pitch-pitch StyleVendor StylePACKAGE : N/A-lead N/A N/A-family

: NAProduct(s): adrv9009HW TYPE : Customer Evaluation

no_template

ACodeID1:1

02_057106TBD

-

-

-

-

-

<PTD_ENGINEER>

-

-

-

-

REV

2REVISIONS

1

OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER

8

CONNECTORFUNCTIONCODE DEVICE

2

2

6JUMPER TABLE

4

7

5

A

3

DATE APPROVED

D

B

DESCRIPTION

34

OFFON

5

57

OEM PART# HANDLER

6

C

B

8

SOCKET OEMBK/BD SPEC.P.O SPEC.

A

1

RELAY CONTROL CHART

3 14

C

NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS

CHECKER

DESIGNER

PTD ENGINEER

TEST ENGINEER

DECIMALS

X.XXX +-0.005X.XX +-0.010

MASTER PROJECT TEMPLATE

TOLERANCES

+-1/32FRACTIONS

+-2SIZE

DDDD

SCHEMATIC

DRAWING NO.

SCALE CODE ID NO.SHEET OF

REV.

DA A

ENV C

L GSE

ODATE

ANGLES

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES

TESTER TEMPLATE

TEMPLATE ENGINEER

HARDWARE SERVICES

HARDWARE SYSTEMS

COMPONENT ENGINEER

TEST PROCESS

HARDWARE RELEASE

* SEE ASSEMBLY INSTRUCTIONS

CONTROL

D

TALISE C

USE LOW-PROFILE PADS FOR CAPACITORS

(AUXDAC_3/FLASH SI)

(AUXDAC_1/FLASH CS)

(AUXDAC_0/FLASH SO)

(AUXDAC_7)

(AUXDAC_8)

JESD CAPS CLOSE TO FPGA

(AUXDAC_6)

(AUXDAC_5)

(AUXDAC_9/FLASH CLK)

(AUXDAC_2)


(AUXDAC_4)

1UF

88

ADRV9009BBCZ

10K

2 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

100

0.1UF

82

0

0

0

81

0.1UF

11

8

0.1UF9

8921

0

0

4.7K

100

0.1UF

0.1UF

20

0.1UF15

0.1UF0.1UF

100PF

68

1UF

14.3K

59

R0201L

58

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0

0

0

0.1UF

0.1UF

1UF

25

10K10K 10K

37

100

10K

27

R514

R144R553

R551

R140

C417

C400

R139

C399

C413

C402

C401

C407C412

C406

C405

C404

C411

C410

C409

C408C403

R552

R527

R520

R518

R519

R516

R517

C416

C418C415

C414

R141 R142 R143

R515

R513

U14

SYNCOUTB0_C_N_ADRV

VDD_INTERFACE_CJESD_SERDOUT0_C_P

AUX_SYNTH_VTUNE_CJESD_SERDIN0_C_P

SPI_CSN_ADRV9009_C

TX2_OUT_C_P

JESD_SERDOUT3_C_P

GPIO_10_C

RESETB_C

VDD_INTERFACE_C

TX1_OUT_C_P

GPIO_18_C

SPI_MOSI

GPIO_3P3_8_CGPIO_3P3_10_CGPIO_3P3_2_CGPIO_3P3_5_C

VDDA1P8_TX_C

GPIO_1_C

SPI_MISO

TX1_OUT_C_N

GPIO_5_C

GPIO_3_C

SYNCINB1_C_N_ADRVSYNCINB1_C_P_ADRVGPIO_6_CGPIO_7_C

GPIO_4_C

RX1_IN_C_NRX1_IN_C_P

RX2_IN_C_NRX2_IN_C_P

ORX1_IN_C_NORX1_IN_C_P

ORX2_IN_C_NORX2_IN_C_P

SYNCOUTB0_C_P_ADRV

SYNCOUTB0_C_N_ADRV

VDDA1P3_AUX_VCO_LDO_C

VDDA1P3_CLOCK_VCO_LDO_C

VDDA1P3_AUX_SYNTH_C

RF_EXT_LO_C_PRF_EXT_LO_C_N

GPIO_16_C

GPIO_17_C

SYNCINB0_C_P_ADRV

SYNCINB0_C_N_ADRV

GPIO_9_CGPIO_14_C

GPIO_13_C

GPIO_11_CGPIO_12_C

RF_SYNTH_VTUNE_C

VDDA1P3_RF_SYNTH_C

VDDA1P3_CLOCK_SYNTH_C

AUXADC_2_C

AUXADC_1_C

AUXADC_0_C

GPIO_3P3_11_C

GPIO_3P3_7_C

AUXADC_3_C

GPIO_3P3_4_CGPIO_3P3_1_C

GPIO_3P3_9_CVDDA3P3

VDDA1P3_RF_LO_C

VDDA1P3_RX_RF_C

RX2_ENABLE_C

SYNCOUTB1_C_P_ADRV

SPI_CLK

SYNCOUTB0_C_N

SYNCOUTB0_C_P

SYNCOUTB1_C_P_ADRV

SYNCINB0_C_P

SYNCINB1_C_P_ADRV SYNCINB1_C_P

SYNCINB1_C_N

VDD_INTERFACE_C

VDDA1P3_RF_VCO_LDO_C

VDDA1P3_BB_C

AUX_SYNTH_OUT_C

SYNCOUTB0_C_P_ADRV

SYNCOUTB1_C_N_ADRV

SYNCINB1_C_N_ADRV

JESD_SERDOUT2_C_PJESD_SERDOUT2_C_N

JESD_SERDOUT3_C_NJESD_SERDIN1_C_N

JESD_SERDIN2_C_NJESD_SERDIN3_C_PJESD_SERDIN3_C_N

JESD_SERDIN2_C_P

VDDA1P3_DES_CVDDA1P3_SER_C

JESD_SERDIN1_C_PJESD_SERDIN0_C_N

JESD_SERDOUT1_C_N

JESD_SERDOUT0_C_N

TX2_ENABLE_C

TX1_ENABLE_CRX1_ENABLE_C

SYNCINB0_C_P_ADRV

SYNCINB0_C_N_ADRV

SYNCOUTB1_C_N

REF_CLK_IN_C_NREF_CLK_IN_C_P

VDDA1P8_BB_CGPIO_3P3_6_C

JESD_SERDOUT1_C_P

SYNCOUTB1_C_N_ADRV

SYNCINB0_C_N

SYNCOUTB1_C_P

GPIO_3P3_0_CGPIO_3P3_3_CVDDA1P3_RX_TX_C

GPIO_8_CGPIO_15_C

VDD1P3_DIG_C

GPIO_0_C

JESD_SYSREF_IN_C_NJESD_SYSREF_IN_C_P

GPIO_2_C

GPINT_C

TX2_OUT_C_N

J10

K3

F9

J8

J14

E10

P1

F3 F4 F11

E11

K10

J5

K8

J7

K7

C1

D1

E1

C2

D2

E2 E3 E13

D13

C13

D14

E14

K6K5

L5L6

L12

K12

J12

H12H11

J11

K11

L11

M11

J3

A12A13

A2A3

C14

E7 E8

J4

B8B7

G9

M5

A9A10

M7

A5A6

K9

J9

N13

N12

N11

N10

P14

P13

P12

P11

P7 P6 P5 P4 N6

L4L3

M14

M13

K4

J6

H14J1

D10

M1

C7

C10

E5 G5

N9P9

C8

G7

C5C6

B1

C3

N8P8

E4 E12

C12

L8L9

A1

A4

A7A8

A11

A14

B2B3B4B5B6

B9B10B11B12B13B14

C4

C9

C11

D3D4D5D6D7

D8 D9 D11

D12 E6 E9 F1 F2 F5 F6 F7 F8 F10

F12

F13

F14

G1

G2

G3

G4

G6

G10

G11

G12

G13

G14

H3H4H5H6H7H8H9H10

H13

J2

J13

K1K2

K13K14L1L2

M2

M9

N7N14

P2P3P10

L7

L10

L13

L14

M3

M6

M10

M12

N1N2N5 N4 N3 M4

M8

H2H1

G8

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSAVSSAVSSAVSSA

VSSAVSSA

VSSA

VSSA

VSSA

VSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSAVSSAVSSAVSSAVSSA

VSSA

VSSA

VSSA

VSSAVSSAVSSAVSSAVSSAVSSA


VSSA

VSSA

VSSAVSSA

RX1_IN-RX1_IN+

RX2_IN-RX2_IN+

VDDA1P3_RF_VCO_LDOVDDA1P3_RF_VCO_LDO

ORX1_IN-ORX1_IN+

ORX2_IN-ORX2_IN+

SERD

IN2+

SERD

IN2-

SERD

IN3+

SERD

IN3-

VDDA

1P3_

DES

VDDA

1P3_

SER

SERD

IN0+

SERD

IN0-

SERD

IN1+

SERD

IN1-

VDDA

1P3_

DES

VDDA

1P3_

SER

SYNC

OUT

B0+

SYNC

OUT

B0-

TX2_

ENAB

LE

TX1_

ENAB

LE

SYNC

OUT

B1+

SYNC

OUT

B1-

TX1_OUT-

TX2_OUT+TX1_OUT+

TX2_OUT-

VDDA

1P8_

TX

VDDA1P3_RX_TX

VSSA

GPIO_18

AUX_

SYNT

H_O

UT

VDDA

1P1_

AUX_

VCO

VDDA1P3_AUX_VCO_LDO

AUX_

SYNT

H_VT

UNE

VDDA

1P3_

CLO

CK_V

CO_L

DO

VDDD

1P3_

DIG

VDDD

1P3_

DIG

GP_INTERRUPT

VDDA

1P3_

AUX_

SYNT

H

RF_EXT_LO_I/O+RF_EXT_LO_I/O-

SERD

OUT

0+SE

RDO

UT0-

SERD

OUT

1+SE

RDO

UT1-

SERD

OUT

2+SE

RDO

UT2-

SERD

OUT

3+SE

RDO

UT3-

VDD_

INTE

RFAC

EG

PIO

_16

GPI

O_1

7

RX2_

ENAB

LE

RX1_

ENAB

LESY

NCIN

B0+

SYNC

INB0

-

VDDA

1P1_

CLO

CK_V

CO

GPI

O_8

GPI

O_1

5VS

SD

VSSDGPIO_7GPIO_6

SYNCINB1+SYNCINB1-

GPIO_9GPIO_14

CSBSCLK

GPIO_0GPIO_3GPIO_4GPIO_5

SYSREF_IN-SYSREF_IN+

GPIO_10GPIO_13

SDOSDIO

GPIO_1GPIO_2

TEST

RESETB

GPIO_11GPIO_12

RF_S

YNTH

_VTU

NE

VDDA

1P3_

RF_S

YNTH

VDDA

1P3_

CLO

CK_S

YNTH

AUXA

DC_2

AUXA

DC_1

AUXA

DC_0

GPI

O_3

p3_1

1G

PIO

_3p3

_7

AUXA

DC_3

REF_

CLK_

IN-

REF_

CLK_

IN+

VDDA

1P3_

BBVD

DA1P

8_BB

GPI

O_3

p3_6

GPI

O_3

p3_5

GPI

O_3

p3_2

GPI

O_3

p3_1

0G

PIO

_3p3

_8

GPIO_3p3_4GPIO_3p3_1RBIASGPIO_3p3_9VDDA_3P3

VDDA1P3_RF_LOVDDA1P1_RF_VCO

GPIO_3p3_3GPIO_3p3_0

VDDA1P3_RX_RF

VSSA

GND

GND

GNDGND

GND

GND

GND

GND

D

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

AC

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.

2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

JESD CAPS CLOSE TO FPGA

(AUXDAC_2)

(AUXDAC_8)

(AUXDAC_1/FLASH CS)

(AUXDAC_0/FLASH SO)

(AUXDAC_7)

(AUXDAC_4)

(AUXDAC_6)

(AUXDAC_5)

(AUXDAC_9/FLASH CLK)

(AUXDAC_3/FLASH SI)


TALISE D


3 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

25

10K

5

19

672026

10K

21

13

10K10K1UF

0.1UF

0.1UF16

0.1UF

0.1UF

0.1UF

R0201L

1UF

28

14.3K

27

1UF

29

22

100PF

3

4

0.1UF

20.1UF

1

150.1UF

14

0.1UF

100.1UF

11

0.1UF

9

0.1UF

8

100

100

4.7K

0

0

0

0

0

0.1UF

17

180.1UF

0

0

0

10K

0.1UF

100ADRV9009BBCZ

0.1UF

12

R549

R88

C312

C305

R83

C304

C318

C307

C306C317

C311

C310

C309

C316

C315

C313

C314

C308

R550

R548

R526

R505

R504

R502

R501

C321 R84

C323

C319

C320C322

R85 R86 R87

R500

R499

R498

U38R503

GPIO_1_D

GPIO_18_DRESETB_D

VDD_INTERFACE_D

GPINT_D

GPIO_11_DGPIO_12_D

GPIO_9_D

JESD_SERDIN3_D_P

RX1_IN_D_NRX1_IN_D_P

RX2_IN_D_NRX2_IN_D_P

ORX1_IN_D_NORX1_IN_D_P

ORX2_IN_D_N

SYNCOUTB0_D_P_ADRV

SYNCOUTB0_D_N_ADRV

TX2_OUT_D_PTX1_OUT_D_P

TX2_OUT_D_N

VDDA1P8_TX_D

VDDA1P3_AUX_VCO_LDO_D

VDDA1P3_CLOCK_VCO_LDO_D

VDDA1P3_AUX_SYNTH_D

RF_EXT_LO_D_N

VDD_INTERFACE_D

GPIO_16_D

GPIO_17_D

SYNCINB0_D_P_ADRV

SYNCINB0_D_N_ADRV

SYNCINB1_D_N_ADRV

GPIO_0_DGPIO_3_D

RF_SYNTH_VTUNE_D

VDDA1P3_RF_SYNTH_D

AUXADC_2_D

AUXADC_1_D

AUXADC_0_D

GPIO_3P3_11_D

GPIO_3P3_7_D

AUXADC_3_D

GPIO_3P3_4_DGPIO_3P3_1_D

GPIO_3P3_9_DVDDA3P3

VDDA1P3_RF_LO_D

VDDA1P3_RX_RF_D

JESD_SERDOUT3_D_N

JESD_SERDOUT2_D_NJESD_SERDOUT2_D_P

JESD_SERDOUT3_D_P

JESD_SERDIN2_D_NJESD_SERDIN2_D_P

JESD_SERDOUT1_D_PJESD_SERDOUT0_D_N

JESD_SERDOUT1_D_NAUX_SYNTH_VTUNE_DJESD_SERDIN0_D_P

JESD_SERDIN1_D_N

SYNCINB1_D_N_ADRV SYNCINB1_D_N

GPIO_8_D

GPIO_3P3_10_D

VDD1P3_DIG_D

AUX_SYNTH_OUT_DREF_CLK_IN_D_NREF_CLK_IN_D_P

VDDA1P3_BB_DVDDA1P8_BB_DGPIO_3P3_6_DGPIO_3P3_5_DGPIO_3P3_2_D

GPIO_3P3_8_D

SYNCINB1_D_P

SYNCINB0_D_PSYNCINB0_D_P_ADRV

SYNCINB0_D_N

SYNCOUTB1_D_N

SYNCOUTB1_D_N_ADRVSYNCOUTB0_D_P

SYNCOUTB1_D_P_ADRV

SYNCOUTB0_D_NSYNCOUTB0_D_N_ADRV

SPI_CLK

TX2_ENABLE_D

RX1_ENABLE_DTX1_ENABLE_D

RX2_ENABLE_D

GPIO_13_DSPI_MISO

VDDA1P3_CLOCK_SYNTH_D

SYNCINB1_D_P_ADRV

GPIO_2_D

GPIO_10_D

SPI_MOSI

GPIO_15_D

JESD_SERDOUT0_D_PVDDA1P3_SER_D

VDDA1P3_DES_DJESD_SERDIN3_D_N

GPIO_3P3_0_D

ORX2_IN_D_P

GPIO_14_D

SYNCOUTB1_D_P_ADRV

SYNCINB0_D_N_ADRV

SYNCINB1_D_P_ADRV

SYNCOUTB1_D_N_ADRV

SYNCOUTB0_D_P_ADRV

TX1_OUT_D_N

JESD_SYSREF_IN_D_PJESD_SYSREF_IN_D_NGPIO_5_DGPIO_4_D


VDD_INTERFACE_D

GPIO_7_DGPIO_6_D

SPI_CSN_ADRV9009_D

RF_EXT_LO_D_P

VDDA1P3_RF_VCO_LDO_D

GPIO_3P3_3_DVDDA1P3_RX_TX_D

SYNCOUTB1_D_P

J1H14

M6

E10

P1

F3 F4 F11

E11

K10

J5

K8

J8J7

K7

C1

D1

E1

C2

D2

E2 E3 E13

D13

C13

D14

E14

K6K5

L5L6

L12

K12

J12

H12H11

J11

K11

L11

M11

M10

J3

A12A13

A2A3

C14

E7 E8

J4

B8B7

G9

M5

A9A10

M7

A5A6

K9

J9J10

N13

N12

N11

N10

P14

P13

P12

P11

P7 P6 P5 P4 N6 N5 N4 N3 M4

M3

L4L3

M14

M13

L14

L13

K3K4

J6

J14

M8

H1

M12

D10

M1

C7

G8

C10

E5 G5

N1N9P9

C8

G7

C5C6

B1

C3

N8P8

E4 E12

C12

L8L9

A1

A4

A7A8

A11

A14

B2B3B4B5B6

B9B10B11B12B13B14

C4

C9

C11

D3D4D5D6D7

D8 D9 D11

D12 E6 E9 F1 F2 F5 F6 F7 F8 F9 F10

F12

F13

F14

G1

G2

G3

G4

G6

G10

G11

G12

G13

G14

H2H3H4H5H6H7H8H9H10

H13

J2

J13

K1K2

K13K14L1L2

M2

M9

N2N7N14

P2P3P10

L7

L10

GND

GND

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSAVSSAVSSAVSSA

VSSAVSSA

VSSA

VSSA

VSSA

VSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA


VSSA

VSSA

VSSA

VSSAVSSAVSSAVSSAVSSAVSSA


VSSA

VSSA

VSSAVSSA

RX1_IN-RX1_IN+

RX2_IN-RX2_IN+

VDDA1P3_RF_VCO_LDOVDDA1P3_RF_VCO_LDO

ORX1_IN-ORX1_IN+

ORX2_IN-ORX2_IN+

SERD

IN2+

SERD

IN2-

SERD

IN3+

SERD

IN3-

VDDA

1P3_

DES

VDDA

1P3_

SER

SERD

IN0+

SERD

IN0-

SERD

IN1+

SERD

IN1-

VDDA

1P3_

DES

VDDA

1P3_

SER

SYNC

OUT

B0+

SYNC

OUT

B0-

TX2_

ENAB

LE

TX1_

ENAB

LE

SYNC

OUT

B1+

SYNC

OUT

B1-

TX1_OUT-

TX2_OUT+TX1_OUT+

TX2_OUT-

VDDA

1P8_

TX

VDDA1P3_RX_TX

VSSA

GPIO_18

AUX_

SYNT

H_O

UT

VDDA

1P1_

AUX_

VCO

VDDA1P3_AUX_VCO_LDO

AUX_

SYNT

H_VT

UNE

VDDA

1P3_

CLO

CK_V

CO_L

DO

VDDD

1P3_

DIG

VDDD

1P3_

DIG

GP_INTERRUPT

VDDA

1P3_

AUX_

SYNT

H

RF_EXT_LO_I/O+RF_EXT_LO_I/O-

SERD

OUT

0+SE

RDO

UT0-

SERD

OUT

1+SE

RDO

UT1-

SERD

OUT

2+SE

RDO

UT2-

SERD

OUT

3+SE

RDO

UT3-

VDD_

INTE

RFAC

EG

PIO

_16

GPI

O_1

7

RX2_

ENAB

LE

RX1_

ENAB

LESY

NCIN

B0+

SYNC

INB0

-

VDDA

1P1_

CLO

CK_V

CO

GPI

O_8

GPI

O_1

5VS

SD

VSSDGPIO_7GPIO_6

SYNCINB1+SYNCINB1-

GPIO_9GPIO_14

CSBSCLK

GPIO_0GPIO_3GPIO_4GPIO_5

SYSREF_IN-SYSREF_IN+

GPIO_10GPIO_13

SDOSDIO

GPIO_1GPIO_2

TEST

RESETB

GPIO_11GPIO_12

RF_S

YNTH

_VTU

NE

VDDA

1P3_

RF_S

YNTH

VDDA

1P3_

CLO

CK_S

YNTH

AUXA

DC_2

AUXA

DC_1

AUXA

DC_0

GPI

O_3

p3_1

1G

PIO

_3p3

_7

AUXA

DC_3

REF_

CLK_

IN-

REF_

CLK_

IN+

VDDA

1P3_

BBVD

DA1P

8_BB

GPI

O_3

p3_6

GPI

O_3

p3_5

GPI

O_3

p3_2

GPI

O_3

p3_1

0G

PIO

_3p3

_8

GPIO_3p3_4GPIO_3p3_1RBIASGPIO_3p3_9VDDA_3P3

VDDA1P3_RF_LOVDDA1P1_RF_VCO

GPIO_3p3_3GPIO_3p3_0

VDDA1P3_RX_RF

VSSA

GNDGND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

DECOUPLING TALISE C

POSSIBLE INDUCTOR

0201 FOOTPRINT

OVERLAP PADS

1.3VDC

SHARE PADS

4 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

100UF

30

50

1UF

57

0.01UF

55

0.1UF

92

0.01UF

97

0.1UF

100UF

2928

470UF

48

0.1UF

49

0.01UF

100UF

35

100UF

38

100UF

3639

100UF1UF

60

0.1UF

6162

0.01UF

85

10UF1UF

94

0.1UF

93

341.8KOHM AT 100MEGHZ

80

1UF

86

0.1UF

87

1UF

5654

100UF

DNI

106

30OHM107

0104

0.1UF

1UF

96103

10UF

102

108

0

0.01UF

105

117

10UF1UF

99

0.1UF0.01UF

111

0

10UF

122

74

10UF

1UF

69

109

1UF0.1UF

110

83

10UF

0.01UF

98

72

1UF

1UF

78

0.1UF

70

100UF

11975

100UF470UF

0.01UF

115

0.1

1UF

40

76

10UF

77

1UF

53

1UF

65

67

0.1UF0.01UF

66

64

0.1UF0.01UF

63

4142

0.1UF

32

10UF

46

1UF

44

0.01UF

43

0.01UF

45

0.1UF

47

0.01UF

73

0.01UF

95

0

91

0.01UF

51

1.8K OHM AT 100MEGHZ

79

0

113

0

84

0

0

121

118

0

114

0

470UF

0

120

52

0

42OHM AT 100MEGHZ

31

33

0

10UF

71

116

10UF

0.1UF

101 100

10UF

112

DNI

100UF

1UF 0.1UF

10UF0.01UF

C965

C966

C967C963

C968C964

C962C958

C961C956

C949C948C947C945C943C941C935

L16

C922C912C903

E29

C923C913C904

C959

TP103TP102

C955

E30

R373

C951

C960C957C954

R374

TP10

1

TP100

C950

C953C952

C1099C1098

C946C944C942C940

R372

C936

C937

C939

C929C920

C914

C910

C905

C930C921

C934C927C918

C911

R371

C938

C928C919

C933C926

C909C902

C917C908

C931C924

C932C925

C915C906

C916C907

C900

TP12

3

R368

TP89

C901

TP90

E28

R369

TP91

TP92

TP93

R370

R362

R363

TP95

TP96

R364

R365

TP87

TP88C899

TP97

TP94

R366

R361

TP98

TP99

E1

R367

C898

VDDA1P3_BB_C

VDD1P3_DIG_CVDDA1P3_RF_SYNTH_C

VDDA1P3_CLOCK_VCO_LDO_C

VDD1P3_DIG_C

VDDA1P3_RX_RF_C

VDDA1P3_CLOCK_SYNTH_C

VDDA1P3_ANLG_C

VDDA1P3_ANLG_SNS_C

VDDA1P8_C VDDA1P8_TX_C

VDDA1P3_AUX_VCO_LDO_CVDDA1P8_BB_C

VDDA1P3_RF_LO_C

VDDA1P3_RF_VCO_LDO_C

VDDA1P3_AUX_SYNTH_C

VDDA1P3_SER_C

VDDA1P3_DES_C

VDDA1P3_RX_TX_C

VDDA3P3

VDD_INTERFACE_C1V8

21

21

21

GND

GND

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

1.3VDC

DECOUPLING TALISE D

OVERLAP PADS

SHARE PADS

0201 FOOTPRINT

POSSIBLE INDUCTOR

5 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

10UF

100UF

1UF

0.01UF0.1UF

0.01UF0.1UF

1UF

100UF

1UF

470UF

0.1UF0.01UF

100UF100UF100UF100UF1UF0.1UF

DNI

0.01UF

10UF1UF0.1UF

1.8KOHM AT 100MEGHZ

10UF1UF0.1UF

100UF

DNI

30OHM

0

0.1UF

0

100UF

0.01UF

10UF0.01UF

0.1UF1UF

1UF0.1UF0.01UF

0

1UF

10UF

10UF1UF0.1UF

10UF

0.01UF

1UF

1UF0.1UF

100UF100UF

0.01UF

470UF

0.1

1UF

10UF

10UF1UF

1UF0.1UF

0.1UF0.01UF

0.1UF0.1UF

10UF1UF

0.01UF0.01UF

0.1UF0.01UF

0.01UF

0.01UF

0

0.01UF

1.8K OHM AT 100MEGHZ

0

0

0

0

0

0

0

0

42OHM AT 100MEGHZ

0

470UF10UF

10UF

C1035

C1036

C1038C1034

C1039C1037

C1032

C1031

C1033

C1027

C1030C1026

C1020C1019C1018C1016C1014C1012

L17

C1006

C993C983C974

E33

C994C984C975

TP122

C1028

TP121E34

R387

C1022

C1029

R388

C1025

TP12

0

TP119

C1021

C1024C1023

C1101C1100

C1017C1015C1013C1011

R386

C1010

C1008

C1007C1000C991

C985

C981

C976

C1001C992

C1005C998

C982

C989

R385

C1009

C999

C1004C997

C990C980

C988C979

C1002C995

C1003C996

C986C977

C987C978

C973

C971

TP10

7

R382

TP10

8

C972

TP10

9

E31

R383

TP11

0TP

111

TP11

2

R384

R376

R377

TP11

4TP

115

R378

R379

TP105

TP106

TP11

6TP

113

R380

R375

TP11

7TP

118

E32

R381

C970C969

VDDA3P3

VDDA1P3_BB_D

VDD1P3_DIG_DVDDA1P3_RF_SYNTH_D

VDDA1P3_CLOCK_VCO_LDO_D

VDD1P3_DIG_D

VDDA1P3_CLOCK_SYNTH_D

VDDA1P3_ANLG_D

VDDA1P3_ANLG_SNS_D

VDDA1P3_RX_TX_D VDDA1P8_D VDDA1P8_TX_D

VDDA1P3_AUX_VCO_LDO_DVDDA1P8_BB_D

VDDA1P3_RF_LO_D

VDDA1P3_RF_VCO_LDO_D

VDDA1P3_AUX_SYNTH_D

VDDA1P3_SER_D

VDDA1P3_DES_D

VDDA1P3_RX_RF_D

VDD_INTERFACE_D1V8

GND

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

LO IN/OUT

RX, ORX, LO TALISE C

ORX1 C

ORX2 C

RX1 C

RX2 C

6 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

SCIS00512-F

DNI

DNI

0

100PF

100PF

010PF 27PF

DNI

18PF

DNI DNI

0

6

DNI

10

DNI

8

0

9

DNI

18PF

DNI10PF

12

18PF

7

27PF

11

DNI

TCM1-83X+

0

TCM1-83X+

5

4

DNI

0

3

0

2

DNI

0

DNI HHM1595A1

DNI

DNI

1

DNI

DNI

0

DNI10PF 27PF

0

DNI10PF 27PF

18PF

TCM1-83X+

DNI

TCM1-83X+

DNI

0

0

0

DNI

MRXA

C325

J10

C340

R96

C350

C351

R102

R101

R100

R99

C348

T2

C349

T4

C342

C346C344

R97

C343

C347C345

C341

R98

C338

J9

C339

C336

C337

C364

C365

T13

C363

R506

C202

R93

R94

C334

T1

R95T3

C335

C332

C328

C330

C333

C329

C331

J13

R91

C326C324

J1

R92

C327

J2

RX2_IN_C_N

RX2_UNBAL_C

ORX1_IN_C_N

ORX1_IN_C_PORX1_UNBAL_C

RF_EXT_LO_C_N

RX2_BAL_C_P

RF_EXT_LO_C_P

ORX2_BAL_C_NRX2_BAL_C_NORX2_IN_C_N

ORX2_IN_C_PRX2_IN_C_PORX2_BAL_C_PORX2_UNBAL_C

ORX1_BAL_C_NRX1_BAL_C_NRX1_IN_C_N

RX1_IN_C_PORX1_BAL_C_PRX1_BAL_C_PRX1_UNBAL_C 5

4

3

2

6 1

5

4

3

2

6 1

5

4

3

2

6 1

32

1

32

1

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDGNDGNDGNDGNDGNDGNDGNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDGNDGNDGNDGNDGNDGNDGNDGND

NC

NC

GND

GND

GND

GND

GND

GNDGND

GNDGND

GNDGNDNCBALBAL

UNBAL

GNDGND

GND

NC

NC

GND

GND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

LO IN/OUT

RX, ORX, LO TALISE D

ORX1 D

ORX2 D

RX1 D

RX2 D

7 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

DNI

DNI

0

0

0

DNI

0

DNI

TCM1-83X+

DNI

18PF

27PFDNI10PF

DNI

0

18PF

27PF10PFDNI

0

DNI

DNI

DNI

DNI

DNI

100PF

100PFHHM1595A1DNI

0

0

0

DNI

TCM1-83X+

0

0

DNI

27PF10PF

18PF

27PFDNI

18PF

DNI

0

0

DNI

DNI

TCM1-83X+

10PF

DNI

TCM1-83X+

DNI

C1067

C1066

J8

C1069

R396

J7 R395

C1068

C1071

C107

3

C107

5

C1070

C107

2

C107

4

T10

R400

R399

T9

C1076

R398

R397

J15

C1114

R521

C1115

T15

C1116

C1079

C1078

C1081

J12

J11

C1080

C1083

R402

C1087

C108

9

C1085

R401

C1082

C1086

C108

8

C1084

T12

C1091

T11

C1090

R406

C1093

R405

R404

R403

C1092

C1117

C1077

RX1_UNBAL_D RX1_BAL_D_P ORX1_UNBAL_D ORX1_BAL_D_PRX1_IN_D_P ORX1_IN_D_P

RX1_IN_D_N ORX1_IN_D_NRX1_BAL_D_N ORX1_BAL_D_N

RX2_UNBAL_D RX2_BAL_D_P ORX2_UNBAL_D ORX2_BAL_D_PRX2_IN_D_P ORX2_IN_D_P

RX2_IN_D_N ORX2_IN_D_NRX2_BAL_D_N ORX2_BAL_D_N

RF_EXT_LO_D_P

RF_EXT_LO_D_N

1

2 3

2 3

16

2

3

4

5

1

GND

GNDNC

NC

GND

GND

GND

GND

GND

GNDGND

GNDGND

GNDGNDNCBALBAL

UNBAL

GNDGND

GND

GND

NC

NC

GND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

TX1 C

TX CHANNELS TALISE C

TX2 C

8 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

SCIS00511

SCIS00511

0

DNI

18PF

10PF

27PF

51PF

75PF

DNI

0

DNI

TCM1-83X+

10PF

27PF

51PF

75PF

DNIDNI

43NH

DNI

DNI

0

DNI

0

DNI

DNIDNI

0.1UF

43NH

DNI

DNI

0

0

DNI

DNI43NH

0.1UF

43NH

0.1UF

0.1UF

TCM1-83X+

DNI

18PF

MTX2C

MTX1C

C575

L4L8

C571

R201

C579

C581

L3

C574

L7

C573

C578

L2L6

R199

C570

R198

C577

C580

L1

C572

L5 C576

C589

C588

C587

C586

C593

R203

C595

C585

C584

C583

C582

T5 C590

C592

J4

C594

J3

T6 C591

R200

R202

TX1_OUT_C_N TX1_BAL_C_N

TX1_OUT_C_P TX1_BAL_C_P

VDDA1P8_TX_C

TX2_OUT_C_N

TX2_OUT_C_P TX2_BAL_C_P

VDDA1P8_TX_C

VDDA1P8_TX_C

VDDA1P8_TX_C

RFO1_C

RFO2_C

TX2_BAL_C_N

1 6

24

5

1

23

1

23

3

GND

GNDGND

GNDGND

GNDGNDGND

GND

GNDGNDGND

GND

GND

GND

GNDGND

NC

GND

GNDGND

NC

GND

GND

GND

GND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

TX CHANNELS TALISE D

TX1 D

TX2 D

9 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

SCIS00511

SCIS00511

0.1UF

43NHDNI

DNI

0

0

DNI

DNI

43NH

43NH

DNI

0.1UF

DNI

0.1UF

DNI

DNI

0

0

DNI

DNI

43NH

0.1UF

DNI DNI

75PF

51PF

27PF

10PF

TCM1-83X+

18PF

DNI

0

DNI

8

75PF

7

51PF

6

27PF

10PF

5

4

TCM1-83X+

3

DNI

18PF

21

09

DNI

10

MTX1D

MTX2D

J5

C1064

R393C1060

C1062

T7

C1052

C1053

C1054

C1055

J6

C1065

R394

C1063

C1061T8

C1056

C1057

C1058

C1059

C1046L22

C1042

L18

C1050

C1047

R389

R390

L23

C1048

C1043

L24

C1044

C1040

L19

L20

C1051

C1049

R391

R392

C1041

L25L21

C1045

VDDA1P8_TX_D

VDDA1P8_TX_D

TX2_BAL_D_PTX2_OUT_D_P

RFO2_D

TX2_BAL_D_NTX2_OUT_D_N

VDDA1P8_TX_D

TX1_BAL_D_PTX1_OUT_D_P

RFO1_D

TX1_BAL_D_NTX1_OUT_D_N

VDDA1P8_TX_D

3 2

1

3 2

1

GND

GND GND

GNDGND

GNDGNDGND

GND

GNDGNDGND

GNDGND

GNDGND

NC

GND

GNDGNDGND

NC

GND

GND

GND

GND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

PLACE CAPACITORS CLOSE TO FPGA

CML EXTERNAL RESISTORSPLACE TERMINATION CLOSE TO TALISE

CML EXTERNAL RESISTORS

PLACE TERMINATIONS CLOSE TO TALISE

PLACE TERMINATIONS CLOSE TO TALISE

LVDS HIGHPOWER OR CML 50OHM ZOUT

PLACE TERMINATION CLOSE TO TALISE

LVDS HIGHPOWER OR CML 50OHM ZOUT


PLACE PULL-UP RESISTORS CLOSE TO HMC7044







PLACE CAPACITORS CLOSE TO FPGA


LVDS OR CML

LVDS OR CML


PLACE NEAR OSCILLATORREF CLK

PLACE 0 OHM RESISTORS CLOSE TO HMC7044

HMC7044 JESD CLOCK GENERATOR

1UF

4.7K

10 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

4.7UF

0.1UF

DNI

4.7UF

11K

DNI

0.1UF

0

DNI

430

DNI

100PF

1UF4700PF

4700PF160PF

0

0

0

0

0

0

0

4.7K

100100

100

10K

0

100

100100

100

4.7UF4.7UF

10K

0.1UF

DNI

2.2UF

0DNI

DNI

HMC7044LP10BE

DNIR0402L

24.9

0.1UF

R0201L

100DNI

100

R0201L

24.9DNI

R0402L

0.1UF

R0402L

0

0.1UF

DNI

49.9R0402L

DNI

MABA-007159-000000

4.7UF

49.9

82PF100PF

CVHD-950X-122.880122.88MEGHZ

24

2200PF0.1UF120OHM

10UF

120OHM

0

49.9

49.9

DNI

0.1UF120OHM

0.1UF1UF1UF120OHM

19.2MEGHZ

0

0

100

49.9

0

100

0.01UF

0.01UF

0.01UF

49.9

0

100

0

0

49.9

49.949.9

49.9

100

0.01UF

49.9 49.9

0.1UF

R0201L0.1UF

100

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0

0

R0201L

DNI

0

100

0

0.1UF

0.1UF

100

100

49.9

49.949.9

100

0

0

DNI100

49.9

R0201L

R0201L

0

C358

R423

R50

R47 R49

C10

C9

R48

R46R45

C7

R33 R37

R41

R34 R38

R42

R43

R39R35

C8

R44

R40R36

C379

C353 C356

C355

R104

R106

R110

R111

R114

R115

R108

R109R105

C368

R112

C372

R463

R464

R460

R461

R462

R459

R528

R529

U11

C374 C376

C373 C375

C378

TP3

C377

R118

C380

TP2

R116

R117

R119

R103

C370

R107

R509

C367

R512R511

R510

C821

T14R508

C366

R507

J14

C352

R113

TP1

C371C369C359C357

E10

C354

E11

Y6

R232

R231

C282E3

C278C277C276

E2

Y4

R474

R469

R468

R467

C382

C383

R472

C384

R120

C385

C386

C381

R473

R470

R477

R478

R121

R471

C388

C387

R475

R476

R122

R123

CLKIN1_HMC7044_P

CLKIN1_HMC7044_N

CLKIN3_HMC7044_N

CLKIN2_HMC7044_P

CLKIN2_HMC7044_N

GPIO_2_HMC7044GPIO_1_HMC7044

VCC8_OUT

OSCOUT1_N

VCC7_PLL2

CLKIN0_HMC7044_N

GPIO_3_HMC7044

SPI_CLK

SYNC_HMC7044_FPGA

SYNC_HMC7044

SPI_CSN_HMC7044

SPI_MOSI

CLKIN0_HMC7044_P

CLKIN3_HMC7044_P

VCC1_VCO

VCC2_OUT

VCC3_SYSREF

VCC4_OUT

VCC5_PLL1

CPOUT1

OSCOUT1_P

OSCIN_EXT

GPIO_4_HMC7044

RESET_HMC7044

1V8

VCC6_OSCOUT

VCC9_OUT

CLKIN2_HMC7044_N

VDDA3P3_VCXO

OSCIN_EXTCPOUT1

CLKIN2_HMC7044_P

CLKIN3_HMC7044_P

CLKIN3_HMC7044_N

VDDA3P3_VCXO

CORE_CLK_C_P

JESD_SYSREF_FPGA_D_N

VCC8_OUT

CORE_CLK_C_N

JESD_REFCLK_FPGA_D_P

JESD_REFCLK_FPGA_C_N

JESD_REFCLK_FPGA_C_P

REF_CLK_IN_C_P

REF_CLK_IN_C_N

JESD_SYSREF_FPGA_D_P

JESD_REFCLK_FPGA_D_N

VCC8_OUT

VCC4_OUT

CORE_CLK_D_PCORE_CLK_D_N

JESD_SYSREF_FPGA_C_PJESD_SYSREF_FPGA_C_N

VCC8_OUT

VCC2_OUT

JESD_SYSREF_IN_C_P

JESD_SYSREF_IN_C_N

VCC9_OUT

VCC4_OUT

VCC4_OUT

REF_CLK_IN_D_N

REF_CLK_IN_D_P

VCC9_OUT

VCC2_OUT

JESD_SYSREF_IN_D_P

JESD_SYSREF_IN_D_N

46

7

3940

3637

4243

3334

2

1516

2425

2728

5556

5859

3250

315262

89

12

49

4748

44

PAD

5

35

19

34

1314

2223

2930

5354

6061

6465

20

18

6

10 21 26 41 51 57 68

1

45

11

63

3817

1

4

3

2

1 2

6766

GND

GND

VDDOUTCONTROL

PAD

VCC9

_OUT

CLKOUT12_NCLKOUT12

SCLKOUT13_NSCLKOUT13

GPIO4GPIO3 SCLKOUT11_N

SCLKOUT11CLKOUT10_N

CLKOUT10

VCC8

_OUT

CLKOUT8_NCLKOUT8

SCLKOUT9_NSCLKOUT9

GPIO2

VCC7

_PLL

2

CPOUT2

LDOBYP7

OSCIN_NOSCIN

LDOBYP6

OSCOUT1_N

OSCOUT1

CLKIN2_N/OSCOUT0_NCLKIN2/OSCOUT0

VCC6

_OSC

OUT

CLKIN0_N/RFSYNCIN_NCLKIN0/RFSYNCIN

VCC5

_PLL

1

CLKIN1_N/FIN_NCLKIN1/FIN

RSV

CLKIN3_NCLKIN3

CPOUT1

GPIO1

SCLKOUT7_NSCLKOUT7

CLKOUT6_NCLKOUT6

VCC4

_OUT

CLKOUT4_NCLKOUT4

SCLKOUT5_NSCLKOUT5

VCC3

_SYS

REF

SDATASCLKSLEN

VCC2

_OUT

CLKOUT2_NCLKOUT2

SCLKOUT3_NSCLKOUT3

LDOBYP5LDOBYP4

VCC1

_VCO

LDOBYP3LDOBYP2

BGABYP1

SYNCRESET

SCLKOUT1_NSCLKOUT1

CLKOUT0_NCLKOUT0

GND

GND

GND

GND

GND

SECPRIGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

SUP_VOLT

GND GNDOUTPUT

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

DECOUPLING HMC7044

11 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

120OHM

4.7UF

4.7UF

4.7UF

0.1UF1000PF

0.1UF1000PF

0.1UF1000PF

1UF0.01UF

4.7UF

4.7UF0.1UF

4.7UF0.1UF

1000PF

1000PF

1UF0.1UF1000PF

1000PF

120OHM

120OHM

120OHM

120OHM

120OHM

0.1UF

0.1UF

4.7UF0.1UF1000PF

120OHM

120OHM C546 C552 C558

C545 C551 C557

C550 C556

C543 C555

C548 C554

C541 C547 C553

C561 C564

C560 C563

C559 C562

C568

C567

C566

E15

E14

E16

E13

E19

E18

E17E12

C549

C542

C544

VCC5_PLL1

VCC6_OSCOUT

VCC7_PLL2

VCC1_VCO

VCC2_OUT

VCC3_SYSREF

VCC4_OUT

VCC8_OUT

VDDA3P3_CLK

VDDA3P3_VCO

VCC9_OUT

VDDA3P3_CLK

GND

GND

GND

GND

GND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

3.8V, 2.5A

10.7K | 38.3K | 23.2K6.34K | 31.6K | 12.7K

R350 | R348 | R349

WITHOUT LDOSWITH LDOS

RF SUPPLIES C

CLKOUT ON SYNC/MODE

2.65V, 1A

1.65V, 3A

1.3V, 3A

12 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

6.34K

0.1

6.8UH

3

470OHM AT 100MEGHZ

2.2UH47UF

ADP5054ACPZ

0.1UF

14

20

10K0.0027UF100K

100K

74

29

470OHM AT 100MEGHZ

23

47UF

28

49

68

10UF

1

10UF

2

10UF

27

10UF

71

DNI

64

47K 100K

65

60

604K

59

100K

70

DNI

72

47K

0

67

73

DNI

52

58

0.0033UF

61

20K

15

0.0033UF

16

20K

69

0.0027UF

66

10K

2526

13

1UF

12

1UF

53

10K 0

5451

0.01UF 56

23.2K

11

75

0.1UF

0.1UF

21

10K

44

10.2K

0.1UF

10

22.1K

47K32

DNI

33

DNI47K

22

10K

0 0.01UF

63

0 0.01UF

62

55

DNI27.4K

38.3K

37.4K DNI

4610K

47

DNI

0

24

0.01UF

18

SIA906EDJ-T1-GE3

43

DNI

10.7K

42

10.7K

47UF

48

57

0.47

4

5

6.8UH

2.2UH

19

6

47UF

7

47UF

17 35

47UF

470OHM

50

22UF

47UF

8

9

470OHM AT 100MEGHZ

34

47UF0.1

37

36

47UF

45

30

47UF

31

0.1

40

41

39

47UF

47UF

38

47UF

TP86

TP84

TP85

C897C895

C891

E24

R356

C886C884

TP83

C896

E27

C892

R357C889

E25

C893

R358

C894

E26

C887L12

C888C885

L13

L14

L15

R359

C890

TP82TP66TP65

R350

R351

Q1

C880R344

R352

R353

R354

R348

R355

C881R345

C882R346

R339

R341

R340

R337

U45

C879

R338

R342

C876

C877

C878

R349

C883R347R343

R336

C875

C870

R332C871

R333C872

R334C873

R335C874

R331

R329

TP64

R327

R325

R323

R330R326

R328

TP63

R324

R322

C866

C867

C868

C869

CLK_ADP5054

VREG_ADP5054_C

VDDA1P3_ANLG_C

VDDA2P65_C

VREG_ADP5054_C

VREG_ADP5054_C

VDD1P3_DIG_C

VDD1P3_DIG_C

VDDA1P65_ANLG_C

12P0V

VDDA3P8

EN_RF

EN_RF

EN_RF

4

152

PAD2

3

PAD16

45

43

44

98

54

272625

353433

42

17

7

6

242322

383736

1110

32

30

16

46

19

41

PAD

14

48

21

39

29

31

15

47

20

40

13

18

12

1

28

32

GND

GNDGNDGND

GND

GND

GNDGND

GND

GND

GND

GNDGNDGND

D2

D1

S2G2

D2

S1G1

D1

GND

EPAD

EN3

COMP3

FB3

VREG SYNC/MODE

VDD RT

FB1

COMP1

EN1

PVIN1PVIN1PVIN1

SW1SW1SW1

BST1

DL1

PGND

DL2

BST2

SW2SW2SW2

PVIN2PVIN2PVIN2

EN2

COMP2

FB2

CFG12

PWRGD

FB4COMP4

EN4

CFG34

BST4

PGND4PGND4

SW4SW4

PVIN4

PVIN3

SW3SW3

PGND3PGND3

BST3

GND

GND

GND

GNDGNDGNDGND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

1500MA

1.65V, 3A

1.3V, 3A

2.65V, 1A

6.34K | 12.7KWITHOUT LDOSWITH LDOS

R314 | R31310.7K | 23.2K

CLKIN ON SYNC/MODE

RF SUPPLIES D

13 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

72

10

10UF

10UF

47UF

0.0033UF

24

DNI

0.0027UF

0.01UF

SIA906EDJ-T1-GE3

22.1K

30

DNI

DNI

100K47K

0.0027UF10K

34

14

6

11

10UF

47K

23.2K

22UF

470OHM AT 100MEGHZ

47UF

47UF

9

470OHM AT 100MEGHZ

10UF

32

20

21

69

22

200K

23

499K

2

15

17

0

16

68

18

100K

29

0.0033UF20K

28

37

20K

40

1219

10K

4133

1UF

38

39

1UF

4

ADP5054ACPZ

13

3

0.1UF

0.1UF

48

10K

25

44

10.2K

58

0.1UF

42

DNI59

47K

47K60

DNI

10K

0 0.01UF

31

0

2627

DNI27.4K

6.34K

49

DNI

45

10K

0

3536

0.01UF

61

DNI

62

10.7K

55

10.7K

6.8UH

1

50

2.2UH

2.2UH

54

47UF

46

8

470OHM

0.47

5

7

51

47UF0.1

52

43

53

47UF

47

47UF

63

47UF

64

0.1

56

57

47UF

67

65

47UF

66

TP61

C841

TP4

TP80

TP81

TP79

C865C863

E21

C860

R319

C856C855

C864

C861

E23

R320C858

C862

R321

E22

C859

C857L9

L10

L11

R314

R315

Q7

C852R310

R318

R316

R317

C853R311

C854R312

R306

R307

R308

R304

C851

R305

R309

C849

C850

R313

U44C848

C843

R300C844

R301C845

R302C846

R303C847

R296

R299

TP59

R295

R292

R290

R298R294

R297

TP60

R293

R291

C839

C840

C842

VDDA1P3_ANLG_D

VDDA2P65_D

VREG_ADP5054_D

VREG_ADP5054_D

VDD1P3_DIG_D

VDD1P3_DIG_D

VREG_ADP5054_D

VDDA1P65_ANLG_D

12P0V

EN_RF

EN_RF

EN_RF

CLK_ADP5054

1

4

152

PAD2

3

PAD16

GNDGNDGNDGNDGND

GNDGND

GND

GNDGND

GNDGND

GND

D2

D1

S2G2

D2

S1G1

D1

GND

GND

EPAD

EN3

COMP3

FB3

VREG SYNC/MODE

VDD RT

FB1

COMP1

EN1

PVIN1PVIN1PVIN1

SW1SW1SW1

BST1

DL1

PGND

DL2

BST2

SW2SW2SW2

PVIN2PVIN2PVIN2

EN2

COMP2

FB2

CFG12

PWRGD

FB4COMP4

EN4

CFG34

BST4

PGND4PGND4

SW4SW4

PVIN4

PVIN3

SW3SW3

PGND3PGND3

BST3

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

1.8V, 0.6A

1.3V, 3A

1.8V, 0.6A

1.3V, 3A

RF SUPPLIES - LDO

3.3V, 0.4A

3.3V, 0.4A

3.3V, 0.4A

3.3V, 2A

14 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

0

0.1UF

10UF

5

10UF

0.01UF

1UF

3

DNI8.66K

10UF 1UF

3

10UF

10UF

6

0

1UF

ADM7154ACPZ-1.8

1

10UF

0.1UF

7

1UF

6

DNI

ADP1763ACPZ-1.3

1UF

ADM7154ACPZ-1.8

5

2

10UF

2

22UF 22UF

1

1UF

DNI

0.01UF DNI8.66K

10UF

1UF ADP1763ACPZ-1.3

22UF

1UF

22UF

10UF

10UF

4.7UF

0

10UF

ADP124ACPZ-3.3

0

0.1UF

4.7UF

1UF

DNI

1UF

0

10UF

1UF

DNI

ADM7154ACPZ-3.3

10UF

0.1UF 1UF

ADM7154ACPZ-3.3

10UF

0

DNI

1UF 1UF 1UF 0.1UF

10UF

0ADP7158ACPZ-3.3-R7

22UF 22UF

TP78

C836C831

U28

R493

C825

C362C361C828C829

JP1

JP3

JP2

JP5

JP4

TP77

R497

R495

C830

U26

C837C832

TP75

C833

U27

R492

TP50

C822

C826

R530

C823

R496

C838

TP76

C835

C834

R494

U25

TP130

C827

R531

C824

C819

C820

JP6

JP8

JP7

TP74TP73TP72TP71

TP69

C816

C808

C811

U24

C806

C802

R288C797

TP68

R491

C818

TP70

C815C809

C813

R489

C814

U43

C807

U23

TP67

R490

C817C812

C810

U22

C804

R488

C801

C805

C800C798

R287

C799

C795

C796

C803

VDDA2P65_D

VDDA1P8_D_N

VDDA1P8_D_P

VDDA1P8_D

VDDA1P3_ANLG_D_N

VDDA1P3_ANLG_D_P

VDDA1P3_ANLG_D

VDDA1P3_ANLG_SNS_D

VDDA1P65_ANLG_D

VDDA1P8_DVDDA2P65_D

VDDA1P3_ANLG_DVDDA1P65_ANLG_D

VDDA2P65_C

VDDA1P8_C_N

VDDA1P8_C_P

VDDA1P8_C

VDDA1P8_CVDDA2P65_C

VDDA1P3_ANLG_C_N

VDDA1P3_ANLG_CVDDA1P65_ANLG_CVDDA1P3_ANLG_C_P

VDDA1P3_ANLG_C

VDDA1P3_ANLG_SNS_C

VDDA1P65_ANLG_C

VDDA3P8

VDDA3P8

VDDA3P8

VDDA3P8

VDDA3P3_VCXO

VDDA3P3_VCO

VDDA3P3

VDDA3P8

VDDA3P8VDDA3P3

VDDA3P3_VCXO

VDDA3P3_VCO

VDDA3P8 VDDA3P3_CLK

VDDA3P8

VDDA3P3_CLK

VDDA3P3_N

VDDA3P3_P

VDDA3P3_VCO_N

VDDA3P3_VCXO_P

VDDA3P3_VCO_P

VDDA3P3_VCXO_N

VDDA3P3_CLK_N

VDDA3P3_CLK_P

12

856

4 PAD

73

12

856

4 PAD

73

321

87

64 PAD

5

6

1211109

4321

8

14

13

5 15

PAD7

16

6

1211109

4321

8

14

13

5 15

PAD7

16

12

856

4 PAD

73

EP

VINVIN

NC

EN

GND

VOUT_SENSEVOUTVOUT

GND

GND

GND

GND

GND

GND

GND

GND

GNDGNDGNDGND

GND

GND

PAD

EN

PG

SS

SENSEVOUTVOUTVOUTVOUT

VADJ

GND

VREG

REFCAP

VIN

VIN

VIN

VIN

GNDGND

GND

GND

GNDGND

GND

GND

GND

EP

VINEN

REFREF_SENSE

GND

BYP VOUTVREG

GND

GND

PAD

EN

PG

SS

SENSEVOUTVOUTVOUTVOUT

VADJ

GND

VREG

REFCAP

VIN

VIN

VIN

VIN

GND

GND

GND

GND

EP

VINEN

REFREF_SENSE

GND

BYP VOUTVREG

GND

GND

GND

GND

GND

GND

EP

VINVIN

VREG

REFREF_SENSE

EN

BYP

VOUT_SENSE

VOUTVOUT

GND

GND

GND

GND

EP

VINEN

REFREF_SENSE

GND

BYP VOUTVREG

GND

GND

EP

VINEN

REFREF_SENSE

GND

BYP VOUTVREG

GND

GND

GND

GND

GND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

FMC

15 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

ASP-134488-01ASP-134488-01

ASP-134488-01 ASP-134488-01

ASP-134488-01

ASP-134488-01 ASP-134488-01

ASP-134488-01

ASP-134488-01 ASP-134488-01

0

R1

P3

P3

P3 P3 P3

P3 P3 P3

P3 P3

JESD_SERDOUT0_C_PJESD_SERDOUT0_C_N

CORE_CLK_C_P

EPROM_A1

JESD_SYSREF_FPGA_C_P

GPIO_3_D

FMCA_SCLFMCA_SDA

12P0V

SYNC_HMC7044_FPGA

SYNCOUTB1_C_P

CLKIN0_HMC7044_NCLKIN0_HMC7044_P

3P3VAUX

SPI_CSN_HMC7044

OSCOUT1_POSCOUT1_N

RESETB_DRESETB_C

1V81V8

1V8

3P3VAUX

JESD_SERDOUT3_D_P

PG_C2MJESD_SERDOUT1_C_PJESD_SERDOUT1_C_N

JESD_SERDOUT2_C_P

JESD_SERDOUT0_D_P

JESD_SERDOUT2_C_N

JESD_SERDOUT1_D_P

JESD_SERDIN2_C_NJESD_SERDIN2_C_P


JESD_SERDIN1_D_N


JESD_SERDOUT3_D_N

JESD_SERDIN3_D_P


JESD_SERDIN1_C_P

JESD_SERDIN3_D_N

RX1_ENABLE_CRX2_ENABLE_C

TX2_ENABLE_C

TX1_ENABLE_D

JESD_REFCLK_FPGA_C_NJESD_REFCLK_FPGA_C_P

SPI_CSN_ADRV9009_C

SPI_CSN_ADRV9009_D

1V8

SYNC_HMC7044

JESD_SYSREF_FPGA_D_P

CORE_CLK_D_PCORE_CLK_D_N

RESET_HMC7044

GPIO_1_HMC7044GPIO_2_HMC7044

SYNCINB1_C_PSYNCINB1_C_N

SYNCINB1_D_PSYNCINB1_D_N

SYNCOUTB1_C_N

SYNCOUTB1_D_PSYNCOUTB1_D_N

GPINT_CGPINT_D

GPIO_0_CGPIO_0_D

GPIO_1_C

GPIO_2_D

GPIO_1_D

GPIO_2_C

GPIO_4_C

GPIO_4_HMC7044

SYNCINB0_C_N

SYNCINB0_D_NSYNCINB0_D_P

SYNCOUTB0_C_PSYNCOUTB0_C_N

SYNCOUTB0_D_NSYNCOUTB0_D_P

GPIO_5_CGPIO_5_D

GPIO_6_CGPIO_6_D

GPIO_7_C

GPIO_8_CGPIO_8_D

GPIO_7_D

CLKIN1_HMC7044_PCLKIN1_HMC7044_N

GPIO_3_HMC7044

GPIO_3_C

JESD_SERDIN1_D_P

CORE_CLK_C_N

JESD_SERDIN1_C_N

SPI_MOSISPI_MISO

JESD_SYSREF_FPGA_C_N

SYNCINB0_C_P

GPIO_4_D


JESD_SERDOUT0_D_N

JESD_SERDOUT3_C_P

TX2_ENABLE_D

TX1_ENABLE_C

JESD_SYSREF_FPGA_D_N

JESD_REFCLK_FPGA_D_NJESD_REFCLK_FPGA_D_P

JESD_SERDOUT3_C_N

JESD_SERDOUT1_D_N

JESD_SERDOUT2_D_P

EPROM_A0

SPI_CLK

RX2_ENABLE_DRX1_ENABLE_D

FAN_TACHFAN_PWM

JESD_SERDOUT2_D_N

C9

C1

D21D22

D24D25

G28

G38J39

D29

C24C25C26

G20

D15

C21

D16

A2

A19A18

A1

A4A5

A28A29

A36A37

A40

B1

B36

B32

B29B28

B9B8

B5B4

B2B3

B6B7

B10

B19

B22B23

B26

B30B31

B38B39B40

H5H6

H18

H21

H24

H36

H39

H7

H11

H23

H31

H35

H38H37

H2

H40

H1

K5K4

K2K3

K9

K12

K15

K18

K21

K24

K27

K30

K33

K36

K39

K8K7

K14K13

K17

K20K19

K23K22

K26K25

K29K28

K32K31

K35K34

K38K37

K40

K1

C39

C37

C2

C6C5

C12

C16

C32

C36

C38

C11C10

C15

C31

D36

D38

D35

D3

D10

D28

D37

D39

D9D8

D14

D30

D34

E1

E5

E8

E11

E14

E20

E29

E38

E40

E2

E7E6

E10E9

E13E12

E16E15

E19E18

E22E21

E25E24

E27

E31E30

E39

F2F3

F6

F18

F24

F27

F30

F33

F36

F39

F5F4

F7

F10

F17F16

F20

F23

F26F25

F29F28

F32F31

F35F34

F38F37

F1

F40

G1

G5

G11

G23

G29

G40

G16

G18

G21

G34G33

G39

J1

J4J5

J8

J11

J14

J17

J20

J23

J26

J29

J32

J35

J38

J40

J7J6

J10J9

J13J12

J16J15

J19J18

J22J21

J25J24

J28J27

J31J30

J34J33

J37J36

D1

D7

D13

A7

H9

H22F22F21

A8

A6

A3

A13A12A11

A9

A15

A17A16

A20

A14

A10

A22A23A24A25

A27A26

A31A32A33A34A35

A38A39

B13

B16B15B14

B18

B20B21

B34

B37

B11

C14C13

C4C3

C8C7

C33

B12

C17

C20C19

B27C28C29C30

C34B35 C35

D40

D2

D4D5D6

D12D11

D26D27

E34

E37E36

E32E33

E35

D20

D31

K10K11

G2G3

F9

F11

F14

G9

G6

F8

G4

G7

F12F13

F19

F15

G8

G10

G12G13G14G15

G19

G17

G22

G25G26

G24

G27

G32G31G30

G35G36G37

H3

H8

H14

H16

H13

H17

H15

H19H20

H25H26H27H28

H30H29

H32H33H34

K6

J2J3

H4

H12

H10 K16

A30

E17

D33

E28

E3E4

D32

E23

E26

C40

C18D17

D19D18

B24

A21

B33

B17

D23

C27

C22C23

B25

GND

GNDGND

RES0GNDGNDDP6_C2M_NDP6_C2M_PGNDGNDDP7_C2M_NDP7_C2M_PGNDGNDDP8_C2M_NDP8_C2M_PGNDGNDDP9_C2M_NDP9_C2M_PGNDGNDGBTCLK1_M2C_NGBTCLK1_M2C_PGNDGNDDP6_M2C_NDP6_M2C_PGNDGNDDP7_M2C_NDP7_M2C_PGNDGNDDP8_M2C_NDP8_M2C_PGNDGNDDP9_M2C_NDP9_M2C_PGNDGNDCLK_DIR

GNDDP5_C2M_NDP5_C2M_PGNDGNDDP4_C2M_NDP4_C2M_PGNDGNDDP3_C2M_NDP3_C2M_PGNDGNDDP2_C2M_NDP2_C2M_PGNDGNDDP1_C2M_NDP1_C2M_PGNDGNDDP5_M2C_NDP5_M2C_PGNDGNDDP4_M2C_NDP4_M2C_PGNDGNDDP3_M2C_NDP3_M2C_PGNDGNDDP2_M2C_NDP2_M2C_PGNDGNDDP1_M2C_NDP1_M2C_PGND

GND

GND

GNDVIO_B_M2CGNDHB18_NHB18_PGNDHB15_NHB15_PGNDHB11_NHB11_PGNDHB07_NHB07_PGNDHB01_NHB01_PGNDHA22_NHA22_PGNDHA18_NHA18_PGNDHA14_NHA14_PGNDHA11_NHA11_PGNDHA07_NHA07_PGNDHA03_NHA03_PGNDGNDCLK3_BIDIR_NCLK3_BIDIR_PGND

GND

GNDVADJGNDLA33_NLA33_PGNDLA31_NLA31_PGNDLA29_NLA29_PGNDLA25_NLA25_PGNDLA22_NLA22_PGNDLA20_NLA20_PGNDLA16_NLA16_PGNDLA12_NLA12_PGNDLA08_NLA08_PGNDLA03_NLA03_PGNDLA00_N_CCLA00_P_CCGNDGNDCLK1_M2C_NCLK1_M2C_PGND

VADJGNDHB20_NHB20_PGNDHB16_NHB16_PGNDHB12_NHB12_PGNDHB08_NHB08_PGNDHB04_NHB04_PGNDHB02_NHB02_PGNDHA19_NHA19_PGNDHA15_NHA15_PGNDHA12_NHA12_PGNDHA08_NHA08_PGNDHA04_NHA04_PGNDHA00_N_CCHA00_P_CCGNDGNDPG_M2C

GNDVADJGNDHB21_NHB21_PGNDHB19_NHB19_PGNDHB13_NHB13_PGNDHB09_NHB09_PGNDHB05_NHB05_PGNDHB03_NHB03_PGNDHA20_NHA20_PGNDHA16_NHA16_PGNDHA13_NHA13_PGNDHA09_NHA09_PGNDHA05_NHA05_PGNDGNDHA01_N_CCHA01_P_CCGND

3P3VGND3P3VGND3P3VGA1TRST_LTMS3P3VAUXTDOTDITCKGNDLA26_NLA26_PGNDLA23_NLA23_PGNDLA17_N_CCLA17_P_CCGNDLA13_NLA13_PGNDLA09_NLA09_PGNDLA05_NLA05_PGNDLA01_N_CCLA01_P_CCGNDGNDGBTCLK0_M2C_NGBTCLK0_M2C_PGNDGNDPG_C2M

GND3P3VGND12P0VGND12P0VGA0GNDGNDSDASCLGNDGNDLA27_NLA27_PGNDGNDLA18_N_CCLA18_P_CCGNDGNDLA14_NLA14_PGNDGNDLA10_NLA10_PGNDGNDLA06_NLA06_PGNDGNDDP0_M2C_NDP0_M2C_PGNDGNDDP0_C2M_NDP0_C2M_PGND

VIO_B_M2CGNDHB17_N_CCHB17_P_CCGNDHB14_NHB14_PGNDHB10_NHB10_PGNDHB06_N_CCHB06_P_CCGNDHB00_N_CCHB00_P_CCGNDHA23_NHA23_PGNDHA21_NHA21_PGNDHA17_N_CCHA17_P_CCGNDHA10_NHA10_PGNDHA06_NHA06_PGNDHA02_NHA02_PGNDCLK2_BIDIR_NCLK2_BIDIR_PGNDGNDVREF_B_M2C

GND

GND

GND

VADJGNDLA32_NLA32_PGNDLA30_NLA30_PGNDLA28_NLA28_PGNDLA24_NLA24_PGNDLA21_NLA21_PGNDLA19_NLA19_PGNDLA15_NLA15_PGNDLA11_NLA11_PGNDLA07_NLA07_PGNDLA04_NLA04_PGNDLA02_NLA02_PGNDCLK0_M2C_NCLK0_M2C_PGNDPRSNT_M2C_LVREF_A_M2C

GND D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

RESISTIVE DIVIDER TO TRANSLATE TO 1.8V LOGIC INPUT

VOLTAGE MEASURE ADC BOARD ID EEPROM

FAN CONNECTOR

16 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

10K

1K

10K

SML-P11MTT86R

1.37K

0.1UF 10UF

2.7K

DNI

SML-P11MTT86RSML-P11MTT86R SML-P11MTT86R

BSS138TA

10K

10K

1.37K 100

20K

DNI

27

27

DNI

DNI

M24C02-FDW6TP

10UF

10K

20K20K

1UF

20K 20K

DNI

20K

DNI0.1UF

10K

10K

10K

10K

10K

10KDNI

10K

10K

10K

10K

DNI

10K

DNI

AD7291BCPZ

10KDNI

10K

10K

10UF

R0402L

10K

SI2300DS-T1-GE3

47053-1000

R31

R29

R7

R32

R30

R28

DS4DS3DS2

R5

R11

C2

P9

U703

R21

R22

R27

Q2

DS1

R3R2 R4

R26R24

R25R23

C5 C6

U1

R12

R20

R19

R10

R18

R9

R17

R8

R16

R15

R6

R14

R13

C3

C4C1

Q3

EPROM_A1

FAN_PWM

FAN_TACH

12P0V

12P0V

VDDA1P3_ANLG_C

VDDA1P3_ANLG_D

VDDA1P8_C

VDDA3P3_CLK

PG_C2M

3P3VAUX3P3VAUX

VDDA1P8_D

EPROM_A0EPROM_A1

3P3VAUX3P3VAUX

FMCA_SCL

FMCA_SDA

3P3VAUX

VDDA3P3

VDDA3P3_VCXO

VDDA3P3_VCO

EPROM_A2

EPROM_A0

FMCA_SCL FMCA_SDA

1V8

21

3

C

A

C

A

C

A

4

7

8

5

6321

7

54321

201918

16

10

1415

17

PAD 69

8

1311

12

4

GND

GND

GND GND

GND

VSS

SCL

SDA

WC_N

E2E1E0

VCC

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

GND

PAD GND1GND

VDD VREF

SDA

ALERT

DCAP

SCLAS1AS0

VIN7VIN6VIN5VIN4VIN3VIN2VIN1VIN0

VDRIVE

PD_N/RST_N

GND

GND

GND

GND

G

S

DGND GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

AUXDAC_4AUXDAC_6

AUXDAC_7AUXDAC_5

AUXDAC_7AUXDAC_5

AUXDAC_4AUXDAC_6

GPIO AND AUX PINS

17 17

<DESIGN_VIEW>


1:1

A02_057106

<PTD_ENGINEER>

20021121-00010C4LF20021121-00010C4LF

20021121-00010C4LF20021121-00010C4LF

20021121-00010C4LF 20021121-00010C4LF

20021121-00010C4LF20021121-00010C4LF

P1

P6 P6

P4P4P1

P5 P5

GPIO_3P3_8_D

GPIO_3P3_3_D

AUXADC_2_D

GPIO_10_D

GPIO_3P3_2_DGPIO_12_D



GPIO_3P3_0_DGPIO_3P3_4_DAUXADC_0_D


GPIO_3P3_2_C


AUXADC_3_C

GPIO_11_CGPIO_13_CGPIO_3P3_3_C

AUXADC_1_D

GPIO_9_DAUXADC_3_D

GPIO_10_C

AUXADC_1_CAUXADC_2_CAUXADC_0_C


GPIO_9_C

GPIO_3P3_6_C

GPIO_12_CGPIO_13_DGPIO_11_D1

3579

2

97531

108642

97531

108642

9753

108642

10864

1

GND

GNDGND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

control code device function connector * see …...u14 syncoutb0_c_n_adrv vdd_interface_c...

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