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10/27/17K.I.T

byS Pramod Kumar

Assistant Professor,Dept.of ECE,KIT,

Tiptur

Images © 2006 D. M.Dhamdhare

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Contiguous Memory allocation,

Non-Contiguos Memory Allocation,

Paging, Segmentation, Segmentation with paging,

Virtual Memory Management,

Demand Paging, Paging Hardware, VM handler,

FIFO, LRU page replacement policies

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Managing the Memory Hierarchy

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Memory Fragmentation

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Contiguous Memory Allocation

In contiguous memory allocation each process is allocated a single contiguous area in memory

Issues: Memory protection, Relocation, Avoid fragmentation Faces the problem of memory fragmentation

Apply techniques of memory compaction and reuse in dynamic

Compaction requires a relocation register

Swapping

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Noncontiguous Memory Allocation

Portions of a process address space are distributed among different memory areas Reduces external fragmentation

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Logical Addresses, Physical Addresses, and Address Translation

Logical address: address of an instruction or data byte as used in a process Viewed as a pair (compi, bytei)

Physical address: address in memory where an instruction or data byte exists

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Approaches to Noncontiguous Memory Allocation

Two approaches: Paging

Process consists of fixed-size components called pages

Eliminates external fragmentation

The page size is defined by hardware

Segmentation

Programmer identifies logical entities in a program; each is called a segment

Facilitates sharing of code, data, and program modules between processes

Hybrid approach: segmentation with paging Avoids external fragmentation

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Paging

In the logical view, the address space of a process consists of a linear arrangement of pages

Each page has s bytes in it, where s is a power of 2 The value of s is specified in the architecture of the computer

system

Processes use numeric logical addresses

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Paging (continued)

Memory is divided into areas called page frames

A page frame is the same size as a page

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Paging (continued)

Notation used to describe address translation:s Size of a page

ll Length of a logical address (i.e., number of bits in it)

lp Length of a physical address

nb Number of bits used to represent the byte number in a logical address

np Number of bits used to represent the page number in a logical address

nf Number of bits used to represent frame number in a physical address

The size of a page, s, is a power of 2 nb is chosen such that s = 2nb

logical address effective physical address

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Example: Address Translation in Paging

32-bit logical addresses

Page size of 4 KB 12 bits are adequate to address the bytes in a page

212 = 4KB

For a memory size of 256 MB, lp = 28

If page 130 exists in page frame 48, pi = 130, and qi = 48

If bi = 600, the logical and physical addresses are:

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Example: Address Translation in Paging

ll=32-bit logical addresses

Page size of 4 KB 12 bits are adequate to address the bytes in a page

212 = 4KB

For a memory size of 256 MB, lp = 28

The logical and physical addresses are:

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Segmentation

A segment is a logical entity in a program E.g., a function, a data structure, or an object

Each logical address used in Q has the form (si, bi) si and bi are the ids of a segment and a byte within a segment

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Segmentation with Paging

Each segment in a program is paged separately

Integral number of pages allocated to each segment

Simplifies memory allocation and speeds it up

Avoids external fragmentation

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Summary

CPU has a relocation register to facilitate relocation

Allocation/deallocation of memory can lead to fragmentation: internal or external Noncontiguous allocation reduces external fragmentation

Requires use of the memory management unit (MMU) of CPU

Uses special techniques to make memory reuse fast and efficient

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Virtual Memory Basics

MMU translates logical address into physical one

Virtual memory handler is a software component Uses demand loading

Exploits locality of reference to improve performance

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Virtual Memory Basics (continued)

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Paged virtual memory systems

Segmented virtual memory systems

Rate at which process components have to be loaded

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Demand Paging

• Page frame for 0 to nf-1, the nf X s is the size of the memory

• MMU performs address translation using page tableLogical address (pi, bi) i.e 0 ≤ bi ≤s

= start address of the page frame containing page pi + bi

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Demand Paging Preliminaries

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Demand Paging Preliminaries (continued)

Memory Management Unit (MMU) raises a page fault interrupt if page containing logical address not in memory

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Demand Paging Preliminaries (continued)

A page fault interrupt

is raised because

Valid bit of page 3 is 0

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Demand Paging Preliminaries (continued)

At a page fault, the required page is loaded in a free page frame

Page-in and page-out: page I/O or page traffic

If no page frame is free, virtual memory manager performs a page replacement operation Page replacement algorithm

Page-out initiated if page is dirty (modified bit is set)

Effective memory access time in demand paging:

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Paging Hardware

Page-table-address-register (PTAR) points to the start of a page table

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Paging Hardware (continued)

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Address Translation and Page Fault Generation

Memory Protection

Memory protection violation raised if: Process tries to access a nonexistent page

Process exceeds its (page) access privileges

It is implemented through: Page table size register (PTSR) of MMU

Kernel records number of pages contained in a process in its PCB

Loads number from PCB in PTSR when process is scheduled

Prot info field of the page’s entry in the page table

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Address Translation and Page Fault Generation

Translation look-aside buffer (TLB): small and fast associative memory used to speed up address translation

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Address Translation and Page Fault Generation (continued)

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Superpages

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Superpages

TLB reach is stagnant even though memory sizes increase rapidly as technology advances TLB reach = page size x no of entries in TLB

It affects performance of virtual memory

Superpages are used to increase the TLB reach A superpage is a power of 2 multiple of page size

Promotion or demotion

Size of a superpage is adapted to execution behaviour of a process The VM handler combines some frequently accessed consecutive

pages into a superpage (called a promotion)

It disbands a superpage if some of its pages are not accessed frequently (called a demotion)

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Support for Page Replacement

Virtual memory manager needs following information for minimizing page faults and number of page-in and page-out operations: The time when a page was last used

Expensive to provide enough bits for this purpose

Solution: use a single reference bit

Whether a page is dirty

A page is clean if it is not dirty

Solution: modified bit in page table entry

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VM handler

The VM handler performs the following functions: Manage the logical address space of a process

Organize swap space and page table of the program

Perform page-in and page-out operations

Manage the physical memory

Implement memory protection

Maintain information for page replacement Paging hardware collects the information

VM handler maintains it in a convenient manner and form

Perform page replacement

Allocate physical memory to processes

Implement page sharing

Page replacement policies

A page replacement policy should replace a page not likely to be referenced in the immediate future

Two primary policies FIFO policy

Needs information about when a page was loaded in memory

Least-recently-used (LRU) policy

Needs information about when a page was last used

Needs a ‘time stamp’ of the last use of a page

The VM hardware and software has to collect additional information to facilitate page replacement decisions

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Page reference string

A page reference string is a sequence of page numbers containing the pages referenced by a process during an execution, e.g.

1, 5, 3, 1, 2, 4, 1, 5, 3.

If 3 page frames are allocated to a process, the page replacement algorithms will make the following decisions when page 2 is accessed FIFO page replacement algorithm would replace page 1

LRU page replacement algorithm would replace page 5

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• The misc info field contains a time-stamp

• For FIFO, it is the time of loading

• For LRU, it is thetime of lastreference

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FIFO page replacement policy does not exhibit stack property.10/27/17K.I.T

Page Replacement Policies (continued)

Virtual memory manager cannot use FIFO policy Increasing allocation to a process may increase page fault

frequency of process

Would make it impossible to control thrashing10/27/17K.I.T

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Summary

Basic actions in virtual memory using paging: address translation and demand loading of pages Implemented jointly by

Memory Management Unit (MMU): Hardware

Virtual memory manager: Software

Memory is divided into page frames

Virtual memory manager maintains a page table Inverted and multilevel page tables use less memory but are

less efficient

A fast TLB is used to speed up address translation

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Summary (continued)

Which page should VM manager remove from memory to make space for a new page? Page replacement algorithms exploit locality of reference

LRU has stack property, but is expensive

How much memory should manager allocate? Use working set model to avoid thrashing

Copy-on-write can be used for shared pages

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