computer science 37 lecture 16
TRANSCRIPT
-
8/4/2019 Computer Science 37 Lecture 16
1/22
1
Lecture16
Datapath fortheMIPSArchitecture
(Asingle-cycle implementation)
-
8/4/2019 Computer Science 37 Lecture 16
2/22
2
Registers
Register #
Data
Register #
Data
memory
Address
Data
Register #
PC Instruction ALU
Instruction
memory
Address
Figure5.1:AbstractviewoftheMIPSdatapath
-
8/4/2019 Computer Science 37 Lecture 16
3/22
3
State
elementCombinational logic
ClockMethodology
Whatcanwedosothatwecanread
thestateandwritebacktoitinthe
sameclockcycle?
CLOCK
READ WRITE
-
8/4/2019 Computer Science 37 Lecture 16
4/22
4
IncrementingtheProgramCounter
PC
Instructionmemory
Read
address
Instruction
4
Add
-
8/4/2019 Computer Science 37 Lecture 16
5/22
5
InstructionRegisters
Writeregister
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Writedata
ALUresult
ALU
Zero
RegWrite
ALU operation3
Figure5.7:Datapath forR-typeinstructions
-
8/4/2019 Computer Science 37 Lecture 16
6/22
6
Instruction
16 32
RegistersWriteregister
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Datamemory
Writedata
Readdata
Writedata
Sign
extend
ALUresult
Zero
ALU
Address
MemRead
MemWrite
RegWrite
ALU operation3
Figure5.9:Load/storedatapath
-
8/4/2019 Computer Science 37 Lecture 16
7/22
7
16 32Sign
extend
ZeroALU
Sum
Shiftleft 2
To branch
control logic
Branch target
PC + 4 from instruction datapath
Instruction
Add
RegistersWriteregister
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Writedata
RegWrite
ALU operation3
Figure5.10:Branchdatapath
-
8/4/2019 Computer Science 37 Lecture 16
8/22
8
PC
Instructionmemory
Readaddress
Instruction
16 32
Registers
Writeregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Sign
extend
ALUresult
Zero
Datamemory
Address
Writedata
Readdata
Mux
4
Add
Mux
ALU
RegWrite
ALU operation3
MemRead
MemWrite
ALUSrcMemtoReg
Figure5.12:Datapath withinstructionfetch.
-
8/4/2019 Computer Science 37 Lecture 16
9/22
9
PC
Instructionmemory
Readaddress
Instruction
16 32
Add ALUresult
Mux
Registers
Writeregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Shiftleft 2
4
Mux
ALU operation3
RegWrite
MemRead
MemWrite
PCSrc
ALUSrc
MemtoReg
ALUresult
ZeroALU
Datamemory
Address
Writedata
Readdata M
ux
Signextend
Add
Figure5.13:Singlecycledatapath forbasicMIPSinstructions
-
8/4/2019 Computer Science 37 Lecture 16
10/22
10
111
001
000
110
010
110
010010
ALU
control
input
addXXXXXXloadword00lwaddXXXXXXstoreword00sw
or100101OR10R-type
subtract100010subtract10R-type
subtractXXXXXXbrancheq01beq
setonless
than
101010slt10R-type
and100100AND10R-type
add100000add10R-type
ALUactionfunctoperationALU
Op
opcode
Figure5.14:ALUcontrolbitsforR-typeinstructions
-
8/4/2019 Computer Science 37 Lecture 16
11/22
11
OperationFunct fieldALU
op2
ALU
op1
1110101XXX1
0011010XXX1
0011010XXX1
1100100XXX1
110XXXXXX1X
0
0
X
0
0
X
1
0
X
0
0
X
X
X
X
000XX1
010XX1
010X00
Figure5.15:TruthtableforthethreeALUcontrolbits
-
8/4/2019 Computer Science 37 Lecture 16
12/22
12
ReviewofInstructionFormats
OP rs rt rd shamt funct
6bits 5bits 5bits 5bits 5bits 6bits
R-format:
OP rs rt address/immediate
6bits 5bits 5bits 16bits
I-format:
OP targetaddress
6bits 26bits
J-format:
Lookingatthedatapath,youllseemanycontrollinesthathavebeenleftdanglinguptonow.Weneedtofigureouthowtoset
thesevalues;theinformationforthiswillcomefrominstructions.
-
8/4/2019 Computer Science 37 Lecture 16
13/22
13
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[310]
Instruction [2016]
Instruction [2521]
Add
Instruction [50]
RegWrite
4
16 32Instruction [150]
0
Registers
Writeregister
Writedata
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata
Mux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [1511]
ALUcontrol
Shiftleft 2
PCSrc
ALU
AddALU
result
Figure5.17:Controllinesinthedatapath
DesigningtheControlUnit
-
8/4/2019 Computer Science 37 Lecture 16
14/22
14
PC
Instructionmemory
Readaddress
Instruction
Instruction [20 16]
Instruction [25 21]
Add
Instruction [5 0 ]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
RegDst
ALUSrc
Instruction [31 26]
4
16 32
Instruction [15 0]
0
0Mux
0
1
Control
AddALU
result
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Mux
1
ALUresult
Zero
PCSrc
Datamemory
Writedata
Readdata
Mux
1
Instruction [15 11]
ALUcontrol
Shiftleft 2
ALU
Address
Figure5.19:Addingthecontrolunittothedatapath
-
8/4/2019 Computer Science 37 Lecture 16
15/22
15
PC
Instructionmemory
Readaddress
Instruction
Add
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
RegDst
ALUSrc
4
16 32
0
0Mux
0
1
Control
AddALU
result
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
ALUcontrol
ALUAddress
Figure5.21:ExecutinganR-typeinstruction fetchfrominstruction
memoryandincrementthePC.
-
8/4/2019 Computer Science 37 Lecture 16
16/22
16
PC
Instructionmemory
Readaddress
Instruction
Add
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
RegDst
ALUSrc
4
16 32
0
0Mux
0
1
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
ALUcontrol
ALU
Address
Figure5.22:Readsourceregistersfromregisterfile.
-
8/4/2019 Computer Science 37 Lecture 16
17/22
17
PC
Instructionmemory
Readaddress
Instruction
Instruction [20 16]
Instruction [25 21]
Add
Instruction [5 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
RegDst
ALUSrc
Instruction [31 26]
4
16 32Instruction [15 0]
0
0Mux
0
1
ALUcontrol
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Mux
1
ALUresult
Zero
Datamemory
ReaddataAddress
Writedata
Mux
1
Instruction [15 11]
ALU
Shiftleft 2
Figure5.23:ALUperformsoperationonregistercontents.
-
8/4/2019 Computer Science 37 Lecture 16
18/22
18
PC
Instructionmemory
Readaddress
Instruction
Instruction [20 16]
Instruction [25 21]
Add
Instruction [5 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
RegDst
ALUSrc
Instruction [31 26]
4
16 32Instruction [15 0]
0
0Mux
0
1
ALUcontrol
Control
Shiftleft 2
AddALU
result
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
Instruction [15 11]
ALU
Address
Figure5.24:Finally,writeresulttodestinationregisterand
incrementthePC.
-
8/4/2019 Computer Science 37 Lecture 16
19/22
19
DesigningtheControlUnit
Thesettingofcontrollinesiscompletelydeterminedby
theinstructionopcode. Question: Howareopcodes determined?
0
1
0
Op0Op1Op2Op3Op4
0
1
0
Op5
1000beq
0001sw
0000lw
Opcode inbinaryInstruction
Usinganopcode asinput,youcandefineafunctionthatproduces
controlsignalsasoutputs(RegDst,ALUSrc,MemtoReg,etc).
Thecontrolunitinthiscaseissimplyacombinationalcircuit.
-
8/4/2019 Computer Science 37 Lecture 16
20/22
20
PerformanceofSingle-CycleMachines
Thegoal: haveeveryinstructionexecuted
inasingleclockcycle.
Thedrawback: theclockperiodischosen
toallowfortheexecutionofthelongest
instruction.
Variableclocks:isthisasolution?
-
8/4/2019 Computer Science 37 Lecture 16
21/22
21
AMulticycle Machine
Goal: breakuptheexecutionofaninstructionintosteps,
whereeachsteptakesoneclockcycletocomplete.
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
Maindifferences: onememoryunitfordataandcode,asingleALU,extraregisterstoholddatathatspassedfromoneclock
cycletothenext.
-
8/4/2019 Computer Science 37 Lecture 16
22/22
Figure5.33:Completedatapath foramulticycle
machine
Shiftleft 2
PC
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction
Mux
0
1
Mux
0
1
4
Instruction
Signextend
3216
Instruction
Instruction
Instruction
Instructionregister
ALUcontrol
ALUresult
ALU
Zero
Memorydata
register
A
B
IorD
MemRead
MemWrite
MemtoReg
PCWriteCond
PCWrite
IRWrite
ALUOp
ALUSrcB
ALUSrcA
RegDst
PCSource
RegWrite
Control
Outputs
Op
Instruction[31-26]
! " #
Mux
0
2
Jumpaddress [31-0]
$ ! " #
$
26 28Shiftleft 2
PC [31-28]
1
1 Mux
0
3
2
Mux
0
1ALUOut
Memory
MemData
Writedata
Address