computer organization & programming chapter 5 synchronous components
TRANSCRIPT
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Computer Organization & Programming
Chapter 5
Synchronous Components
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Clocks
Synchronization toolA clock allows separate circuits to do their work at precisely the same time.
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Set Reset Latch (SR Latch)
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Clocked latches
Control exactly when the S or R input is provided
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Clocked D latch
No need for separate variables R, S since they are mutually exclusive. D and D’ provide the same effect.
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Latch using Mux
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Standard representations
Latch loaded when clock is 1
Latch loaded when clock is 0(Note inversion bubble on CK)
Flip flop loaded when clock is changing from 0 to 1 (rising edge)
Flip flop loaded when clock is changing from 1 to 0 (falling edge)
Do we care? Not much. Just know that boxes that look like this hold a value
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8-bit register
Pin 1 drives clear on all the flip flopsPin 11 drives enable (CK) on all. Pin 11’s inverter serves as an amplifier also.
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FF with asynchronous Set & Reset
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Shift Register
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Right-Left Shift Register
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Synchronous Up-Counter
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Synchronous Up-Counter + Count Enable and Parallel Load
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Sequential Circuits
So far, all outputs have been determined completely by the current input.
Having a clock pulse allows us to determine the time at which each circuit fires.
Circuits that allow the output of a circuit to become an input to the next iteration of the circuit are called sequential circuits.
A sequential logic unit is also known as a Finite State Machine
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Finite State Machines
A finite state machine takes an input and a current state and produces an output and a next state
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Classical model of FSM
Abstraction of a delay mechanism. This will hold the value of the state output and release it as input in the next cycle.
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Example –Pseudo Random Numbers
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FSM for thePseudo Random Numbers
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FSM by a Graph
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FSM – Formal Definition
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State Transition Diagram
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Example
Look for the sequence ‘110’ (output ‘1’ when found)
Step 1 – Build the Graph
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Step 2 – write transition table
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Step 3 – Allocate State Values
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Step 4 – Get Functions
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Step 5 – Implement