Central Processing UnitThe organization of a simple computer with one CPU and two I/O devices

CPUBrain of the computer systemControls all internal and external devicesPerforms arithmetic and logic operationsOperates on binary data (0s and 1s)Controls usage of main memory and sequence of operationsArithmetic/Logic Unit, Control Unit and Registers Three main subsystems

Arithmetic/Logic Unit (ALU)ALU contains the electronic circuitry that executes all arithmetic and logic operations on data available to itData are inputs from designated registersArithmetic unit carries out addition, subtraction, multiplication and division at high speedsLogic unit enables CPU to make logical operations based on the instructions providedCan compare letters, numbers or special characters for less than, equal to and greater than conditions

RegistersRegisters are special purpose, high speed temporary memory unitsTemporary storage areas for holding information such as data, instructions, addresses and intermediate results of calculationsCPUs working memory, a special additional storage that offers advantage of speedWork under the direction of control unit to accept, hold or transfer data or instructionsInstruction addresses are stored in consecutive registers and executed sequentiallyControl unit reads an instruction in memory by a specific address in the register and executes itAX - the accumulator register (divided into AH / AL). BX - the base address register (divided into BH / BL)CX - the count register (divided into CH / CL)DX - the data register (divided into DH / DL) SI - source index registerDI - destination index registerBP - base pointerSP - stack pointer

Types of RegistersProgram Counter Keeps track of next instruction to be executedInstruction Register Holds the instruction register to be decoded by the control unitMemory Address Register Holds the address of the next location in memory to be accessedMemory Buffer Register Stores data either coming to CPU or transferred by CPUAccumulator Stores temporary results and results produced by ALUData Register Storing the operands and other dataThe length of register - Should have the same number of bits as its type eg memory address or the instruction (for memory address and instruction register)

Control UnitControl unit of the CPU contains circuitry that uses electrical signals to carry out, execute stored program instructionsLike an orchestra leader who himself does not play but directs others to playDirects other party of the system to execute instructions by communicating with ALU and memoryControls I/O devices and transfer of data to and from primary memoryInstructions are retrieved from primary storage one at a timeUses the instruction register for holding the current instruction and instruction pointer for holding the next instructionEach instruction is decoded, based on the instruction control unit co-ordinates the execution of the instruction with ALU and other componentsIssues commands to all elements of CPUDetermines what data is needed, where it is stored and where to store the results of operationAdministers the movement of large amount of data and instructions used by the computerTo maintain proper sequence of events, CU uses clock inputs

System BusBus is a set of connections between two or more components/devices, designed to transfer several/all bits of a word from a source to destinationPhysically, a bus is a number of parallel electrical conductors. These circuits are normally imprinted on printed circuit boards. Bus extends across system components, which can be tapped into bus linesBus has several lines, each line capable of transferring only one bit at a time8 lines needed to transfer 8 bits at a time over a busShared bus source can transmit data at one time but one or more can receive the dataA bus that connects CPU, memory and I/O is a System BusSystem bus can have 80 to 100 lines

System BusData lines Provides the path for moving data between system modules- Data lines are also called as data bus. Contains 8, 16 and 32 bits separate lines The number of lines in a data bus is called the width of the data busLarger the width better the performance of the computer systemAddress lines Used to designate the source of data for data bus For reading or writing information on to memory CPU need to provide address The address is provided by address busWidth of the memory specifies the maximum possible memory supplied by the systemControl lines Control the access to data and address busUsed for transmission of commands and timing signals between system modulesTiming signals indicate whether data and address information is valid or notCommand signals specify which operations to be performed

Main memory UnitHolds data and instructions for processingLogically an integral component of CPUPhysically a separate part placed on the mother boardStores program instruction or data as longs as program is in operationCPU accesses memory randomlyRAM and ROMRAM Directly provides required information to the processor. Block of sequential memory locations, each of which has a unique address determining the location and the locations contain a data element. Storage locations in main memory are addressed directly by CPUs instructionsVolatile in nature- information will be lost if power is switched offROM Read only memory Stores initial start-up instruction and routines in BIOS (basic input/output system) which can only be read by CPU Contents are not lost even power is switched off Non-volatile

Cache MemoryCache is a high speed, expensive piece of memory, used to speed up memory retrieval processStores data that is frequently used and accessedIncorporated in the processorL1 Cache closest to processor and is the primary cache, saves time consuming access to the main memory.Ranges from 8 to 64 KB, with more memory on new processorsFast because its integrated with the processorHandles command instructions (instruction cache) and data (data cache)L2 Cache Larger but slower in speed compared to L1, usually 64KB to 2 MB in size, also incorporated in CPU, information not found in L1 can be retrieved from L2L3 Cache Extra Cache built into motherboard between processor and main memory to speed up processing time, reduces the time gap between request and retrieve of data and instructions, quicker than main memory, can store up to 3 MB of storage

Communication amount various units Processor to Memory communicationInformation transfer - Processor places the address in memory address register through the address busissues a read command through control busMemory places retrieved data on data bus which is transferred to processorWriting to memory Processor places the address in memory address register through the address busThe processor transmits the data to be written through data busThe processor issues a write command to memory by the control busData is written in memory at address specified in memory address register

Speed mismatch between memory and processor, memory access is generally slower than CPU access time, so processor is forced to wait for the data. Cache memory improves the performance by being a intermediate buffer

Communication amount various units Processor to I/O devices communicationI/O devices are connected to CPU through system busDMA controller handles the data transfers on behalf of CPUControls the operation of the I/O deviceCan use system bus when CPU does not require it or free it when CPU requiresAllows peripheral devices to read or write data in main memory without going through CPUDirect Memory Access increases speed of I/O operations by taking over buses and eliminating CPU intervention

Instruction FormatAn instruction consists of an opcode and one or more operands, which may be addressed implicitly or explicitlyInstruction format specifies the layout of the bits allocated to the elements of an instructionInstruction length determines the flexibility of the machine. The decision on length depends on the memory size, memory org and memory transfer lengthTradeoff between no. of opcodes and addressing capability. More opcodes means more bits in the opcode field and this reduces the no. of bits for addressing for a fixed length format

Instruction FormatTypically first 3 bits represent the opcodeFinal 6 bits represent the operandsThe middle bit represent whether the operand is memory address or dataThree types of instructions :Data TransferArithmetic instructionsProgram ControlInput-Output

Instruction CycleBasic function of CPU is execution of a programProgram is a set of instructions stored in memoryCPU fetches instructions and executes within CPU, execution takes place in CPU registersFetch Cycle : Program counter MAR (address transferred to memory address register)MAR => memory => MBR (transferred through data lines by co-ordinated by CU)MBR => IR (transferred to Instruction Register)CU => IR (CU increments PC to point to next address register)In the IR, unique bi patterns that represent the machine language are extracted and sent to the decoder

Instruction CycleDecode Cycle : For recognizing which operation the bit patternThe operation code of the instruction is first read and then interpreted in the machine languageThe data required by the instruction (operand) is then transferred to DR (data register)Execute Cycle : Once transferred to DR, the execute cycle can beginComplex operations performed with four category of operationsCPU Memory : Data can be transferred from memory to CPU and vice versaCPU-I/O : Data transfer between I/O and CPUData processing : Perform arithmetic or logic operation on ALUControl : An instruction to change the sequence of operations may be specifiedStore Cycle : The results from the execution cycle are stored in memory buffer registerThen the results from MBR are stored back in the main memoryLoad ACC, memory : - IR => MAR (transferring address portion of the instruction from IR to MAR)MAR => MBR ( CPU transfers instruction located at MAR to MBR via data lines connecting CPU to memory)MBR => ACC (data transferred to ACC)

Next instruction is fetched and process starts again

Instruction SetCollection of processors operations is an instruction setIts hard wired (embedded) in the processorDetermines the machine language for the processorMore complicated the instruction set, the slower the processor worksProcessors differ from one another by their instruction setCompatible if same programs run on different processors (eg JVM)Program written for IBM may not run on apple computers as the architectures (processors) are differentEach processor has an unique instruction set, machine level programs written for one processor will not work on another processorAll OS and software are constructed within the boundaries of processors instruction setDesign of the instruction set becomes an important aspect of computer archetectureTwo types of architecture : Complex instruction set Computer, Reduced instruction set Computer

CISC and RISCCISC :Processors with extensive and complex Instruction setCould incorporate hard wired circuitary for performing square root or other complex operations in a single stepWriting instructions is easierSaves memory

RISC : Uses small highly optimized instructionsSmall number of instructions is faster than a large single instructionPipelining allows processor to work on different steps of instruction at the same timeMore instructions can be executed in a shorter period of timeBy overlapping fetch, decode and execute cycles of two or more instructionsUses large number of registers Processors are smaller, consume less power and run cooler than CISC processorsIdeal for mobile phone, PDA and digital came applications (embedded applications)Simple design also reduces the development time compared to CISC processor

Processor SpeedFaster the processor better the performaceSpeed of computer is determined by Clock speed of processor (eg 700 MHz)Speed and Size of data busA 32 bit 800 MHz processor can process 4 bytes simultaneously, 800 million cycles per secondWhile buying computer, a perfect match between the bus size, bus speed and the speed of clock should be consideredOther factors that limit the processors speed Transmission delays on the chip (in wires that connect components together on the chip)Heat build up on the chip