computer design basics digital logic design instructor: kasım sinan yildirim
TRANSCRIPT
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Computer Design Basics
Digital Logic DesignInstructor: Kasım Sinan YILDIRIM
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Introduction• Computer Specification– Instruction Set Architecture (ISA) - the
specification of a computer's appearance to a programmer at its lowest level
– Computer Architecture - a high-level description of the hardware implementing the computer derived from the ISA• The architecture usually includes additional
specifications such as speed, cost, and reliability.
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Simple Computer Architecture
• Simple computer architecture decomposed into:– Datapath for performing operations– Control unit for controlling datapath operations
• A datapath is specified by:– A set of registers– The microoperations performed on the data
stored in the registers– A control interface
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Datapaths• The set of registers
• A set of registers with common access resources called a register file
• Microoperation implementation• Buses - shared transfer paths• Arithmetic-Logic Unit (ALU) - shared resource for
implementing arithmetic and logic microoperations• Shifter - shared resource for implementing shift
microoperations
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• Four parallel-load registers• Two mux-based register selectors• Register destination decoder• Mux B for external constant input• Buses A and B with external
address and data outputs• ALU and Shifter with Mux F for
output select• Mux D for external data input• Logic for generating status bits
V, C, N, Z
Datapath Example
MD select 0 1MUX D
V
C
NZ
n
n
n
n
n
n
n
nn n
n
2 2
n
n
A data B data
Register file
1 0
MUX B AddressoutDataout
BusABus B
nn
Function unit
A B nG select
4
Zero Detect
MF select
nn
nF
MUX F
H select2
n
A BS2:0 || Cin
Arithmetic/logicunit (ALU)
G
BS
Shifter
H
MUX
0123
MUX
0123
0 1 2 3
Decoder
Load
Load
Load
Load
Load enable
WriteD data
D address2
Destination select
Constant in
MB select
A select
A address
B select
B address
R3
R2
R1
R0
Bus Dn
Data in
ILIR0 0
0 1
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MD select 0 1MUX D
V
C
NZ
n
n
n
n
n
n
n
nn n
n
2 2
n
n
A data B data
Register file
1 0
MUX B AddressoutDataout
BusABus B
nn
Function unit
A B nG select
4
Zero Detect
MF select
nn
nF
MUX F
H select2
n
A BS2:0 || Cin
Arithmetic/logicunit (ALU)
G
BS
Shifter
H
MUX
0123
MUX
0123
0 1 2 3
Decoder
Load
Load
Load
Load
Load enable
WriteD data
D address2
Destination select
Constant in
MB select
A select
A address
B select
B address
R3
R2
R1
R0
Bus Dn
Data in
ILIR0 0
0 1
Microoperation: R0 ← R1 + R2
Datapath Example: Performing a Microoperation
Apply 01 to A select to place contents of R1 onto Bus A
Apply 10 to B select to place contents of R2 onto B data and apply 0 to MB select to place B data on Bus B
Apply 0010 to G select to perform addition G = Bus A + Bus B
Apply 0 to MF select and 0 to MDselect to place the value of G onto BUS D
Apply 00 to Destination select to enable the Load input to R0
Apply 1 to Load Enable to force the Load input to R0 to 1 so that R0 is loaded on the clock pulse (not shown)
The overall microoperation requires1 clock cycle
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Arithmetic Logic Unit (ALU)• Decompose the ALU into:
– An arithmetic circuit– A logic circuit– A selector to pick between the two circuits
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Arithmetic Circuit Design
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Example: 4-bit Arithmetic Circuit
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Logic Circuit
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Arithmetic Logic Unit (ALU)
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The Shifter
4-Bit Basic Shifter
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Barrel Shifter
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Datapath Representation
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G Select, H Select, and MFin T of FS Codes
Datapath With Function Unit Select Codes
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The Control Word• The datapath has many control inputs• The signals driving these inputs can be defined and
organized into a control word• To execute a microinstruction, we apply control
word values for a clock cycle. – For most microoperations, the positive edge of the clock
cycle is needed to perform the register load
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Control Word
108
14
0
13
11
Bus D
Constant inn
n
MUX B1 0
D dataWrite
D address
A address B address
A data B data
8 x nRegister file
A B
Functionunit
n
n
n
MUX D
0 1
n nData in
Bus A
Bus B
R W
12AA
15D A
n
BA9
Address out
Data out
V
C
N
Z
7
MD 1
MB 6
4 FS
5
32
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108
14
0
13
11
Bus D
Constant inn
n
MUX B1 0
D dataWrite
D address
A address B address
A data B data
8x nRegister file
A B
Functionunit
n
n
n
MUX D
0 1
n nData in
Bus A
Bus B
RW
12AA
15DA
n
BA9
Address out
Data out
VC
NZ
7
MD 1
MB 6
4 FS
5
32
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Datapath Simulation
1 4 7 1 0 4 5
2 0 7 0
3 6 0 3 0
X X
2 0 7 0
3 6 0 2 3 0
14 1 2 0 10
2 0 0 1 X
18 18
1 255 2
2
3
4 12 18
5 0
6
7 8
Clock
DA
1 4
AA
2
BA
3 6
Constant_in 2
MB
Address_out
Data_out
FS
5
Status_bits
Data_in
MD
RW
reg0 0
reg1
reg2
reg3
reg4
reg5
reg6
reg7
7 8
5
108
14
0
13
11
Bus D
Constant inn
n
MUX B1 0
D dataWrite
D address
A address B address
A data B data
8 x nRegister file
A B
Functionunit
n
n
n
MUX D
0 1
n nData in
Bus A
Bus B
R W
12AA
15D A
n
BA9
Address out
Data out
V
C
N
Z
7
MD 1
MB 6
4 FS
5
32