computer-based project on vlsi design co 3/7dmh/ptiiavlsi/pdf/2004/c7lab8.pdf · 2004-04-21 ·...

Computer-based project in VLSI Design Lab Guide 8 - Semi-Custom Design

D M Holburn May 2004 C.4.3 135 C7lab8.doc

Computer-Based Project on VLSI Design Co 3/7

Laboratory Guide 8 - Semi-Custom Design

This laboratory guide provides an introduction to the techniques of Semi-Custom Design of IC layouts using Mentor Graphics' ICgraph tool, together with the subsidiary tools: ICplan, ICblocks, and ICcompact. All work is done within the ICstation environment. In this form of semi-custom design, we begin with the schematic design for ring, and lay out complete circuits in silicon using automated place-and-route procedures. The circuits we create will comprise sets of standard cells, each of which corresponds to a symbol in the schematic. One of these standard cells will be the nor2 layout cell created and verified in lab sessions 3, 6 and 7.

The result is a layout consisting of cells in neat rows with routing in between, providing power distribution and interconnecting signals as required. The entire design is placed within a power frame and equipped with pad drivers and bond pads at the periphery.

Although this design will not be sent for fabrication, it would be perfectly possible to do so. Instead, we shall satisfy ourselves with printing out a checkplot of the entire chip layout. It is expected that colour printer output will be available as well as monochrome laser printer output.

Orientation The laboratory guide is divided into three main sections.

In the first section (I), you will make preparations for carrying out the design, by building a library of layout cells and generating a design viewpoint for ICgraph.

In the second (II), you will construct a cell (named ring_flat) in which the constituent core gates are loaded in flattened form, i.e. they are placed and routed so that the electrical connections are connect, but in an arbitrary configuration, i.e. they are not grouped to correspond with the original schematic. You will then have an opportunity to experiment with via reduction and compaction. The second section also gives details of how to go about generating a colour hardcopy of the completed design.

All groups should carry out Sections I and II. Do Section III if there is time.

In the third section (II), you will generate a hierarchical layout (ring_hier) with the primitive gates grouped into functional blocks.

Editor modes There are three important modes in which ICgraph can be operated when being used for editing layouts.

When designing the nor2 cell, ICgraph was used in a mode known as Geometry Editing (GE). In GE mode, there are no direct restrictions on the kind of edits that can be carried out. We shall meet two new modes in this session.

Semi-custom design requires that ICgraph be run in a special mode, known as Correct by Construction (CBC). In CBC mode, the nature of the editing operations that can be carried out is significantly reduced so that layout changes carried out by hand do not cause connectivity violations (for example, the inadvertent deletion of a track or path). Naturally, layout changes must not violate design rules either.

ICgraph has an intermediate mode of operation known as Connectivity Editing (CE). In CE mode, no restrictions are placed on edits, but warnings are issued if an operation results in a change of connectivity.



In the version of Mentor (C.4) used for this project the conventions have been very slightly modified from the above. More recent versions of the package have reverted to the standard defaults.

Circuit blocks and interconnect All the essential elements of the proposed design are held in a top-level cell. Here these elements comprise circuit blocks and interconnect.

The circuit blocks are collections of cells which may have a direct correspondence with the separate components comprising the schematic design, e.g. ringarray, manchester_transmitter. However, such a correspondence is not always necessary. Often cells may be assembled in groups together more by virtue of their physical shape and size, or their nature (analogue, digital, memory etc) rather than their status within the schematic. The cells being referred to include I/O pads and drivers, which are conventionally positioned around the periphery of the cell. Since I/O pads are physically large, their number may determine the physical size of the cell far more directly than the core cells.

The interconnect comprises metal1 and metal2 wires which carry signals between the blocks, and between their constituent cells, as well as power supplies. Power supplies may be required to carry significant current, and are typically laid out as broad, gridded strips of metal1 or metal2, usually as the first stage of the automated routing process. The I/O pad drivers typically consume a large proportion of the total chip power requirement, and are therefore sited on or near a power frame constructed of broad metal interconnect, which distributes necessary power supplies to them. Power is brought onto the circuit by means of dedicated pads (in this case iovdd and iovss) which are joined directly to the power frame.

Cell library While most of the cells in this design will be taken from the library provided by Mietec, we shall use the nor2 cell studied, laid out and verified earlier in this project, to form the heart of the ringarray module. As a result of the detailed modelling work carried out in the last lab session, this cell is by now well characterised and suited to this requirement.



Section I – Creation of design viewpoint and library

In this section, you will make preparations for carrying out the design, by building a library of layout cells and generating a design viewpoint for ICgraph.

You should be logged in at a workstation as described in the Getting Started pamphlet, with Design Manager running. The current Mentor working directory should be $CBT_WD (which is the soft prefix for your $HOME/cbt directory), and you should select that same directory with the Navigator.

1. Determine the list of cells required. Before it is possible to build a chip layout, we need to assemble the complete set of

cells required into a single library. You will probably have determined the names of the full set of schematic cells embodied in the ring design earlier, but if necessary, carry out the following instructions in order to build the list of cells.

Within Design Manager, select the ring component icon in the Navigator window. Open the Component Hierarchy window by giving the command: (Menu bar) > Report > Open Hierarchy Window. When the dialogue box appears, OK it. You should recognise all the major cells on which you have worked: ringarray, manchester_transmitter, etc. Left click each in turn; using the right mouse button, give the command: (Popup Menu) > Show Levels. You should then be able to determine the lower-level schematic cells. All but one are marked with a diamond: ♦.

Compile a list, in alphabetical order, of the different low-level schematic cells in the design, including the I/O pad cells. Note that certain of the I/O pad cells are held as schematic, non-primitive cells, while others are primitive. Each cell name should appear just once on the list. Ensure also that your list contains both the power pads iovdd and iovss – these are essential.

If you wish you can generate a printed version of the full-length report. To do this, right-click in the Component Hierarchy window and select the command (popup) > Report. A HW Report text window should appear. Give the Design Manager command: (Menu) > File > Print > Print Document to generate a Postscript file for printing. If required, specify the printer as mgcps_a4.

Use mgcplot to preview and print the resultant document file.

2. Create a design viewpoint upon ring for ICgraph. In order to carry out the semi-custom layout, ICgraph needs a viewpoint to be

constructed upon the top-level schematic in the design. This requires DVE.

With the Design Manager Navigator window active and open on the $CBT_WD directory, select the ring component. Using the method of data-centred invocation, start up DVE upon that object. When DVE displays its menu, give the command: (Menu bar) > Mietec > Setup ICgraph. Observe the message "Mietec setup for ICgraph is done" in the message area.

We now save the newly constructed viewpoint with a distinguishing name. Give the command: (Menu bar) > File > Save Design Viewpoint > Save As...

In the New Name field, enter the name: icgraph_vpt1, and OK the dialogue box. The message area should show that the viewpoint was saved successfully. You can now close the DVE application and revert to Design Manager.

3. Construct the cell library using ICstation and generate a printed listing. Start up ICstation. Do this by double-clicking its icon in Design Manager's Tools

window, in order to avoid opening any specific cell.



We shall create a library named ringlib, and add to it the cells required for this design. Give the command: (Menu bar) > File > Library > Edit. Unfortunately, the Edit library dialogue seems to have some bugs, and this operation must be done in two passes. When the dialogue box appears, use the Navigator to ensure the current directory is $CBT_WD, then enter the name ringlib into the Library name field. Now we add cells to the ringlib library. Note that no cell data as such is actually placed in the library; the library consists of a list of references (directory paths) to the required set of cells which are mainly held in a centralised data base.

Make sure that Append and Save Library are selected. Click on the Navigator button adjacent to the Get Library Cells field. You should see a list box showing the cells available in the $CBT_WD directory, including nor2. Click on nor2, and OK the Navigator box. The nor2 cell path name should now appear in the listbox of the Edit Library dialogue box. If not, click Reset, and if necessary, re-enter the library name. Click the nor2 cell to select it (important!), and then OK the dialogue.

Give the command: (Menu bar) > File > Library > Edit once again, and make sure the library shown in the Library name field is ringlib. Click the Navigator button adjacent to Get Library Cells. Click the 4-arrow button within the Navigator, and enter: $MIETEC_LIB/layout/cmos24/cells in the Change Directory to: field. OK the Change Directory dialogue. You should now select the remaining cells required from the list that appears in the scrolling box. Do not select nor2 here -- your own version of this cell has already been inserted into the library. You can select additional cells without de-selecting the first by holding down the Control key before clicking on them. When you have selected the required cells, OK the dialogue box.

The path names for the complete set of chosen Mietec cells should now appear in the listbox of the Edit Library dialogue box. If not, click Reset, and if necessary, re-enter the library name. These must all be selected before you OK the Edit library dialogue, otherwise they will not be transferred into your library. To do this, click the first entry, scroll to the end of the list and Shift-click the final entry. Make sure the Append button and the Save Library buttons are checked, then OK the dialogue.

Give the command: (menu bar) Report > Library.., enter ringlib as the Library name and choose Window for the report target. Review the list of cells now contained in the library, and check that there are no omissions. Remedy if necessary.

For your report you will require a printed list of the library cells used.

To obtain this, switch temporarily to Design Manager. With ringlib selected in the Navigator window, click on (palette window) > HIERARCHY.

When the Open Hierarchy dialog appears, confirm the selection of $CBT_WD/ringlib, and OK the dialog. An IC Hierarchy window will appear. Right-click in it, and choose the command: (popup) > Setup > Display. In the resultant dialog, select Show Full Path and OK the dialog. The cells used in your library should be listed, complete with their paths. Verify that these are complete and appear to be correct before proceeding.

This listing is not printable in its present form, so in order to generate a printable report, right-click in the IC Hierarchy window and select the command (popup) > Report. A HW Report text window should appear. You can now use the Design Manager command: (Menu) > File > Print > Print Document to generate a Postscript file for printing. If required, specify the printer as mgcps_a4.

Use mgcplot to preview and print the resultant document file.



Section II Creating a flattened layout

In this section you will create a flattened layout for the ring design. All designers should complete this section. If time permits, continue with section II, which indicates how to build a hierarchical layout.

4. Create an empty cell to hold the complete layout. The top-level cell is the repository for circuit blocks (including I/O pads) and

interconnect. At this stage, we know very little about the organisation of its contents, but we must provide certain basic information about it for use by the automated tools. To create the cell, click the CREATE button in the Session palette menu. The Create Cell dialogue box appears. This is one of Mentor’s more complex dialogues – take care to enter the data correctly.

First set up the following conditions by clicking the corresponding buttons:

Cell type Block Connectivity Mode Connectivity Editing

The dialogue box should now expand to show a further area headed Logic Source Type, and will offer other options. Select:

Logic Source Type Eddm

Click on the Logic Loading Options button: a further dialogue box should open. Check that Viewpoint Directory is set to $CBT_WD; select the following option:

Logic Loading Flat

OK the dialogue. Now enter the information shown in the Create Cell dialogue box fields shown below. If you prefer, use the Navigator to select the name for the Attach Lib and Eddm schematic viewpoint entries.

Cell name ring_flat Attach Lib $CBT_WD/ringlib Process $MIETEC_CMOS24_IC_PROC Eddm schematic viewpoint $CBT_WD/ring/icgraph_vpt1

Finally, OK the dialogue box and observe the message area for possible diagnostic messages. If any errors are reported, consult a demonstrator. You may be invited to view a file named logic_load, which you should find in $CBT_WD. If you examine this file you will note warning references to dangling nets. These are in fact benign - they refer to the bond pads, to which external wired connections will be made when the circuit is connected up. ICgraph is simply warning you that at this point they are unconnected.

If all is well, a cell window should now open, but will appear blank as it contains no cells or interconnect at this stage.

Note: if you should subsequently decide to abandon this cell and start over, you should do the following:

• Close the design window by double-clicking its system icon, or otherwise. • Answer: Discard when prompted to save the cell. • Give the command: (Menu bar) > File > Unload Cells. • Return to the start of paragraph 4.



5. Promote the cell to CBC editing mode if necessary. Note that the cell’s Operation Config is typically CE, whereas we actually require CBC. In order to promote it to CBC, a set of Rules has to be specified for the process. Give the command: (Menu bar) > File > Load Rules... Check this contains the response: $MIETEC_CMOS24_IC_RUL and enter it if necessary. Then give the command: (Menu bar) > Context > Set Cell Config > Correct by Construction. Note that if this command is greyed out, your cell has already been created in CBC mode and does not need to be promoted. The status line should now show CBC.

You are now ready to create a Floorplan for the design.

6. Create a floorplan for the design. We now enter the ICplan module in order to create a floorplan for the design. The floorplan is simply a set of rectangular shapes identifying suitable sites to place the cells. The size and format of the shapes is determined automatically by the floorplanning utility by considering the number and size of the cells and pads that must be placed; however, no allocation of cells to sites is done yet.

Click the Place & Route item in the Session palette. The Place and Route palette should appear. Click on Autofloorplan. On this occasion, do not change any of the options; simply OK the dialogue box.

After a few moments, you should see a completion message generated by ICplan.

Press Shift+F8 in order to view the entire design. You should see a ring of I/O pad cells surrounding rectangular areas delineated in green; these represent rows on which the necessary core layout cells will be aligned. Their area has been calculated by ICplan to be sufficient for the cells required by the design.

7. Place the standard cells in the design. The remaining standard cells from the ringlib library must now be placed before

routing can take place. In the Place & Route palette, click the Std Cells item. The Standard Cell Placer Options dialogue box should appear. Normally no changes should be required to the entries in this dialogue; however, you should confirm that the following settings are in force, and select them if necessary.

Under the item Placement Method, check the box for the option: Initial+improve. For Wire Bias select Balanced. OK the dialogue box.

After a short period of processing, you should see the design screen update to show all the cells in automatically chosen sites. Zoom in and try to identify the key modules of the design (ringarray, 4bit_counter, shiftregister and nor2). Depending on the details of your own cells, you will almost certainly find that there is no clear distinction between them. This is typical of a flattened layout.

8. Automatically route the layout. It remains to insert the power frame, power rails, and wire all the core cells together

and to the I/O pads. This is accomplished with ICblocks, as follows.

Under the Autoroute heading in the Place & Route palette, click on All. A prompt bar should appear at the foot of the screen. For the moment do not change any of the options, but click OK. In approximately 30 seconds (dependent upon system loading) the circuit should be fully routed.

• Inspect the layout, and try to make an assessment of the efficiency of the placement and routing. Are the blocks regularly placed and the connections between them short and direct?



• Consider the set of nor2 cells which in the schematic are regularly interconnected to form the ring oscillator array. Has the regular schematic given rise to a regular layout? Is there any evidence of apparently unnecessary loops of interconnect?

• Make a note of the design’s total X and Y dimensions. Use the command: (Menu bar) > Report > Active > Context to determine this. You may wish first

to use (Menu bar) > Report > Setup Reports to direct your reports to a scrolling window rather than a popup box for ease of reading.

• Note also the number of via objects and nets generated by this operation.

• If you were unfortunate, ICblocks may have been unable to complete the routing. You may see a few yellow overflows, signifying connections that could not be made automatically. If you see these, the demonstrators may be able to advise on possible remedies. For the circuit to work, these problems need to be resolved, but this may be time consuming! We shall leave this problem for now, but return to it in Part III where we develop a fully hierarchical layout.

At this stage, it is wise to save the cell, using the command: (Menu bar) > File > Cell > Save Cell. Be sure to reserve it for edits before continuing.

9. Attempt to reduce the number of vias. The initial attempt at automatic placement and routing may need optimisation. For

example, the router may have used more vias than actually necessary in planning the crossovers (i.e. structures to allow wires to cross over other wires of the same material -- see the example in the diagram below).

Metal 1

Metal 2

BeforeVia Minimisation

Metal 1

After Via Minimisation

Metal 2

Metal 1

Metal 1

To minimise the vias, first make sure nothing is selected (press F2).

Now click on the Minim Vias item in the Place and Route palette, under the heading Autoroute. A prompt bar will appear. You must identify the sequence of routing levels at which minimisation will be attempted, and the maximum length of interconnect that will be searched. In this dialogue, levels 1 and 2 correspond to the layers Metal1 and Metal2 respectively.

Enter 1 in the From Routing Level field, and 2 in the To Routing Level field.

Enter 500 in the Maximum Length field, and OK the dialogue box.

When the minimisation is complete, execute the command: (Menu bar) > Report > Active > Context. Note the new number of vias.

Repeat the via minimisation operation, this time with From Routing Level set to 2, and To Routing Level set to 1.

Again determine the reduction in the via count achieved. 10. Compact the design. The initial layout is unlikely to be the most compact that can be achieved. ICplan is

fairly conservative about the size of the floorplan it constructs, to minimise the risk that routing cannot be achieved. The operation of via minimisation is likely further to



reduce the actual area required by the design. Compaction seeks to condense the design down to the minimum possible size, without modifying cells or connectivity, but purely by moving interconnect and eliminating unused space.

Often the principal determinant of the cell size is the number of I/O pads and drivers required. In these circumstances, little compaction may be achieved.

Compaction must be carried out independently in two perpendicular directions. This requires that the command be given twice, rather like for via minimisation.

Click the Compact item in the Place & Route palette (under the Autoroute heading). A prompt bar should appear. In the two scrolling list boxes within it, select Down for the Direction, and Centre for the Reference. OK the prompt bar. Compaction should begin.

When it completes, use the command: (Menu bar) > Report > Active > Context to determine the new dimensions, and compare them with the original values.

Repeat the Compact operation, this time setting the Direction parameter to Right. Note the improvement in compactness.

12. Generate a checkplot of the design. You will probably wish to generate a checkplot of the output. It should be possible to

direct one copy of this (per designer) to a colour printer. Please do not exceed this number. To generate a plot, follow the instructions below.

Give the command: (Menu bar) > MGC > Setup > Printer... When the Setup Printer - General dialogue box appears, enter in the Printer Name field:

mgcps_a4 for black-and-white output (standard laser printer) mgcpsa4_colour for colour output (colour laser printer)

Check that the Object type is set to design (correct if necessary). Leave the remaining fields in their default states, and OK the dialogue box.

In order to print the cell, you must have it visible on the screen, and the design window must be active.

Give the command: (Menu bar) > File > Print > Print Cell ... When the Print Cell dialogue box appears, first click the Setup Print... button.

A further, Setup Print dialogue box appears. In this box, set the Paper Width to 7 inches and the Paper Length to 10 inches. Leave the other settings at their default values and OK the dialogue box.

When the Print Cell dialogue is revealed again, you must re-enter the parameters for the paper to be used. Enter 7 in the Wid field, and 10 in the Len field. Units are inches in both cases. Now click the Set button just below the Len entry field. Click in sequence the Set buttons to the right of the Pages and the Scale fields.

Finally, click the Set Layers button. You are recommended to suppress printing of the Metal1.blkg and Metal2.blkg layers, since these occupy much of the layout and appear as a strongly hatched design on the plot, obscuring much of the detail below. To achieve this, you must select the list of layers you do wish to see, and ensure that this excludes the unwanted blockages. Starting at the top of the list in the scrolling box, use the cursor down key to navigate down to layer number 13, pressing the Shift key as you do so, in order to obtain an additive selection. Select also any other layers you particularly wish to include.

When you have finished selecting layers, OK the dialogue, and note that the Layers item is now set to Other in the Print Cell dialogue box. OK the Print Cell dialogue.



The plot will then be prepared and placed in a temporary directory. To send it to the colour printer, first check with a demonstrator that this service is currently available (it is provided via the computer operators who require prior warning of the need for colour output), then, from an xterm shell or similar, give the Unix command: mgcplot. The name of the cell you plotted should be listed. Follow the screen prompts to preview the plot (using ghostview) before committing it to paper.

When you are happy with the result, exit from ghostview and this time direct the output to the chosen printer. In due course the output will be made available by the computer operators.



Section III Creating a hierarchical layout

In this section we shall create a hierarchical layout (ring_hier) for the ring design.

This requires us to interact with the list of schematic cells used in the design and partition them into groups. This is done by means of a hierarchy window.

We shall construct the layout in the form of five distinct blocks. These will comprise:

• the four-bit counter (ring_count); • the Manchester transmitter (ring_transmitter); • the set of identical NOR gates making up the ring oscillator (ring_array); • the Manchester receiver (ring_receiver); • a small block containing one remaining logic gates (ring_glue).

We shall lay out the floorplans for each of these blocks interactively rather than automatically as in section II.

The key stages are as follows:

• Create an empty cell to hold the hierarchical layout • Use the hierarchy window to expose the hierarchical structure of the design • Identify cells to go in the ring_count block; place, route and save ring_count • Identify cells to go in the ring_transmitter block; place, route and save • Identify cells to go in the ring_array block; place, route and save • Identify cells to go in the ring_receiver block; place, route and save • Assign remaining cell to the ring_glue block; place, route and save ring_glue • Place the five new blocks in the ring_hier • Add ports and route interconnect to complete ring_hier

Along the way you may possibly meet minor problems relating to placement of cells and routing. It should become apparent that there are quite serious limits to the capabilities of even the best automated layout tools.

The remaining sections of this guide are quite long, though the activity itself should not take more than 45 minutes – provided no errors are made! Once cell creation is under way it is quite difficult to break off the work and resume in a later session, so allow yourself an hour or more to carry out this activity, with allowance for a restart. Also, if an error is made during cell creation, it is often difficult to re-enter the procedure. If you do go wrong you are strongly recommended to restart with a new empty cell. In these circumstances:

Follow the instructions at the end of paragraph 13

Please consult a demonstrator if in any doubt.



13. Create an empty cell to hold the hierarchical layout. As in section II, we must provide certain basic information about the content of the

top-level cell for use by the automated tools. To create the cell, click the CREATE button in the Session palette menu to call up the Create Cell dialogue box. If you have just completed creating the ring_flat design, several of the settings remain the same as in section II - the changes are italicised for emphasis.

First set the following conditions by clicking the corresponding buttons:

Cell type Block Connectivity Mode Connectivity Editing

The dialogue box should now expand to show a further area headed Logic Source Type, and will offer other options (NB if you continue without a break after ring_flat, the extra options will aready be visible). Select:

Logic Source Type Eddm

Click on the Logic Loading Options button: a further dialogue box should open. Check that Viewpoint Directory is set to $CBT_WD; select the following option:

Logic Loading Full Hierarchy

OK the dialogue.

Now enter the information (as required) in the fields shown below.

Cell name ring_hier Attach Lib $CBT_WD/ringlib Process $MIETEC_CMOS24_IC_PROC Eddm Schematic Viewpoint $CBT_WD/ring/icgraph_vpt1

OK the dialogue box and observe the message area for possible diagnostic messages. If any errors are reported, consult a demonstrator. As with ring_flat, you may be invited to view the file named logic_load, which you should find in $CBT_WD.

A cell window should open, as before, but will appear blank as it contains no cells or interconnect at this stage.

Note: as before, if you should subsequently decide to abandon the cell and start over, you should do the following:

• Close the design window by double-clicking its system icon, or otherwise. • Answer: Discard when prompted to save the cell. • Give the command: (Menu bar) > File > Unload Cells. • Return to the start of paragraph 13.

14. Load the Rules in preparation for promoting the cell to CBC editing mode.

At a later stage in the procedure we shall need to switch between CE mode and CBC mode, and back again. For convenience, we shall load the Rules file here. Give the command: (Menu bar) > File > Load Rules... If necessary, enter the response: $MIETEC_CMOS24_IC_RUL.

You are now ready to open the hierarchy window.



15. Open the hierarchy window The hierarchy window is a text window which lists all the cells and blocks of cells

involved in a design, in a form which emphasises the hierarchical relationships between them. The instance name corresponding to each cell and its component name are shown in the window. A cell can be selected in the hierarchy window, and the same cell will be selected in the design window. Each cell has a code letter describing its status, as follows:

• E signifies an external cell (I/O pad driver) • S signifies a standard layout cell • B indicates a block, itself composed of cells or blocks. • No letter signifies that the cell has been placed on the layout.

The code letter is removed when the cell is placed on the layout, but restored if the cell is removed from the layout by means of the Unplace command. The hierarchy window is controlled by commands in the Floorplan palette.

Click on the Floorplan item in the Session palette. The Floorplan palette should be displayed. Click on the Open Window item, under the heading Hierarchy. When the window opens, you will need to resize it so that both it and the design window are visible. Rearrange the windows so that the hierarchy window is narrow and positioned at the left, while the cell window is to the right and occupies the remaining space. You should see in the hierarchy window references to the top-level cells involved in the ring design; these should include ring_oscillator, 4bit_counter, manchester_receiver and manchester_transmitter.

Note: had you elected for flattened logic loading in paragraph 13 rather than the hierarchical mode, these references would not have been present; the complete set of their schematic sub-cells would have been listed instead.

You should also see a single instance of nor2 - the single test gate in the ring design.

The paragraphs that follow are somewhat lengthy and at first reading they may seem rather complex. However, their objective is simply to create laid-out versions of the four main blocks of logic – ring_count, ring_transmitter, ring_receiver and ring_array, each comprising standard cells and interconnect. Thus, paragraphs 16 to 20 represent the creation of ring_count; paragraphs 21 to 25 are effectively a repeat of the same procedure to create ring_transmitter. Paragraphs 26 to 28 are concerned with creation of ring_array, and paragraphs 29 to 33 are concerned with the final block, ring_receiver. Paragraphs 34 to 37 deal with the remaining logic, ring_glue. Finally, paragraphs 38 to 42 puit the finishing touches to the design. Since later sections effectively repeat procedures already carried out in paragraphs 16 – 20, some are presented in a more concise form.

You are now ready to generate a cell block (ring_count) representing the 4 bit counter component, for later

placement in ring_hier.



16. Flatten the 4bit_counter cell. In the hierarchy window, click on the 4bit_counter cell to select it. Click in the

design window to reactivate it and its associated palette. Click on the Flatten item in the Floorplan palette (under the Hierarchy heading). A prompt bar should appear. In the bar, use the scrolling list boxes to choose the following options:

cell_position noplace copy norouting

OK the prompt bar. Observe in the hierarchy window that the four bit counter has been flattened into its constituent sub-cells, all coded S.

17. Combine the standard cells into a new block. We shall now gather together all the cells from the flattened 4bit_counter and

assemble them into a new block. Prior to doing this it is necessary to detach the current library. With the design window active, give the command: (Menu bar) > File > Library > Detach.

Now, in the hierarchy window, select all cells bearing the code letter S. When you have done this, check in the status bar that 16 cells have been selected (Sel: item).

Re-activate the design window and its associated Floorplan palette. Click on the Partition item in the Floorplan palette (under the Hierarchy heading). In the resulting prompt bar, enter ring_count in the cell_name field. Select the noplace setting for cell_position. OK the prompt bar.

Observe the resulting changes in the hierarchy window, and in particular, the presence of a new part, ring_count.

18. Lay out a floorplan shape for the cell ring_count. We shall interactively lay out a floorplan shape for the new block.

Make sure ring_count is selected in the Component Hierarchy window. Then activate the design window and click on the Add Fp Shape item in the Floorplan palette. In the prompt bar, use the Tab key to outline in red the Shape Extent item. Now, in the design window, with the Select button depressed, drag out a rectangular shape. Note that a small percentage figure is shown by the cursor; continue dragging until this reaches at least 250%. This figure indicates the relative size of the floorplan compared with the net area (excluding interconnect) of the cells it must accommodate. The greater the figure, the smaller the risk that auto-routing will fail.

Now click on the Link item in the Floorplan palette (FP Edit heading). This extracts the cells selected in the hierarchy window into the newly created floorplan shape; the shape will acquire the name ring_count.

19. Change the editing context to ring_count and set up the cell. We must now complete the creation of the ring_count cell and save it so it can later

be placed in the top-level ring_hier cell.

Change the editing context to ring_count by giving the following commands: (Menu bar) > Context > Hierarchy > Peek , and OK the resulting prompt bar. The ring_count cell should appear shaded.

Now give the command: (Menu bar) > Context > Hierarchy > Set context. Click within the ring_count floorplan shape. Observe in the title bar of the design

window that the context has now changed from ring_hier to ring_count, and that the floorplan shape is now outlined in green.

Re-attach the library with the following command:



(Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib cell library. OK the dialogue box.

Now use Autofloorplan, Autoplace, & Autoroute to complete the cell. In the Floorplan palette, click on:

• Autofloorplan and OK the dialogue box; • Back, followed by Place & Route (to select the Place & Route palette); • Std Cells (under Autoplace), and OK the dialogue box.

At this stage press Shift+F8 if necessary to view the entire layout. The cells have been placed, but interconnections still need to be routed. You should see networks of yellow overflow links, representing the set of interconnections still to be resolved. Continue with the following commands, from the Floorplan palette:

• Ports (under Autoplace), and OK the dialogue box; • All (under Autoroute), and OK the prompt bar.

Note that ports are virtually invisible when placed at this stage, but they can be seen as small rectangles within the green border around the floor plan shape.

You should now observe a placed and routed block. In most cases ICblocks can automatically generate all the required interconnections using metal1 and/or metal2, but if the structures are complex there is a risk this operation may fail, and you will continue to see yellow overflows. Consult a demonstrator if this is the case.

Save the cell at this point: (Menu bar) File > Cell > Save Cell.

20. Change editing context temporarily back to ring_hier. Give the two following menu commands: (Menu bar) > Context > Hierarchy > Set Context Up, and OK the prompt bar.

Make sure the cell ring_count is selected and the design window is activated before giving the command:

(Menu bar) > Context > Hierarchy > Unpeek. Unplace the ring_count part by giving the command: (Menu bar) > Objects > Unplace. Now press function key F2 to de-select all objects.

You are now ready to generate a cell block (ring_shift), representing the shift register component,

for later placement in ring_hier.



21. Flatten the manchester_transmitter block and the shiftregister block within. In the hierarchy window, click on the manchester_transmitter cell to select it. Click

in the design window to reactivate it and its associated palette. Click on the Flatten item in the Floorplan palette (under the Hierarchy heading). In the prompt bar, choose the following options:


OK the prompt bar. Observe in the hierarchy window that the shift register has been flattened into two constituent sub-cells, both coded S, and a further block, shiftregister (coded B). This block must also be flattened, using the same approach.

Click on the shiftregister block. Reactivate the design window, and click on the Flatten item in the Floorplan paletter. Set the prompt bar options as before, and OK the prompt bar. The shiftregister block should now have been flattened into its constituent cells, all coded S.

22. Combine the standard cells into a new block. We shall now gather together all the standard cells from the flattened shiftregister

schematic and assemble them into a new block ring_shift.

In the hierarchy window, select all cells bearing the code letter S. When you have done this, check in the status bar and by comparison with your written list that all required cells have been selected. There should be eight cells.

Re-activate the design window and its associated Floorplan palette. Detach the current library by giving the command: (Menu bar) > File > Library > Detach. Click on Partition; in the resulting prompt bar, enter ring_transmitter in the cell_name field. Select the noplace setting for cell_position. OK the prompt bar. Observe the appearance of a new part, ring_transmitter.

23. Lay out a floorplan shape for the cell ring_transmitter. We shall interactively lay out a floorplan shape for the new block.

Make sure ring_shift is selected in the Component Hierarchy window. Then activate the design window and click on the Add Fp Shape item in the Floorplan palette. In the prompt bar, use the Tab key to outline in red the Shape Extent item. In the design window, with the Select button depressed, drag out a rectangular shape until its size reaches at least 250%. Now click on the Link item in the Floorplan palette (FP Edit heading). This extracts the cells selected in the hierarchy window into the newly created floorplan shape; the shape will acquire the name ring_transmitter.

24. Change the editing context to ring_transmitter and set up the cell. Change the editing context to ring_transmitter by giving the following commands:

(Menu bar) > Context > Hierarchy > Peek , and OK the resulting prompt bar. The ring_transmitter cell should appear shaded.

Now give the command: (Menu bar) > Context > Hierarchy > Set context. Click within the ring_transmitter floorplan shape. Observe in the title bar of the

design window that the context has now changed from ring_hier to ring_transmitter, and that the floorplan shape is now outlined in green.

Re-attach the library with the following command: (Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib

cell library. OK the dialogue box.



Select the Floorplan palette: click on Autofloorplan and study the dialogue which appears. OK the dialogue box.

ICblocks should now create a compact, single or double row of cell sites. Consult a demonstrator if this is not the case.

Now give the following commands from the Floorplan palette:

• Back, followed by Place & Route (to select the Place & Route palette); • Std Cells (under Autoplace), and OK the dialogue box; • Ports (under Autoplace), and OK the dialogue box; • All (under Autoroute), and OK the prompt bar.

You should now observe a placed and routed block with all overflows resolved. Study it carefully and try to trace the key signal flows. Save the cell at this point:

(Menu bar) File > Cell > Save Cell.


Make sure the cell ring_transmitter is selected and the design window is activated before giving the command:

(Menu bar) > Context > Hierarchy > Unpeek. Unplace the ring_transmitter part by giving the command: (Menu bar) > Objects > Unplace. Now press function key F2 to de-select all objects.

You are now ready to generate a cell block (ring_array) representing the ring oscillator component for later placement in ring_hier.

26. Flatten the ring_oscillator schematic. Return to the hierarchy window, and select the ring_oscillator schematic object.

Note that this is labelled B (implying that it is an unplaced block cell). We shall now create a floorplan shape for the ring_oscillator schematic, so generating a ring_array layout cell.

With the design window active, switch to the Floorplan palette (click the Back item in the Place & Route palette, then click Floorplan in the IC palette).

Click on the Flatten item in the Floorplan palette (under the Hierarchy heading). In the prompt bar, choose the following options:


OK the prompt bar. Observe in the hierarchy window that the ring oscillator has been flattened into its constituent nor2 sub-cells, all coded S.

27. Combine the standard cells into a new block and generate a floorplan shape. We shall now gather together all the standard cells from the flattened ring oscillator

schematic and assemble them into a new block ring_array.

In the hierarchy window, select all the nor2 cells from the ring oscillator.



Remember that your design contains an additional nor2 gate, provided as a simple test structure. We shall place this in a different cell (ring_glue), not ring_array.

Since the ring devices are in a sub-cell, and the test device is not, you can easily distinguish them. The ring gates will have instance identifiers of the form: I$XXX/I$YYY, while the test gate will have a simpler identifier of the form: I$ZZZ.

Use this information to help you select the ring oscillator gates only. When you have done this, check in the status bar (and by comparison with your written list) that all the required cells have been selected and there are no surplus cells. The number of selected cells and the number you designed in your ring_oscillator schematic must match.

Re-activate the design window and its associated Floorplan palette. Detach the current library by giving the command: (Menu bar) > File > Library > Detach. Click on Partition; in the resulting prompt bar, enter ring_array in the cell_name field. Select the noplace setting for cell_position. OK the prompt bar.

Observe the appearance of a new part, ring_array.

Generate a floorplan shape by clicking on Add Fp Shape. Press Tab to select Shape Extent in the prompt bar. As before, use the mouse to drag out a rectangular shape until the percentage readout is at least 250%. Click on the Link item in the palette; the name ring_array should appear in the shape. Peek into the ring_array cell, set the editing context and re-attach the library by giving the following three commands:

(Menu bar) > Context > Hierarchy > Peek , and OK the prompt bar; (Menu bar) > Context > Hierarchy > Set Context, and click within the new shape.

(Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib cell library. OK the dialogue box.

You are now ready to place and route standard cells for ring_array. 28. Place and route the ring_array cell. Click on Back, then on the Place & Route item in the IC palette to display the Place

& Route palette.

In the Place & Route palette, click on the following:

• Autofloorplan and OK the dialogue box; • Std Cells (under Autoplace) and OK the dialogue box; • Ports (under Autoplace) and OK the dialogue box; • All (under Autoroute), OK the prompt bar and wait.

Save the completed ring_array cell, using (Menu bar) > File > Cell > Save Cell. Restore the context to ring_hier, and unpeek, by giving the commands:

(Menu bar) > Context > Hierarchy > Set Context Up, and OK the prompt bar; (Menu bar) > Context > Hierarchy > Unpeek.

Unplace the ring_array cell by ensuring it is selected, then giving the command: (Menu bar) > Objects > Unplace. Press F2 to unselect all objects.

You are now ready to generate a cell block (ring_receiver), for later placement in ring_hier.



29. Flatten the manchester_receiver cell. In the hierarchy window, click on the manchester_receiver cell to select it. Click in

the design window to reactivate it and its associated palette. Click on the Flatten item in the Floorplan palette (under the Hierarchy heading). A prompt bar should appear. In the bar, use the scrolling list boxes to choose the following options:


OK the prompt bar. Observe in the hierarchy window that the four bit counter has been flattened into its constituent sub-cells, all coded S.

30. Combine the standard cells into a new block. We shall now gather together all the cells from the flattened ring_receiver and

assemble them into a new block. Prior to doing this it is necessary to detach the current library. With the design window active, give the command: (Menu bar) > File > Library > Detach.

Now, in the hierarchy window, select all cells bearing the code letter S. When you have done this, check in the status bar that the expected 14 cells have been selected (Sel: item).

Re-activate the design window and its associated Floorplan palette. Click on the Partition item in the Floorplan palette (under the Hierarchy heading). In the resulting prompt bar, enter ring_receiver in the cell_name field. Select the noplace setting for cell_position. OK the prompt bar.

Observe the resulting changes in the hierarchy window, and in particular, the presence of a new part, ring_receiver.

31. Lay out a floorplan shape for the cell ring_receiver. We shall interactively lay out a floorplan shape for the new block.

Make sure ring_receiver is selected in the Component Hierarchy window. Then activate the design window and click on the Add Fp Shape item in the Floorplan palette. In the prompt bar, use the Tab key to outline in red the Shape Extent item. Now, in the design window, with the Select button depressed, drag out a rectangular shape. Note that a small percentage figure is shown by the cursor; continue dragging until this reaches at least 250%. This figure indicates the relative size of the floorplan compared with the net area (excluding interconnect) of the cells it must accommodate. The greater the figure, the smaller the risk that auto-routing will fail.

Now click on the Link item in the Floorplan palette (FP Edit heading). This extracts the cells selected in the hierarchy window into the newly created floorplan shape; the shape will acquire the name ring_receiver.

32. Change the editing context to ring_receiver and set up the cell. We must now complete the creation of the ring_receiver cell and save it so it can

later be placed in the top-level ring_hier cell.

Change the editing context to ring_receiver by giving the following commands: (Menu bar) > Context > Hierarchy > Peek , and OK the resulting prompt bar. The ring_receiver cell should appear shaded.

Now give the command: (Menu bar) > Context > Hierarchy > Set context. Click within the ring_receiver floorplan shape. Observe in the title bar of the design

window that the context has now changed from ring_hier to ring_receiver, and that the floorplan shape is now outlined in green.



Re-attach the library with the following command: (Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib

cell library. OK the dialogue box.

Now use Autofloorplan, Autoplace, & Autoroute to complete the cell. In the Floorplan palette, click on:

• Autofloorplan and OK the dialogue box; • Back, followed by Place & Route (to select the Place & Route palette); • Std Cells (under Autoplace), and OK the dialogue box.

At this stage press Shift+F8 if necessary to view the entire layout. The cells have been placed, but interconnections still need to be routed. You should see networks of yellow overflow links, representing the set of interconnections still to be resolved. Continue with the following commands, from the Floorplan palette:

• Ports (under Autoplace), and OK the dialogue box; • All (under Autoroute), and OK the prompt bar.

Note that ports are virtually invisible when placed at this stage, but they can be seen as small rectangles within the green border around the floor plan shape.

You should now observe a placed and routed block. In most cases ICblocks can automatically generate all the required interconnections using metal1 and/or metal2, but if the structures are complex there is a risk this operation may fail, and you will continue to see yellow overflows. Consult a demonstrator if this is the case.

Save the cell at this point: (Menu bar) File > Cell > Save Cell.


Make sure the cell ring_receiver is selected and the design window is activated before giving the command:

(Menu bar) > Context > Hierarchy > Unpeek. Unplace the ring_receiver part by giving the command: (Menu bar) > Objects > Unplace. Now press function key F2 to de-select all objects.

You are now ready to generate the final cell block (ring_glue), for later placement in ring_hier.



34. Combine the last remaining standard cell/s in the ring_glue block.

In the hierarchy window, select the last remaining cell bearing the code letter S. This should be nor2 only – if you see others you may have overlooked cells earlier!

Re-activate the design window and its associated Floorplan palette. Detach the library with the command: (Menu bar) > File > Library > Detach. Click on the Partition item in the Floorplan palette (under the Hierarchy heading). In the resulting prompt bar, enter ring_glue in the cell_name field. Select the noplace setting for cell_position. OK the prompt bar.

Observe the appearance of a new part, ring_glue.

35. Lay out a floorplan shape for the cell ring_glue. We shall interactively lay out a floorplan shape for the new block.

Make sure ring_glue is selected in the Component Hierarchy window. Then activate the design window and click on Add Fp Shape in the Floorplan palette. In the prompt bar, use the Tab key to outline in red the Shape Extent item. In the design window, with the Select button depressed, drag until the display reaches at least 250%.

Now click on the Link item in the Floorplan palette (FP Edit heading). The shape should acquire the name ring_glue.

36. Change the editing context to ring_glue and set up the cell. Change the editing context to ring_glue by giving the following commands:

(Menu bar) > Context > Hierarchy > Peek , and OK the resulting prompt bar. (Menu bar) > Context > Hierarchy > Set context. Click the ring_glue floorplan. (Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib cell library. OK the dialogue box. Now use Autofloorplan, Autoplace, & Autoroute to complete the cell.

In the Floorplan palette, click on:

• Autofloorplan and OK the dialogue box; • Back, followed by Place & Route (to select the Place & Route palette); • Std Cells (under Autoplace), and OK the dialogue box; • Ports (under Autoplace), and OK the dialogue box; • All (under Autoroute), and OK the prompt bar.

You should now observe a placed and routed block. Save the cell at this point: (Menu bar) File > Cell > Save Cell.

37. Change editing context back to ring_hier. Give the two following menu commands: (Menu bar) > Context > Hierarchy > Set Context Up, and OK the prompt bar.

Make sure the cell ring_glue is selected and the design window is activated before giving the command:

(Menu bar) > Context > Hierarchy > Unpeek. Unplace the ring_count part by giving the command: (Menu bar) > Objects > Unplace. Now press function key F2 to de-select all objects.

You are now ready to lay out the top level cell ring_hier.



38. Place the three cell blocks in ring_hier, and try to add the I/O ports. In the Place & Route palette, click the Blocks item. The Autoplace Blocks dialogue

box should appear. No changes should be required to the entries in this dialogue; OK the dialogue box. The five blocks: ring_count, ring_receiver, ring_transmitter, ring_array and ring_glue should appear in the design window.

Give the command: (Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib cell library. OK the dialogue box.

Attempt to add the I/O pads. Select all the remaining items (marked E) in the Hierarchy Window. Then, with the design window active, click on the Ports item (under the heading Autoplace) in the Place & Route palette. Choose Selected for the Place item, and OK the dialogue box.

If you are fortunate, the port placement will proceed without problem. If so, move on to paragraph 39. However, because of the new constraints on the shape of the core logic blocks brought about by our use of a hierarchical structure, it is quite possible that the port placement will fail. One or two pads may be left unplaced - see the Hierarchy Window for pad cells with a remaining E code, signifying unplaced. If more than two I/O pads are unplaced, consult a demonstrator!

To circumvent this difficulty, should it arise, study the floorplan. You should be able to see that by stretching the green floorplan shapes at the edges of the layout it will be possible to make space for the remaining ports. Select each of the shapes in turn, and use the (Menu bar) > Edit > Stretch command to stretch the shape upwards, downwards, left or right, as appropriate, to make it large enough to accommodate further I/O pads.

Then, with the design window active, re-attempt port placement. Select the few remaining unplaced pad items in the Hierarchy Window, and click the Ports item. Ensure that the Place field is still set to Selected. All ports should now be placed.

39. Automatically route the layout. At this point a special procedure is necessary to circumvent an inconsistency (bug!) in

the way ICgraph handles the I/O ports and pads. Give the following commands. With the cursor anywhere over the design window, type in the following (a text bar

will automatically appear as you type): load userware followed by Enter. In the resulting prompt bar, enter the string: delete_unplaced_ports.ample in the

filename field. Check that scope name is set to user_ic and language is set to ample. OK the bar. Then, with the cursor over the design window, type in:

delete_unplaced_ports() - paying heed to the empty brackets - followed by Enter. This procedure removes unwanted port references which will otherwise prevent

routing from completing successfully.

Finally, autoroute the entire layout. Under the Autoroute heading in the Place & Route palette, click on All. A prompt bar should appear at the foot of the screen. For the moment do not change any of the options, but click OK. In approximately 30 seconds (dependent upon system loading) the circuit should be fully routed.

Inspect the layout, using the peek facility if needed, and again make an assessment of the efficiency of the placement and routing, in comparison with the flattened version. Make a note of its total X and Y dimensions. This information is available in the output generated by the following command:

(Menu bar) > Report > Active > Context.

At this stage it is wise to save the cell, using the command: (Menu bar) > File > Cell > Save Cell.



Be sure to reserve it for edits before continuing.

40. Check for remaining overflows and attempt to route them manually It is possible that ICblocks will have been unable to complete the routing for every net in this final operation, and yellow overflows may be visible. If the number of overflows is small, it may be worth routing these individually. Select one of the overflows by left-clicking it. In the Place and Route Palette, choose the Overflow option under the Autoroute heading; when the prompt bar appears, choose Probe Extent and use the mouse to sketch out a generous box surrounding of the overflow. OK the prompt. If this procedure is effective, try it on any remaining overflows. Otherwise, ask a demonstrator for advice.

41. Carry out via minimisation and compaction. Via minimisation and compaction can now be carried out as described in paragraphs 9

and 10 earlier. If you attempt these, monitor the reduction in the number of vias and the design dimensions as you pass through the various phases.

Note that compaction applied to ring_hier is unlikely to produce such a dramatic improvement as was observed with ring_flat. In order to achieve significant compaction with the hierarchical layout, it is necessary to apply the process to each of the logic blocks viz. manchester_receiver, manchester_transmitter, ring_oscillator, 4bit_counter and ring_glue, before beginning routing of ring_hier. If you wish to attempt this additional refinement, consult a demonstrator.

42. Generate a checkplot of the design. You will probably wish to generate a checkplot of the output. It should be possible to

direct one copy of this (per designer) to a colour printer. Please do not exceed this number, as the colour printer takes several minutes to produce a single output sheet.

To generate a colour (or black-and-white) plot, follow the instructions in paragaph 12.

computer-based project on vlsi design co 3/7dmh/ptiiavlsi/pdf/2004/c7lab8.pdf · 2004-04-21 ·...

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