computer architecture seminar
TRANSCRIPT
![Page 1: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/1.jpg)
Data-Triggered ThreadsEliminating Redundant Computation
Hung-Wei Tseng and Dean M. TullsenDepartment of Computer Science and Engineering
University of California, San Diego
(HPCA 2011)
Seminar by: Naman Kumar for http://carg.uwaterloo.ca
![Page 2: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/2.jpg)
Eliminating Redundant Computation
Silent Store:A memory store operation that does not change the contents at that location
20-68% of all stores are silent [Lepak and Lipasti]
How about eliminating the entire stream of computation surrounding a silent store!
![Page 3: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/3.jpg)
Eliminating Redundant Computation
Redundant loads: silent stores result in redundant loads
(last time this load loaded this address, it fetched the same value)
SPEC2000 C:– 78% of all loads are
redundant– 50% of all instructions
depend on redundant loads
![Page 4: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/4.jpg)
Data-Triggered Threads
![Page 5: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/5.jpg)
DTT: Implementation
Place redundant computation in a separate thread:• Thread is restartable• Thread may be aborted/restarted multiple times• Thread management is through architectural changes.• Easy to verify data races as thread life is between time
between triggering store and main thread join point.
The Programming Model
![Page 6: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/6.jpg)
DTT: ImplementationThe Programming Model
Trigger is placed in data section, not code section
![Page 7: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/7.jpg)
DTT: ImplementationThe Programming Model
Main Thread
![Page 8: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/8.jpg)
DTT: ImplementationThe Programming Model
Support thread
![Page 9: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/9.jpg)
• Thread registry (table)
• Thread Queue (table)
• Thread Status Table (table) PC
DTT: ImplementationArchitectural Support
PC of DTT Start PC Destination PC Post skip PC
PC of DTT Start PC Triggering Addr
Stack Pointer Global Pointer
Start PC Destination PC Triggering Addr Output Value
Following tables are all implemented in hardware
![Page 10: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/10.jpg)
• tstore – generate thread when mem modified is not silent
• tspawn – spawn the thread using thread registry
• treturn – finish execution of the current thread
• tcancel – terminate a running thread
DTT: ImplementationArchitectural Support
ISA modifications
![Page 11: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/11.jpg)
![Page 12: Computer Architecture Seminar](https://reader036.vdocuments.us/reader036/viewer/2022062308/558eca781a28ab1c3c8b462d/html5/thumbnails/12.jpg)