Computer ArchitectureTime Allotted: 3 Hours Full Marks: 70

GROUP-A(Multiple Choice Type Questions)

1. Choose the correct alternative 10 X 1= 10

i) Consider the high speed 40ns memory cache with a successful hit ratio of 80ns.The regular memory has an access time of 100ns.What is the effective access time for CPU to access memory?

1 52 ns2 60 ns3 70 ns

4 80 ns

ii) The vector stride value is required to

1 deal with the length of vectors2 access the elements in multi-

dimensional vectors

3 find the parallelism in vectors4 execute vector instruction

iii) Superscalar processor has CPI of

1 Less than 12 More than 13 More than 2

4 More than 3

iv) How many stages does MMX pipeline have?

1 22 43 6

4 12

v) If a program of 15000 instructions, is being executed by a linear 5 stage pipelined processor with a clock rate of 25 MH, then the speed up of this pipeline when compared to an equivalent non pipelined processor is

1 2.332 4.993 3

4 5.4

vi) Power PC 601 uses

1 2-way set associative mapped cache 2 8-way set associative mapped cache 3 Direct mapped cache

4 Fully associative cache

vii) Which of the following architecture is not suitable for realizing SIMD architecture?

1 Vector processor2 Array processor3 Von-neuman machine

4 All of these

viii) The CPU of RISC processor is controlled by

1 Control memory2 Hardware without control memory

3 RAM4 None of these

1

ix) Which one of the following network provides the highest bandwidth and interconnection capability?

1 Crossbar network2 Multistage network3 Bus system network

4 None of these

x) In a virtual memory system, the address space specified by the address lines of the CPU must be _________ than the physical memory size, ad __________ than the secondary storage size

1 Smaller, smaller2 Smaller, larger3 Larger, smaller

4 Larger, larger

Group B(Short answer type question)

(Answer any three) 3x5=15

1 Write down difference between RISC and CISC architecture 52 The largest configuration of CRAY T90 has 32 processor, each capable of generating 4

loads and 2 stores per clock cycle. The processor clock cycle length is 2.167ns and cycle time for SRAMs used is 15 ns. Calculate the minimum number of memory banks required to allow all processors to run full memory bandwidth.

5

3 What are the Branch Prediction techniques used while designing a pipelined processor? 54 Following performance measures were recorded while running a machine.

Calculate the CPI and MIPS for this machine assuming the clock rate to be 200 MHz.

5

5 How can you classify conventional computers based on their program flow mechanism? Give examples of each category.

5

Group C(Long answer type question)

(Answer any three) 3x15=45

1 a) 1 2 3 4 5 6S1 X XS2 X XS3 XS4 X X

Considering the given reservation table, write down the forbidden latencies and initial collision vector. Draw the state diagram for scheduling the pipeline. Find out the sample cycle, greedy cycle and MAL. If the pipeline clock rate is 50MHz.What is the throughput

6

2

Instruction Category Percentage of occurrence Number of cycles/instructionALU 35 1LOAD & STORE 30 2BRANCH 15 3OTHERS 20 5

of the pipeline? What are the bounds on MAL?b) State and discuss different pipelined data hazards. 4c) What do you mean by internal data forwarding? Give example. 3d) Calculate the optimal performance/cost ration for a pipelined processor. 2

2 a) Draw and explain the architecture of a typical vector processor 4b) What are meant by Horizontal and Vertical vector processing? Find out speed up of

horizontal processing over uni processing?5

c) Consider a vector computer which can operate in one of two execution mode at a time: one in vector mode with an execution rate of Rv = 10 MFLOPS, and the other is a scalar mode with execution rate of Rs= 1 MFLOPS. Derive and expression for average execution rate Ra for this machine. Determine the vectorization ratio α needed in order to achieve Ra= 7.5 MFLOPS.

6

3 a) Suppose in 1000 memory references there are 40 misses in the 1st level cache and 20 misses in the 2nd level cache. Find out local and global miss rates for both the caches. Assume that miss penalty for L2 cache to memory is 100 clock cycles, hit time of L2 cache is 10 clock cycles, hit time for L1 cache is 1 clock cycle and there are 1.5 memory references per instruction. Find out average memory access time and average stall cycles per instruction. Ignore the write-impact.

6

b) How can you improve cache performance by reducing miss rates of caches? 5c) A two-way set-associative cache memory uses blocks of 4 words. The cache can

accommodate total of 2048 words from main memory. The main memory size is 128K X 32. Find the tag and index size for the cache. What is the size of t the cache?

4

4 a) Describe 8x8 Omega Network with the following permutation using 2x2 switches ∏ = (0,7,6,4,2)(1,3)(5)

4

b) What are the main differences between multicomputer and multiprocessor? 3

c) Differentiate between static and dynamic interconnections network. Give example of each.

5

d) What are the advantages of message-passing technology? 35 Write short notes on any 3 3x5

a) CM 2b) Systolic array for parallel processorc) Worm hole routingd) Write through and write back cachee) C-access memory

3