computer architecture lab

25
1 ﺧﺪﺍ ﻧﺎﻡ ﺑﻪ®Ë ÉZ Ã{ZÌa ¥|Å ÃZ´ËZ»M ¾ËY { CPU É 4 |Z^Ì» ÊfÌ] . dz ¶«Y|u dY Ã| Ê  s ¾ËY { °¸¼ Z] ÊËZÀM dÆm ¹Ó Y§Y ®Ë ¦¸fz» ÉYmY { CPU |Z] ÄfY{ {ÂmÁ . Y¿Y ÉZ Ã{ZÌa ½Z°»Y |Z] \ZÀf» ºnu ÉYY{ É|À] ºÌ Zv· Y ʧ Y Á ÄfY{ Y ¶¼ ·YÂf{ . ÉZÅ ÄYe Y Y|» ÊuY { Âf» ʳ{§ t Z] MSI dY Ã| Ã{Z¨fY . Y |ÀeZ^ ÊZY ¥Y|ÅY ʸ¯ Â] : Ã{ZÌa ÃÂv¿ Z] ÊËZÀM ®Ë ÉZ CPU µÁY ¹|« Y ÃYÂz·{ ½Z»Z Z] ÃZ´ËZ»M { ʸ¼ cÂ] ¹Y³ÁaÁ°Ì» Á] µfÀ¯ |uYÁ ÉZ Ã{ZÌa ÃZ³~³ ¹Âƨ» Z] ʸ¼ ÊËZÀM Data Bus Ê·fÀ¯ ħZu ½YÂÀ ] ÉË Ä»Z¿] ¶]Z« ÉZŠħZu Z] ÊËZÀM ÉZÆÅZ´f{ Z] ÊËZÀM PROGRAMMER Á ERASER Á TESTER M Âf» ʳ|ÌrÌa Z] µZfÌnË{ cYY|» Ê]ZË ÉZÆÁ Z] ÊËZÀ ¶¼ ·YÂf{Ë ÊuY Ã| ÊuY ºfÌ ÉZÆf̸]Z« ZY ] ÃYÂz·{ ÉZÅ ¶¼ ·YÂf{ ÊuY Z] Zy Â] Y§Y dz ÊuY ÉZÅY§Y ¹¿Z] ÊËZÀM MAXPLUS II cY¯~e ÄË~¤e ¾f] ÃÂv¿ : { b»Zm {| ZÆq µZeY Z] |ÌËZ¼¿ ÉZe Y ÄË~¤e ÉZƨË{ {Â]{] Å . ÄÌÂe ÉY] \Ìee Ä] ¾ÌËZa Ä] ÓZ] Y Y ¦Ë{ ZÆq {ÂÌ» Gnd , Vcc , Gnd , Vcc |ÌËZ¼¿ Ã{Z¨fY . ¾ËY Ä] {Â] |ÅYÂy ¾°¼» ºÌ ¾ËfÅZe¯ Z] ÄYe j¯Y ÉY] ÄË~¤e µZeY \Ìee . |¿YÂfÌ» ¥ Å Y {Â] {] Å ¶f» ´Ë{ {Â] {] ®Ë Ä] . Ê´f§Á§ Á Ã|WY ¾ËY ÉY] dY Ã| ÊÀÌ] Ìa µZeY ÉY] ÊËZÅ . ÃZ´ËZ»M ¾ËY Y|» {ZË ºnu Ä] ÄmÂe Z] , ĸm Å { d] |ÌÅYÂy Y ½M Y Êf¼« . tÌv dÆm Z] Y ½M |Ë|m {Â]{] ®Ë ÉÁ Ä] Á Y ¶^« ËÌ´] d{ { µZeY ÉY] | . GND VCC GND VCC

Upload: zelham

Post on 16-Oct-2014

78 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: Computer Architecture Lab

1

به نام خدا

CPU 4 . CPU .

. MSI .

:

CPU Data Bus PROGRAMMER ERASER TESTER MAXPLUS II

: . Gnd Vcc Gnd Vcc .

.

. .

. .

GND

VCC

GND

VCC

Page 2: Computer Architecture Lab

2

5v

.

. –

– .... . .

. IC

IC . . IC .

IC IC .

)5 6 ( .

IC . 80 % IC

IC . IC

. .

GND

. )

( LED . LED .

IC .

Page 3: Computer Architecture Lab

3

طرح کلی مدار

CPU )1 ( . A B C D AR PC IR OUTP

INP ALU SHIFTER RAM . )1 ( .

CPU )2 ( . )3 ( CPU .

.

Part

Refrence

U14 A 74173 REG AU15 B 74173 REG BU16 C 74173 REG CU17 D 74173 REG DU18 AR 74173 Address RegisterU19 PC 74173 Program CounterU20 OUTR 74173 Output RegisterU21 IR 74173 Instruction RegisterU25 INB 74244 Input BufferU24 SHFT 74178 Shift RegisterU25 BUF 74244 BufferU22 ALU 74181 Arithmetic & Logic UnitU8 CAR 74374 Control Address RegisterU2 MUX11 74253 Multiplexer 1U3 MUX12 74253 Multiplexer 2U4 MUX13 74253 Multiplexer 3U5 MUX14 74253 Multiplexer 4U1 SBR 74374 Subroutine RegisterU7 ADR1 7483 Adder 1U6 ADR2 7483 Adder 2U26 BUS SEL 74138 Bus sellectorU13 LD SEL 74138 Load SelectorU11 CM1 2864 Control Memory 1U10 CM2 2864 Control Memory 2U9 CM3 2864 Control Memory 3U12 NOT 7404 Inverter

)1 (

Page 4: Computer Architecture Lab

4

)2 (

3 2 1 0

A

B MUX1

CAR

CONTROL MEMORY

MICRO OP CD BR ADF

SBR

INCREMENTER

LOGIC

MUX2

CONDITION SELECT

INSTRUCTION MAP

T

M

8

8

8

8

8

8

3 2

8

A B DC

AR

PC IR

OUTR

INBRAM 16×4Bit Shift

3-State BUF

ALU

BUS

ABC

خروجی

ورودی

)1 ( CPU 4

MAP

Page 5: Computer Architecture Lab

5

FR

OM

MA

P

CO

NT

RO

L M

EM

OR

Y 3

INB

INP

UT

RE

G A

RE

G C

RE

G B

CA

R

BU

S

OU

TR

TO

MA

P

CO

NT

RO

L M

EM

OR

Y 1

INC

RE

ME

NT

ER

SB

R

BU

S

AR

IR

RA

M

SE

L

PC

CO

NT

RO

L M

EM

OR

Y 2

RE

G DB

UF

AL

U

OU

TP

UT

MU

LT

IPL

EX

ER

VCC

VCC

VCC

VC

C

VCC

U24

74178

SE

R3

A2

B1

C13

D12

CLK

5

SH

IFT

11

LOA

D9

QA

4

QB

6

QC

8

QD

10

U10

2864

A0 10A1 9A2 8A3 7A4 6A5 5A6 4A7 3A8 25A9 24A10 21A11 23A12 2CE 20OE 22WE 27

D011 D112 D213 D315 D416 D517 D618 D719

RDY/B1

U9

2864

A0 10A1 9A2 8A3 7A4 6A5 5A6 4A7 3A8 25A9 24A10 21A11 23A12 2CE 20OE 22WE 27

D011 D112 D213 D315 D416 D517 D618 D719

RDY/B1

U15

74LS173

D1 14D2 13D3 12D4 11CLK 7OE2 1OE1 2IE1 9IE2 10CLR 15

Q13 Q24 Q35 Q46

U20

74LS173

D1 14D2 13D3 12D4 11CLK 7OE2 1OE1 2IE1 9IE2 10CLR 15

Q13 Q24 Q35 Q46

U7

7483

A110 A28 A33 A41B111 B27 B34 B416C013

S1 9S2 6S3 2S4 15

C4 14

U1

74LS374

D0

3

D1

4

D2

7

D3

8

D4

13

D5

14

D6

17

D7

18

OC

1

CLK

11

Q0

2

Q1

5

Q2

6

Q3

9

Q4

12

Q5

15

Q6

16

Q7

19

U17

74LS173

D1 14D2 13D3 12D4 11CLK 7OE2 1OE1 2IE1 9IE2 10CLR 15

Q13 Q24 Q35 Q46

U13

74LS138

A1

B2

C3

G1

6

G2A

4

G2B

5

Y0

15

Y1

14

Y2

13

Y3

12

Y4

11

Y5

10

Y6

9

Y7

7

U8

74LS374

D0

3

D1

4

D2

7

D3

8

D4

13

D5

14

D6

17

D7

18

OC

1

CLK

11

Q0

2

Q1

5

Q2

6

Q3

9

Q4

12

Q5

15

Q6

16

Q7

19

U11

2864

A0 10A1 9A2 8A3 7A4 6A5 5A6 4A7 3A8 25A9 24A10 21A11 23A12 2CE 20OE 22WE 27

D011 D112 D213 D315 D416 D517 D618 D719

RDY/B1

U18

74LS173

D1 14D2 13D3 12D4 11CLK 7OE2 1OE1 2IE1 9IE2 10CLR 15

Q13 Q24 Q35 Q46

U2

74LS253

1C0 61C1 51C2 41C3 32C0 102C1 112C2 122C3 13

A 14B 21G 12G 15

1Y7

2Y9

R1

R

U3

74LS253

1C0 61C1 51C2 41C3 32C0 102C1 112C2 122C3 13

A 14B 21G 12G 15

1Y7

2Y9

U22

74181-1

A0A1A2A3

B0B1B2B3

CN

S0

S1

S2

S3

M

F0F1F2F3

A=B

CN+4G

P

U25

74LS244

1A1

2

1A2

4

1A3

6

1A4

8

2A1

11

2A2

13

2A3

15

2A4

17

1G1

2G19

1Y1

18

1Y2

16

1Y3

14

1Y4

12

2Y1

9

2Y2

7

2Y3

5

2Y4

3

U14

74LS173

D1 14D2 13D3 12D4 11CLK 7OE2 1OE1 2IE1 9IE2 10CLR 15

Q13 Q24 Q35 Q46

U16

74LS173

D1 14D2 13D3 12D4 11CLK 7OE2 1OE1 2IE1 9IE2 10CLR 15

Q13 Q24 Q35 Q46U

12B7404

34

U4

74LS253

1C0 61C1 51C2 41C3 32C0 102C1 112C2 122C3 13

A 14B 21G 12G 15

1Y7

2Y9

U23

74C189

D0 4D1 6D2 10D3 12A0 1A1 15A2 14A3 13CS 2R/W' 3

Q05 Q17 Q29 Q311

U19

74LS173

D1 14D2 13D3 12D4 11CLK 7OE2 1OE1 2IE1 9IE2 10CLR 15

Q13 Q24 Q35 Q46

U6

7483

A110 A28 A33 A41B111 B27 B34 B416C013

S1 9S2 6S3 2S4 15

C4 14

U12A

7404

12

U5

74LS253

1C0 61C1 51C2 41C3 32C0 102C1 112C2 122C3 13

A 14B 21G 12G 15

1Y7

2Y9

U21

74LS173

D1 14D2 13D3 12D4 11CLK 7OE2 1OE1 2IE1 9IE2 10CLR 15

Q13 Q24 Q35 Q46

U26

74LS138

A1

B2

C3

G1

6

G2A

4

G2B

5

Y0

15

Y1

14

Y2

13

Y3

12

Y4

11

Y5

10

Y6

9

Y7

7

)3 (

Page 6: Computer Architecture Lab

6

)1( : CPU A B C D ALU

Data Bus . )4(

ALU

REG A REG B REG C REG D

BUF

SHIFTER

U13

74LS138

A1

B2

C3

G16

G2A4

G2B5

Y0 15

Y1 14

Y2 13

Y3 12

Y4 11

Y5 10

Y6 9

Y7 7

U12A

7404

1 2U12B

7404

3 4

U1574LS173

D1

14D

213

D3

12D

411

CLK

7O

E21

OE1

2IE1

9IE2

10C

LR15

Q1

3Q

24

Q3

5Q

46

U1774LS173

D1

14D

213

D3

12D

411

CLK

7O

E21

OE1

2IE1

9IE2

10C

LR15

Q1

3Q

24

Q3

5Q

46

U1474LS173

D1

14D

213

D3

12D

411

CLK

7O

E21

OE1

2IE1

9IE2

10C

LR15

Q1

3Q

24

Q3

5Q

46

U1674LS173

D1

14D

213

D3

12D

411

CLK

7O

E21

OE1

2IE1

9IE2

10C

LR15

Q1

3Q

24

Q3

5Q

46

U25

74LS244

1A12

1A24

1A36

1A48

2A111

2A213

2A315

2A417

1G1

2G19

1Y1 18

1Y2 16

1Y3 14

1Y4 12

2Y1 9

2Y2 7

2Y3 5

2Y4 3

U24

74178

SER3

A2

B1

C13

D12

CLK5

SHIFT11

LOAD9

QA 4

QB 6

QC 8

QD 10

U2274181

A0A1A2A3 B0B1B2B3CN

S0S1S2S3M

F0F1F2F3

A=B

CN

+4G P

فعالیت های قبل از آزمایش1- )4 ( Data Book IC

. 2- )4 ( . . 3- ALU . 4- ) ( . 5- 74244 74178 6- ALU Load

7-

.

)4 ( 1

Page 7: Computer Architecture Lab

7

انجام آزمایش1- )4 ( . 2- CLOCK PULSE )5 ( .

VCC

7404

5 6

7404

98

clk

3-

( A B C D . ( . ( ALU AND ... . ( ALU Load

. ( A B C D .

تهیه گزارش کار

)5 (

Page 8: Computer Architecture Lab

8

)2( : NEXT ADDRESS GENERATOR CPU :

CONTROL MEMORY (2864×3) CONTROL ADDRESS REGISTER (CAR) 74374 INCREMENTER (7483×2)

. SEQUENTIAL JUMP CALL RETURN ..

CONTROL MEMORY 3 CONTROL MEMORY 2 CONTROL MEMORY 1

INCREMENTER

CAR

VCCVCCVCC

U8

74LS374

D03

D14

D27

D38

D413

D514

D617

D718

OC1

CLK11

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

U67483

A1

10A

28

A3

3A

41

B1

11B

27

B3

4B

416

C0

13

S1

9

S2

6

S3

2

S4

15

C4

14

U112864

A0

10

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

A8

25

A9

24

A10

21

A11

23

A12

2

CE

20

OE

22

WE

27

D0

11D

112

D2

13D

315

D4

16D

517

D6

18D

719

RD

Y/B

1

U102864

A0

10

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

A8

25

A9

24

A10

21

A11

23

A12

2

CE

20

OE

22

WE

27

D0

11D

112

D2

13D

315

D4

16D

517

D6

18D

719

RD

Y/B

1

U92864

A0

10

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

A8

25

A9

24

A10

21

A11

23

A12

2

CE

20

OE

22

WE

27

D0

11D

112

D2

13D

315

D4

16D

517

D6

18D

719

RD

Y/B

1

U7

7483

A1

10A

28

A3

3A

41

B1

11B

27

B3

4B

416

C0

13

S1

9

S2

6

S3

2

S4

15

C4

14

فعالیت های قبل از آزمایش

1- )6 ( Data Book IC .

2- )6 ( . . 3- 7483 . 4- C0 C4 7483 . 5- RESET CLK OC

74374 . 6- )3 ( CONTROL MEMORY 1 DATA BUS

)6 ( 2

Page 9: Computer Architecture Lab

9

7- . A D .

B C A . 8- 1 7

.

انجام آزمایش1- )6 ( . 2- . 3- CLOCK PULSE )5 ( . 4- 2864 . 5- 4 LED .

تهیه گزارش کار

Page 10: Computer Architecture Lab

10

EEPROM3 EEPROM2 EEPROM1 Binary Code Hex Binary Code Hex Binary Code Hex

LBL ASSEMBLY

AD

DR

ES

Page 11: Computer Architecture Lab

11

)3( : RAM CPU . )7 ( .

. ADDRESS REGISTER (AR) 74173 PROGRAM COUNTER (PC) 74173 OUTPUT REGISTER (OUTR) 74173 INSTRUCTION REGISTER (IR) 74173

BUS 74138 IR . OUTR 4 LED .74189

RAM 16 . AR RAM .74189 .

OUTRPCAR IR

RAMOUTPUT

BUS SEL

TO MAP

U1874LS173

D1

14D

213

D3

12D

411

CLK

7O

E21

OE1

2IE1

9IE2

10C

LR15

Q1

3Q

24

Q3

5Q

46

U1974LS173

D1

14D

213

D3

12D

411

CLK

7O

E21

OE1

2IE1

9IE2

10C

LR15

Q1

3Q

24

Q3

5Q

46

U2374C189

D0

4D

16

D2

10D

312

A01

A115

A214

A313

CS

2R

/W'

3

Q0

5Q

17

Q2

9Q

311

U2074LS173

D1

14D

213

D3

12D

411

CLK

7O

E21

OE1

2IE1

9IE2

10C

LR15

Q1

3Q

24

Q3

5Q

46

U2174LS173

D1

14D

213

D3

12D

411

CLK

7O

E21

OE1

2IE1

9IE2

10C

LR15

Q1

3Q

24

Q3

5Q

46

1K

U26

74LS138

A 1

B 2

C 3

G1 6

G2A 4

G2B 5

Y015

Y114

Y213

Y312

Y411

Y510

Y69

Y77

فعالیت های قبل از آزمایش1- Data Book 74189 . 2- )7 ( . . 3- 74138 . .

. 4- 74173 .

)7 ( 3

Page 12: Computer Architecture Lab

12

5- RAM )INSTRUCTION

FETCH ( . . 6- )3( )7 ( . 7- .

A D . B C A .

A D . 8- 1 7

.

انجام آزمایش1- )7 ( . 2- . 3- . 4- 2864 . 5- 4 LED .

تهیه گزارش کار

Page 13: Computer Architecture Lab

13

EEPROM3 EEPROM2 EEPROM1 Binary Code Hex Binary Code Hex Binary Code Hex

LBL ASSEMBLY

AD

DR

ES

Page 14: Computer Architecture Lab

14

)4( : JUMP CALL RETURN .

. 1- )CONTROL MEMORY( . 2- )NEXT ADDRESS GENERATOR ( CAR SBR MUX1

LOGIC . )8 (

.CAR . CAR MAX1 .

3 2 1 0

A

B MUX1

CAR

CONTROL MEMORY

MICRO OP CD BR ADF

SBR

INCREMENTER

LOGIC

MAX2

CONDITION SELECT

INSTRUCTION MAP

T

M

8

8

8

8

8

8

3 2

8

)8 (

Page 15: Computer Architecture Lab

15

( )INCREMENTER ( . ( ADDRESS FIELD JUMP CALL . ( SBR . CALL SBR

RET . ( . MACRO

INSTRUCTION . A B MAX1 . LOGIC A B

. LOGIC SBR . BR CD

)9 ( . 4 74253) ( 74374 SUBROUTINE REGISTER (SBR) 2) 6 ( 9 .

VCCVCCVCC

VCC

CONTROL MEMORY 1CONTROL MEMORY 2CONTROL MEMORY 3

CAR

INCREMENTER

MULTIPLEXER

SBR

FROMMAP

U102864

A010

A19

A28

A37

A46

A55

A64

A73

A825

A924

A1021

A1123

A122

CE

20O

E22

WE

27

D0

11D

112

D2

13D

315

D4

16D

517

D6

18D

719

RD

Y/B1

U574LS253

1C0

61C

15

1C2

41C

33

2C0

102C

111

2C2

122C

313

A14

B2

1G1

2G15

1Y7

2Y9

U92864

A010

A19

A28

A37

A46

A55

A64

A73

A825

A924

A1021

A1123

A122

CE

20O

E22

WE

27

D0

11D

112

D2

13D

315

D4

16D

517

D6

18D

719

RD

Y/B1

U274LS253

1C0

61C

15

1C2

41C

33

2C0

102C

111

2C2

122C

313

A14

B2

1G1

2G15

1Y7

2Y9

U8

74LS374

D03

D14

D27

D38

D413

D514

D617

D718

OC1

CLK11

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

U67483

A110

A28

A33

A41

B111

B27

B34

B416

C0

13

S19

S26

S32

S415

C4

14

U374LS253

1C0

61C

15

1C2

41C

33

2C0

102C

111

2C2

122C

313

A14

B2

1G1

2G15

1Y7

2Y9

U77483

A110

A28

A33

A41

B111

B27

B34

B416

C0

13

S19

S26

S32

S415

C4

14

U1

74LS374

D0 3

D1 4

D2 7

D3 8

D4 13

D5 14

D6 17

D7 18

OC 1

CLK 11

Q02

Q15

Q26

Q39

Q412

Q515

Q616

Q719

U474LS253

1C0

61C

15

1C2

41C

33

2C0

102C

111

2C2

122C

313

A14

B2

1G1

2G15

1Y7

2Y9

U112864

A010

A19

A28

A37

A46

A55

A64

A73

A825

A924

A1021

A1123

A122

CE

20O

E22

WE

27

D0

11D

112

D2

13D

315

D4

16D

517

D6

18D

719

RD

Y/B1

)9 ( 4

Page 16: Computer Architecture Lab

16

فعالیت های قبل از آزمایش1- Data Book 74253 2- )9 ( . . 3- )9 ( . 4- LOGIC :

T=1 JUMP TO BR1 BR0 = 00 T=0 NEXT ADDRESS BR1 BR0 = OTHER NEXT ADDRESS

3 A T .

5- )8 ( )9 ( 6- .

D . D 6 ) A (

. 7- 1 6

.

انجام آزمایش1- )9 ( . 2- . 3- 2864 . 4- TRACE .

تهیه گزارش کار

Page 17: Computer Architecture Lab

17

EEPROM3 EEPROM2 EEPROM1 Binary Code Hex Binary Code Hex Binary Code Hex

LBL ASSEMBLY

AD

DR

ES

Page 18: Computer Architecture Lab

18

)5( : LOGIC JUMP CALL RETURN MAP.

( JUMP : BR1 BR0 00 JUMP . )ADF ( CAR CAR

. . T . 3 CD (CONDITION) . .

( CALL : BR1 BR001 CALL . JUMP LOAD ADF CAR INCREMENTER SBR .SBR .CALL T .

T 3 CD . ( RETURN : BR1 BR0 10 RET .

LOAD SBR CAR SBR CALL .

( MAP : BR1 BR0 10 MAP . . LOAD CAR .MAP FETCH . )INSTRUCTION ( )MICRO

INSTRUCTION ( .

MAP .

3 A T . 74151 .74151 8

. CD .

) ( ) (

0 1 IN Q3A 3 A Q0D 0 D A=B ALU

.

0

1

2

3

4

5

6

7

MAX

8×1 74151

CD2 CD1 CD0

‘1’

Q0D

Q3A

~FF2

A=B

FF1

IN

‘0’

T

Page 19: Computer Architecture Lab

19

فعالیت های قبل از آزمایش1- Data Book 74151 2- LOGIC :

T=1 JUMP TO ADF BR1 BR0 = 00 T=0 NEXT ADDRESS T=1 CALL ADF BR1 BR0 = 01 T=0 NEXT ADDRESS BR1 BR0 = 10 RET BR1 BR0 = 01 MAP

A B M

.

BR1 BR0 T B A M

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

3- .

( A D IN .

( A D . ( .

4- 1 3 .

Page 20: Computer Architecture Lab

20

انجام آزمایش1- LOGIC ) 74151 ( . 2- 2864 . 3- TRACE .

تهیه گزارش کار

Page 21: Computer Architecture Lab

21

EEPROM3 EEPROM2 EEPROM1 Binary Code Hex Binary Code Hex Binary Code Hex

LBL ASSEMBLY

AD

DR

ES

Page 22: Computer Architecture Lab

22

)6( : Carry Flag (CF) IO Flag(IOF) . )11 ( CF IOF ClkEn

AND . IOF Hand shaking

. IN ClkEn SC .CF Carry

. CF .

فعالیت های قبل از آزمایش1- Data Book 4053 7474 2- .

( A D . ( 16 . ( .

5- 1 2 .

انجام آزمایش1- 11 4053 7474 . 3- 2864 . 4- TRACE .

تهیه گزارش کار .

SC

ALU

Shifter

MUXA

D Q CF

MUXC

D Q IOF

MUXB

1 0

System SI Shifter SI

SA SB

Input Output Device

)11 (

Page 23: Computer Architecture Lab

23

EEPROM3 EEPROM2 EEPROM1 Binary Code Hex Binary Code Hex Binary Code Hex

LBL ASSEMBLY

AD

DR

ES

Page 24: Computer Architecture Lab

24

)7( : IO Hand Shaking

فعالیت های قبل از آزمایش :

( IO Hand Shaking ( 16 4 RAM

. IN IN IOF .

انجام آزمایش

1- . 2- 2864 ..

تهیه گزارش کار

.

Page 25: Computer Architecture Lab

25

EEPROM3 EEPROM2 EEPROM1

Binary Code Hex Binary Code Hex Binary Code HexLBL ASSEMBLY

AD

DR

ES