Component Design

•By the end of the course each student will design and test a MIPS processor

•Datapath components will be designed and tested in the next few labs (registers, multiplexers, alu’s, etc.)

•Controller will be designed as a state machine

•Controller and datapath will be combined and it will be used to run a machine program

Design and Test Strategy

ReferenceModel

Design

CompareStimulus

Generation

•Each design will be tested by comparison to a reference model

•Reference model should perform exactly as the real design

•Both reference and design receive the same input

Reference Model

Reference model is behavioral, design is structural

•A behavioral design is easier to create and easier to assume correct

Difficulties

•A bug in either the reference model or the design will be detected

•The reference model must be debugged before the design

•The reference model may not be timing-accurate

Reference Model Example

module MUX_behav(f, sel, b, c);output reg f;input sel, a, b;always @ (sel or a or b)

beginif (sel == 1)

f = b;else

f = a;end

endmodule

module MUX_struct (f, a, b, sel);

output f;input a, b, sel;

and #5 g1 (f1, a, nsel),g2 (f2, b, sel);

or #5 g3 (f, f1, f2);not g4 (nsel, sel);

endmodule

Behavioral Reference Model Structural Design

Testbench with Reference Model

module mux_comp (mismatch, in1, in2, sel)

input in1, in2, sel;output mismatch;wire out1, out2;

MUX_behav m1 (out1, in1, in2, sel);MUX_struct m2 (out2, in1, in2, sel);

xor x1 (mismatch, out1, out2);

endmodule

module mux_tb (mismatch)wire in1, in2, sel;output mismatch;

mux_comp m1 (mismatch, in1, in2, sel);

always…

endmodule

•Error is detected by observing the mismatch signal

Reference Model for a Design with Timing

module mult_behav (prod, in1, in2)input [7:0] in1, in2;output [15:0] prod;

res = in1 * in2;

endmodule

module mult_struct (prod, in1, in2, clk)

input [7:0] in1, in2;input clk;output [15:0] prod;

// shift-add algorithm

endmodule

•Design is timing-accurate, reference model is not

•Need to choose the sample points

A Sample Clock

module mult_comp (in1, in2, clk, sclk)

// declare inputs, outputs, wires

mult_behav m1 (out1, in1, in2);mult_struct m2 (out2, in1, in2, clk);

always (sclk)if (out1 != out2) $display(“error);

endmodule

module mult_tbwire in1, in2, clk, sclk;

mult_comp m1 (in1, in2, clk, sclk);

initial clk = 0; sclk = 0;always #5 sclk = ~sclk;always (sclk) #1 clk = ~clk;always

…

endmodule

•Signals must settle just before the clock

•Sample clock rises just before regular clock