complex programmable logic devices ee 365. plds 16v8 (20 pins) can have 16 inputs (max) and/or 8...
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Complex Programmable Logic Devices
EE 365
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PLDs16V8 (20 Pins)
• can have 16 inputs (max) and/or 8 outputs (marcrocells)• has 32 inputs to each of the AND gates (product terms)
22V10 (24 pins)
• can have 22 inputs and/or 10 outputs (max)• has 44 inputs to each of the AND gates How about a “128V64” for larger applications? It will be slower and will more wasted silicon space
Solution? Use CPLDs
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GAL16V8(review seq_1.ppt)
• Each output is programmable as combinational or registered
• Also has programmable output polarity
And PlaneAnd Plane
The OR gatesThe OR gates
XOR gates tomake inverting or
non-inverting buffer
XOR gates tomake inverting or
non-inverting buffer
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A General CPLD structure
A collection of PLDs on a single chip withProgrammble interconnects
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Who makes the CPLDs?
Manufacturer CPLD Products URL
Altera MAX 5000, 7000 & 9000 www.altera.com Altmel ATF & ATV www.atmel.com Cypress FLASH370, Ultra37000 www.cypress.com Lattice ispLSI 1000 to 8000 www.latticesemi.com Philips XPLA www.philips.com Vantis MACH 1 to 5 www.vantis.com Xilinx XC9500 www.xilinx.com
Manufacturer CPLD Products URL
Altera MAX 5000, 7000 & 9000 www.altera.com Altmel ATF & ATV www.atmel.com Cypress FLASH370, Ultra37000 www.cypress.com Lattice ispLSI 1000 to 8000 www.latticesemi.com Philips XPLA www.philips.com Vantis MACH 1 to 5 www.vantis.com Xilinx XC9500 www.xilinx.com
Let’s takes a look at thisLet’s takes a look at this
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The Xilinx 9500-series CPLD
• The internal PLDs are called Configurable Functional Blocks (FBs or CFBs)
• Each FB has 36 inputs and 18 Macrocells (effectively a “36V18”)
• Each CLPD is packaged in a plastic-leaded chip carrier (PLCC)
• The number of I/O pins are much less than the total number of Macrocells in family of devices
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Xinlinx CPLDs
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Architecture of Xilinx 9500-family CPLD
Global set/resetGlobal set/reset
Global 3 state controlGlobal 3 state control
Global ClockGlobal Clock
36 Signal pins36 Signal pins
18 outputs18 outputs
18 Outputenable signals
18 Outputenable signals
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Architecture of Xilinx FB
Most CLPDs have fewer AND terms per macrocellXC9500 has 5 whereas 16V8 has 8 and 22V10 has 8-16
But…each macrocell can use unused ANDs froms its neigboring macrocells using the “product-term-allocators”
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XC9500 Productterm allocator and
macrocell
XC9500 Productterm allocator and
macrocell
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ISPISP
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XC9500 I/O BlockXC9500 I/O Block
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1
• Could be anything from a limited set of multiplexers to a full crossbar.
• Multiplexer -- small, fast, but difficult fitting
• Crossbar -- easy fitting but large and slow
Switch matrix for XC95108
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XC4000E I/O Block